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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_delayed_sync.v] - Blame information for rev 88

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "delayed_sync.v"                                  ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.5  2002/09/25 09:54:50  mihad
// Added completion expiration test for WB Slave unit. Changed expiration signalling
//
// Revision 1.4  2002/03/05 11:53:47  mihad
// Added some testcases, removed un-needed fifo signals
//
// Revision 1.3  2002/02/01 15:25:12  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:28  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//
 
// module provides synchronization mechanism between requesting and completing side of the bridge
`include "pci_constants.v"
`include "bus_commands.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module pci_delayed_sync
(
    reset_in,
    req_clk_in,
    comp_clk_in,
    req_in,
    comp_in,
    done_in,
    in_progress_in,
    comp_req_pending_out,
    req_req_pending_out,
    req_comp_pending_out,
    comp_comp_pending_out,
    addr_in,
    be_in,
    addr_out,
    be_out,
    we_in,
    we_out,
    bc_in,
    bc_out,
    status_in,
    status_out,
    comp_flush_out,
    burst_in,
    burst_out,
    retry_expired_in
);
 
// system inputs
input reset_in,         // reset input
      req_clk_in,       // requesting clock input
      comp_clk_in ;     // completing clock input
 
// request, completion, done and in progress indication inputs
input req_in,           // request qualifier - when 1 it indicates that valid request data is provided on inputs
      comp_in,          // completion qualifier - when 1, completing side indicates that request has completed
      done_in,          // done input - when 1 indicates that requesting side of the bridge has completed a transaction on requesting bus
      in_progress_in ;  // in progress indicator - indicates that current completion is in progress on requesting side of the bridge
 
// pending indication outputs
output  comp_req_pending_out,   // completion side request output - resynchronized from requesting clock to completing clock
        req_req_pending_out,    // request pending output for requesting side
        req_comp_pending_out,   // completion pending output for requesting side of the bridge - it indicates when completion is ready for completing on requesting bus
        comp_comp_pending_out ; // completion pending output for completing side of the bridge
 
// additional signals and wires for clock domain passage of signals
reg     comp_req_pending,
        req_req_pending,
        req_comp_pending,
        req_comp_pending_sample,
        comp_comp_pending,
        req_done_reg,
        comp_done_reg_main,
        comp_done_reg_clr,
        req_rty_exp_reg,
        req_rty_exp_clr,
        comp_rty_exp_reg,
        comp_rty_exp_clr ;
 
wire    sync_comp_req_pending,
        sync_req_comp_pending,
        sync_comp_done,
        sync_req_rty_exp,
        sync_comp_rty_exp_clr ;
 
// inputs from requesting side - only this side can set address, bus command, byte enables, write enable and burst - outputs are common for both sides
// all signals that identify requests are stored in this module
 
input [31:0]    addr_in ;   // address bus input
input [3:0]     be_in ;     // byte enable input
input           we_in ;     // write enable input - read/write request indication 1 = write request / 0 = read request
input [3:0]     bc_in ;     // bus command input
input           burst_in ;  // burst indicator    - qualifies operation as burst/single transfer 1 = burst / 0 = single transfer
 
// common request outputs used both by completing and requesting sides
// this outputs are not resynchronized, since flags determine the request status
output [31:0]   addr_out ;
output [3:0]    be_out ;
output          we_out ;
output [3:0]    bc_out ;
output          burst_out ;
 
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
input          status_in ;
output         status_out ;
 
// input signals that delayed transaction has been retried for max number of times
// on this signal request is ditched, otherwise it would cause a deadlock
// requestor can issue another request and procedure will be repeated
input   retry_expired_in ;
 
// completion flush output - if in 2^^16 clock cycles transaction is not repeated by requesting agent - flush completion data
output  comp_flush_out ;
 
// output registers for common signals
reg [31:0]   addr_out ;
reg [3:0]    be_out ;
reg          we_out ;
reg [3:0]    bc_out ;
reg          burst_out ;
 
// delayed transaction information is stored only when request is issued and request nor completion are pending
wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
    begin
        addr_out  <= #`FF_DELAY 32'h0000_0000 ;
        be_out    <= #`FF_DELAY 4'h0 ;
        we_out    <= #`FF_DELAY 1'b0 ;
        bc_out    <= #`FF_DELAY `BC_RESERVED0 ;
        burst_out <= #`FF_DELAY 1'b0 ;
    end
    else
        if (new_request)
        begin
            addr_out  <= #`FF_DELAY addr_in ;
            be_out    <= #`FF_DELAY be_in ;
            we_out    <= #`FF_DELAY we_in ;
            bc_out    <= #`FF_DELAY bc_in ;
            burst_out <= #`FF_DELAY burst_in ;
        end
end
 
// completion pending cycle counter
reg [16:0] comp_cycle_count ;
 
/*=================================================================================================================================
Passing of requests between clock domains:
request originates on requesting side. It's then synchronized with two flip-flops to cross to completing clock domain
=================================================================================================================================*/
// main request flip-flop triggered on requesting side's clock
// request is cleared whenever completion or retry expired is signalled from opposite side of the bridge
wire req_req_clear = req_comp_pending || (req_rty_exp_reg && ~req_rty_exp_clr) ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_req_clear )
        req_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_in )
        req_req_pending <= #`FF_DELAY 1'b1 ;
end
 
// interemediate stage request synchronization flip - flop - this one is prone to metastability
// and should have setup and hold times disabled during simulation
synchronizer_flop #(1, 0) req_sync
(
    .data_in        (req_req_pending),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_req_pending),
    .async_reset    (reset_in)
) ;
 
// wire for clearing completion side request flag - whenever completion or retry expired are signalled
wire comp_req_pending_clear = comp_req_pending && ( comp_in || retry_expired_in) ;
 
// wire for enabling request flip - flop - it is enabled when completion is not active and done is not active
wire comp_req_pending_ena   = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ;
 
// completion side request flip flop - gets a value from intermediate stage sync flip flop
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_req_pending_clear )
        comp_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_req_pending_ena )
        comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;
end
 
// completion side request output assignment - when request ff is set and completion ff is not set
assign comp_req_pending_out = comp_req_pending ;
 
// requesting side request pending output
assign req_req_pending_out  = req_req_pending ;
/*=================================================================================================================================
Passing of completions between clock domains:
completion originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain
=================================================================================================================================*/
// main completion Flip - Flop - triggered by completing side's clock
// completion side completion pending flag is cleared when done flag propagates through clock domains
wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ;
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_comp_clear )
        comp_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_in && comp_req_pending )
        comp_comp_pending <= #`FF_DELAY 1'b1 ;
end
 
assign comp_comp_pending_out = comp_comp_pending ;
 
// interemediate stage completion synchronization flip - flop - this one is prone to metastability
synchronizer_flop #(1, 0) comp_sync
(
    .data_in        (comp_comp_pending),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_comp_pending),
    .async_reset    (reset_in)
) ;
 
// request side completion pending flip flop is cleared whenever done is signalled or completion counter expires - 2^^16 clock cycles
wire req_comp_pending_clear = done_in || comp_cycle_count[16];
 
// request side completion pending flip flop is disabled while done flag is set
wire req_comp_pending_ena   = ~req_done_reg ;
 
// request side completion flip flop - gets a value from intermediate stage sync flip flop
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_comp_pending_clear )
        req_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_comp_pending_ena )
        req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;
end
 
// sampling FF - used for sampling incoming completion flag from completing side
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_comp_pending_sample <= #`FF_DELAY 1'b0 ;
    else
        req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;
end
 
// requesting side completion pending output assignment
assign req_comp_pending_out = req_comp_pending && ~req_req_pending ;
 
/*==================================================================================================================================
Passing of delayed transaction done signal between clock domains.
Done is signalled by requesting side of the bridge and is passed to completing side of the bridge
==================================================================================================================================*/
// main done flip-flop triggered on requesting side's clock
// when completing side removes completion flag, done flag is also removed, so requests can proceede
wire req_done_clear = ~req_comp_pending_sample ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_done_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( req_done_clear )
        req_done_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( done_in || comp_cycle_count[16] )
        req_done_reg <= #`FF_DELAY 1'b1 ;
end
 
synchronizer_flop  #(1, 0) done_sync
(
    .data_in        (req_done_reg),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_done),
    .async_reset    (reset_in)
) ;
 
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_done_reg_main <= #`FF_DELAY 1'b0 ;
    else
        comp_done_reg_main <= #`FF_DELAY sync_comp_done ;
end
 
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_done_reg_clr <= #`FF_DELAY 1'b0 ;
    else
        comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;
end
 
/*=================================================================================================================================
Passing of retry expired signal between clock domains
Retry expiration originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain
=================================================================================================================================*/
// main retry expired Flip - Flop - triggered by completing side's clock
wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ;
 
// retry expired is a special case of transaction removal - retry expired propagates from completing
// clock domain to requesting clock domain to remove all pending requests and than propagates back
// to completing side to qualify valid new requests
 
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_rty_exp_clear )
        comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( retry_expired_in && comp_req_pending)
        comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
end
 
// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability
synchronizer_flop #(1, 0) rty_exp_sync
(
    .data_in        (comp_rty_exp_reg),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_rty_exp),
    .async_reset    (reset_in)
) ;
 
// request retry expired flip flop - gets a value from intermediate stage sync flip flop
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
        req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ;
end
 
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
        req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
end
 
synchronizer_flop #(1, 0) rty_exp_back_prop_sync
(
    .data_in        (req_rty_exp_reg && req_rty_exp_clr),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_rty_exp_clr),
    .async_reset    (reset_in)
) ;
 
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
        comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ;
end
 
// completion status flip flop - if 0 when completion is signalled it's finished OK otherwise it means error
reg status_out ;
always@(posedge comp_clk_in or posedge reset_in)
begin
    if (reset_in)
        status_out <= #`FF_DELAY 1'b0 ;
    else
    if (comp_in && comp_req_pending)
        status_out <= #`FF_DELAY status_in ;
end
 
// clocks counter - it counts how many clock cycles completion is present without beeing repeated
// if it counts to 2^^16 cycles the completion must be ditched
 
// wire for clearing this counter
wire clear_count = in_progress_in || ~req_comp_pending_out || comp_cycle_count[16] ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
        comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
    else
    if (clear_count)
        comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
    else
        comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ;
end
 
// completion flush output - used for flushing fifos when counter expires
// if counter doesn't expire, fifo flush is up to WISHBONE slave or PCI target state machines
reg comp_flush_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
        comp_flush_out <= #`FF_DELAY 1'b0 ;
    else
        comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ;
end
 
endmodule //delayed_sync

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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_delayed_sync.v] - Blame information for rev 88

Line No.	Rev	Author	Line
1	77	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "delayed_sync.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	88	mihad	`// Revision 1.1 2003/01/27 16:49:31 mihad`
46			`// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.`
47			`//`
48	77	mihad	`// Revision 1.5 2002/09/25 09:54:50 mihad`
49			`// Added completion expiration test for WB Slave unit. Changed expiration signalling`
50			`//`
51			`// Revision 1.4 2002/03/05 11:53:47 mihad`
52			`// Added some testcases, removed un-needed fifo signals`
53			`//`
54			`// Revision 1.3 2002/02/01 15:25:12 mihad`
55			`// Repaired a few bugs, updated specification, added test bench files and design document`
56			`//`
57			`// Revision 1.2 2001/10/05 08:14:28 mihad`
58			`// Updated all files with inclusion of timescale file for simulation purposes.`
59			`//`
60			`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
61			`// New project directory structure`
62			`//`
63			`//`
64
65			`// module provides synchronization mechanism between requesting and completing side of the bridge`
66			`include "pci_constants.v"
67			`include "bus_commands.v"
68
69			`// synopsys translate_off`
70			`include "timescale.v"
71			`// synopsys translate_on`
72
73			`module pci_delayed_sync`
74			`(`
75			`reset_in,`
76			`req_clk_in,`
77			`comp_clk_in,`
78			`req_in,`
79			`comp_in,`
80			`done_in,`
81			`in_progress_in,`
82			`comp_req_pending_out,`
83			`req_req_pending_out,`
84			`req_comp_pending_out,`
85			`comp_comp_pending_out,`
86			`addr_in,`
87			`be_in,`
88			`addr_out,`
89			`be_out,`
90			`we_in,`
91			`we_out,`
92			`bc_in,`
93			`bc_out,`
94			`status_in,`
95			`status_out,`
96			`comp_flush_out,`
97			`burst_in,`
98			`burst_out,`
99			`retry_expired_in`
100			`);`
101
102			`// system inputs`
103			`input reset_in, // reset input`
104			`req_clk_in, // requesting clock input`
105			`comp_clk_in ; // completing clock input`
106
107			`// request, completion, done and in progress indication inputs`
108			`input req_in, // request qualifier - when 1 it indicates that valid request data is provided on inputs`
109			`comp_in, // completion qualifier - when 1, completing side indicates that request has completed`
110			`done_in, // done input - when 1 indicates that requesting side of the bridge has completed a transaction on requesting bus`
111			`in_progress_in ; // in progress indicator - indicates that current completion is in progress on requesting side of the bridge`
112
113			`// pending indication outputs`
114			`output comp_req_pending_out, // completion side request output - resynchronized from requesting clock to completing clock`
115			`req_req_pending_out, // request pending output for requesting side`
116			`req_comp_pending_out, // completion pending output for requesting side of the bridge - it indicates when completion is ready for completing on requesting bus`
117			`comp_comp_pending_out ; // completion pending output for completing side of the bridge`
118
119			`// additional signals and wires for clock domain passage of signals`
120			`reg comp_req_pending,`
121			`req_req_pending,`
122			`req_comp_pending,`
123			`req_comp_pending_sample,`
124			`comp_comp_pending,`
125			`req_done_reg,`
126			`comp_done_reg_main,`
127			`comp_done_reg_clr,`
128			`req_rty_exp_reg,`
129			`req_rty_exp_clr,`
130			`comp_rty_exp_reg,`
131			`comp_rty_exp_clr ;`
132
133			`wire sync_comp_req_pending,`
134			`sync_req_comp_pending,`
135			`sync_comp_done,`
136			`sync_req_rty_exp,`
137			`sync_comp_rty_exp_clr ;`
138
139			`// inputs from requesting side - only this side can set address, bus command, byte enables, write enable and burst - outputs are common for both sides`
140			`// all signals that identify requests are stored in this module`
141
142			`input [31:0] addr_in ; // address bus input`
143			`input [3:0] be_in ; // byte enable input`
144			`input we_in ; // write enable input - read/write request indication 1 = write request / 0 = read request`
145			`input [3:0] bc_in ; // bus command input`
146			`input burst_in ; // burst indicator - qualifies operation as burst/single transfer 1 = burst / 0 = single transfer`
147
148			`// common request outputs used both by completing and requesting sides`
149			`// this outputs are not resynchronized, since flags determine the request status`
150			`output [31:0] addr_out ;`
151			`output [3:0] be_out ;`
152			`output we_out ;`
153			`output [3:0] bc_out ;`
154			`output burst_out ;`
155
156			`// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion`
157			`input status_in ;`
158			`output status_out ;`
159
160			`// input signals that delayed transaction has been retried for max number of times`
161			`// on this signal request is ditched, otherwise it would cause a deadlock`
162			`// requestor can issue another request and procedure will be repeated`
163			`input retry_expired_in ;`
164
165			`// completion flush output - if in 2^^16 clock cycles transaction is not repeated by requesting agent - flush completion data`
166			`output comp_flush_out ;`
167
168			`// output registers for common signals`
169			`reg [31:0] addr_out ;`
170			`reg [3:0] be_out ;`
171			`reg we_out ;`
172			`reg [3:0] bc_out ;`
173			`reg burst_out ;`
174
175			`// delayed transaction information is stored only when request is issued and request nor completion are pending`
176			`wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;`
177			`always@(posedge req_clk_in or posedge reset_in)`
178			`begin`
179			`if (reset_in)`
180			`begin`
181			addr_out <= #`FF_DELAY 32'h0000_0000 ;
182			be_out <= #`FF_DELAY 4'h0 ;
183			we_out <= #`FF_DELAY 1'b0 ;
184			bc_out <= #`FF_DELAY `BC_RESERVED0 ;
185			burst_out <= #`FF_DELAY 1'b0 ;
186			`end`
187			`else`
188			`if (new_request)`
189			`begin`
190			addr_out <= #`FF_DELAY addr_in ;
191			be_out <= #`FF_DELAY be_in ;
192			we_out <= #`FF_DELAY we_in ;
193			bc_out <= #`FF_DELAY bc_in ;
194			burst_out <= #`FF_DELAY burst_in ;
195			`end`
196			`end`
197
198			`// completion pending cycle counter`
199			`reg [16:0] comp_cycle_count ;`
200
201			`/*=================================================================================================================================`
202			`Passing of requests between clock domains:`
203			`request originates on requesting side. It's then synchronized with two flip-flops to cross to completing clock domain`
204			`=================================================================================================================================*/`
205			`// main request flip-flop triggered on requesting side's clock`
206			`// request is cleared whenever completion or retry expired is signalled from opposite side of the bridge`
207			`wire req_req_clear = req_comp_pending \|\| (req_rty_exp_reg && ~req_rty_exp_clr) ;`
208			`always@(posedge req_clk_in or posedge reset_in)`
209			`begin`
210			`if ( reset_in )`
211			req_req_pending <= #`FF_DELAY 1'b0 ;
212			`else`
213			`if ( req_req_clear )`
214			req_req_pending <= #`FF_DELAY 1'b0 ;
215			`else`
216			`if ( req_in )`
217			req_req_pending <= #`FF_DELAY 1'b1 ;
218			`end`
219
220			`// interemediate stage request synchronization flip - flop - this one is prone to metastability`
221			`// and should have setup and hold times disabled during simulation`
222	88	mihad	`synchronizer_flop #(1, 0) req_sync`
223	77	mihad	`(`
224			`.data_in (req_req_pending),`
225			`.clk_out (comp_clk_in),`
226			`.sync_data_out (sync_comp_req_pending),`
227			`.async_reset (reset_in)`
228			`) ;`
229
230			`// wire for clearing completion side request flag - whenever completion or retry expired are signalled`
231			`wire comp_req_pending_clear = comp_req_pending && ( comp_in \|\| retry_expired_in) ;`
232
233			`// wire for enabling request flip - flop - it is enabled when completion is not active and done is not active`
234			`wire comp_req_pending_ena = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ;`
235
236			`// completion side request flip flop - gets a value from intermediate stage sync flip flop`
237			`always@(posedge comp_clk_in or posedge reset_in)`
238			`begin`
239			`if ( reset_in )`
240			comp_req_pending <= #`FF_DELAY 1'b0 ;
241			`else`
242			`if ( comp_req_pending_clear )`
243			comp_req_pending <= #`FF_DELAY 1'b0 ;
244			`else`
245			`if ( comp_req_pending_ena )`
246			comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;
247			`end`
248
249			`// completion side request output assignment - when request ff is set and completion ff is not set`
250			`assign comp_req_pending_out = comp_req_pending ;`
251
252			`// requesting side request pending output`
253			`assign req_req_pending_out = req_req_pending ;`
254			`/*=================================================================================================================================`
255			`Passing of completions between clock domains:`
256			`completion originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain`
257			`=================================================================================================================================*/`
258			`// main completion Flip - Flop - triggered by completing side's clock`
259			`// completion side completion pending flag is cleared when done flag propagates through clock domains`
260			`wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ;`
261			`always@(posedge comp_clk_in or posedge reset_in)`
262			`begin`
263			`if ( reset_in )`
264			comp_comp_pending <= #`FF_DELAY 1'b0 ;
265			`else`
266			`if ( comp_comp_clear )`
267			comp_comp_pending <= #`FF_DELAY 1'b0 ;
268			`else`
269			`if ( comp_in && comp_req_pending )`
270			comp_comp_pending <= #`FF_DELAY 1'b1 ;
271			`end`
272
273			`assign comp_comp_pending_out = comp_comp_pending ;`
274
275			`// interemediate stage completion synchronization flip - flop - this one is prone to metastability`
276	88	mihad	`synchronizer_flop #(1, 0) comp_sync`
277	77	mihad	`(`
278			`.data_in (comp_comp_pending),`
279			`.clk_out (req_clk_in),`
280			`.sync_data_out (sync_req_comp_pending),`
281			`.async_reset (reset_in)`
282			`) ;`
283
284			`// request side completion pending flip flop is cleared whenever done is signalled or completion counter expires - 2^^16 clock cycles`
285			`wire req_comp_pending_clear = done_in \|\| comp_cycle_count[16];`
286
287			`// request side completion pending flip flop is disabled while done flag is set`
288			`wire req_comp_pending_ena = ~req_done_reg ;`
289
290			`// request side completion flip flop - gets a value from intermediate stage sync flip flop`
291			`always@(posedge req_clk_in or posedge reset_in)`
292			`begin`
293			`if ( reset_in )`
294			req_comp_pending <= #`FF_DELAY 1'b0 ;
295			`else`
296			`if ( req_comp_pending_clear )`
297			req_comp_pending <= #`FF_DELAY 1'b0 ;
298			`else`
299			`if ( req_comp_pending_ena )`
300			req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;
301			`end`
302
303			`// sampling FF - used for sampling incoming completion flag from completing side`
304			`always@(posedge req_clk_in or posedge reset_in)`
305			`begin`
306			`if ( reset_in )`
307			req_comp_pending_sample <= #`FF_DELAY 1'b0 ;
308			`else`
309			req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;
310			`end`
311
312			`// requesting side completion pending output assignment`
313			`assign req_comp_pending_out = req_comp_pending && ~req_req_pending ;`
314
315			`/*==================================================================================================================================`
316			`Passing of delayed transaction done signal between clock domains.`
317			`Done is signalled by requesting side of the bridge and is passed to completing side of the bridge`
318			`==================================================================================================================================*/`
319			`// main done flip-flop triggered on requesting side's clock`
320			`// when completing side removes completion flag, done flag is also removed, so requests can proceede`
321			`wire req_done_clear = ~req_comp_pending_sample ;`
322			`always@(posedge req_clk_in or posedge reset_in)`
323			`begin`
324			`if ( reset_in )`
325			req_done_reg <= #`FF_DELAY 1'b0 ;
326			`else`
327			`if ( req_done_clear )`
328			req_done_reg <= #`FF_DELAY 1'b0 ;
329			`else`
330			`if ( done_in \|\| comp_cycle_count[16] )`
331			req_done_reg <= #`FF_DELAY 1'b1 ;
332			`end`
333
334	88	mihad	`synchronizer_flop #(1, 0) done_sync`
335	77	mihad	`(`
336			`.data_in (req_done_reg),`
337			`.clk_out (comp_clk_in),`
338			`.sync_data_out (sync_comp_done),`
339			`.async_reset (reset_in)`
340			`) ;`
341
342			`always@(posedge comp_clk_in or posedge reset_in)`
343			`begin`
344			`if ( reset_in )`
345			comp_done_reg_main <= #`FF_DELAY 1'b0 ;
346			`else`
347			comp_done_reg_main <= #`FF_DELAY sync_comp_done ;
348			`end`
349
350			`always@(posedge comp_clk_in or posedge reset_in)`
351			`begin`
352			`if ( reset_in )`
353			comp_done_reg_clr <= #`FF_DELAY 1'b0 ;
354			`else`
355			comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;
356			`end`
357
358			`/*=================================================================================================================================`
359			`Passing of retry expired signal between clock domains`
360			`Retry expiration originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain`
361			`=================================================================================================================================*/`
362			`// main retry expired Flip - Flop - triggered by completing side's clock`
363			`wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ;`
364
365			`// retry expired is a special case of transaction removal - retry expired propagates from completing`
366			`// clock domain to requesting clock domain to remove all pending requests and than propagates back`
367			`// to completing side to qualify valid new requests`
368
369			`always@(posedge comp_clk_in or posedge reset_in)`
370			`begin`
371			`if ( reset_in )`
372			comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
373			`else`
374			`if ( comp_rty_exp_clear )`
375			comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
376			`else`
377			`if ( retry_expired_in && comp_req_pending)`
378			comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
379			`end`
380
381			`// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability`
382	88	mihad	`synchronizer_flop #(1, 0) rty_exp_sync`
383	77	mihad	`(`
384			`.data_in (comp_rty_exp_reg),`
385			`.clk_out (req_clk_in),`
386			`.sync_data_out (sync_req_rty_exp),`
387			`.async_reset (reset_in)`
388			`) ;`
389
390			`// request retry expired flip flop - gets a value from intermediate stage sync flip flop`
391			`always@(posedge req_clk_in or posedge reset_in)`
392			`begin`
393			`if ( reset_in )`
394			req_rty_exp_reg <= #`FF_DELAY 1'b0 ;
395			`else`
396			req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ;
397			`end`
398
399			`always@(posedge req_clk_in or posedge reset_in)`
400			`begin`
401			`if ( reset_in )`
402			req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
403			`else`
404			req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
405			`end`
406
407	88	mihad	`synchronizer_flop #(1, 0) rty_exp_back_prop_sync`
408	77	mihad	`(`
409			`.data_in (req_rty_exp_reg && req_rty_exp_clr),`
410			`.clk_out (comp_clk_in),`
411			`.sync_data_out (sync_comp_rty_exp_clr),`
412			`.async_reset (reset_in)`
413			`) ;`
414
415			`always@(posedge comp_clk_in or posedge reset_in)`
416			`begin`
417			`if ( reset_in )`
418			comp_rty_exp_clr <= #`FF_DELAY 1'b0 ;
419			`else`
420			comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ;
421			`end`
422
423			`// completion status flip flop - if 0 when completion is signalled it's finished OK otherwise it means error`
424			`reg status_out ;`
425			`always@(posedge comp_clk_in or posedge reset_in)`
426			`begin`
427			`if (reset_in)`
428			status_out <= #`FF_DELAY 1'b0 ;
429			`else`
430			`if (comp_in && comp_req_pending)`
431			status_out <= #`FF_DELAY status_in ;
432			`end`
433
434			`// clocks counter - it counts how many clock cycles completion is present without beeing repeated`
435			`// if it counts to 2^^16 cycles the completion must be ditched`
436
437			`// wire for clearing this counter`
438			`wire clear_count = in_progress_in \|\| ~req_comp_pending_out \|\| comp_cycle_count[16] ;`
439			`always@(posedge req_clk_in or posedge reset_in)`
440			`begin`
441			`if (reset_in)`
442			comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
443			`else`
444			`if (clear_count)`
445			comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
446			`else`
447			comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ;
448			`end`
449
450			`// completion flush output - used for flushing fifos when counter expires`
451			`// if counter doesn't expire, fifo flush is up to WISHBONE slave or PCI target state machines`
452			`reg comp_flush_out ;`
453			`always@(posedge req_clk_in or posedge reset_in)`
454			`begin`
455			`if (reset_in)`
456			comp_flush_out <= #`FF_DELAY 1'b0 ;
457			`else`
458			comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ;
459			`end`
460
461			`endmodule //delayed_sync`