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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module
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axi4_checker
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#(
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A = 32, // address bus width
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N = 8, // data bus width in bytes
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I = 1, // ID width
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MAXRBURSTS = 16,
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MAXWBURSTS = 16,
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MAXWAITS = 16,
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RecommendOn = 1'b1,
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RecMaxWaitOn = 1'b1,
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qaztronic |
EXMON_WIDTH = 4
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qaztronic |
)
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(
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axi4_if axi4_in
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);
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//---------------------------------------------------
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//
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localparam AWUSER_MAX = 0;
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localparam WUSER_MAX = 0;
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localparam BUSER_MAX = 0;
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localparam ARUSER_MAX = 0;
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localparam RUSER_MAX = 0;
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//---------------------------------------------------
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//
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// INDEX: - Global Signals
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// =====
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wire ACLK = axi4_in.aclk; // AXI Clock
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wire ARESETn = axi4_in.aresetn; // AXI Reset
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// INDEX: - Write Address Channel
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// =====
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wire [(I-1):0] AWID = axi4_in.awid;
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wire [(A-1):0] AWADDR = axi4_in.awaddr;
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wire [7:0] AWLEN = axi4_in.awlen;
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wire [2:0] AWSIZE = axi4_in.awsize;
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wire [1:0] AWBURST = axi4_in.awburst;
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wire [3:0] AWCACHE = axi4_in.awcache;
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wire [2:0] AWPROT = axi4_in.awprot;
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wire [3:0] AWQOS = axi4_in.awqos;
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wire [3:0] AWREGION = axi4_in.awregion;
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wire AWLOCK = axi4_in.awlock;
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wire [AWUSER_MAX:0] AWUSER = 0;
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wire AWVALID = axi4_in.awvalid;
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wire AWREADY = axi4_in.awready;
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// INDEX: - Write Data Channel
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// =====
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wire [(8*N)-1:0] WDATA = axi4_in.wdata;
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wire [N-1:0] WSTRB = axi4_in.wstrb;
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wire [WUSER_MAX:0] WUSER = 0;
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wire WLAST = axi4_in.wlast;
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wire WVALID = axi4_in.wvalid;
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wire WREADY = axi4_in.wready;
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// INDEX: - Write Response Channel
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// =====
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wire [(I-1):0] BID = axi4_in.bid;
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wire [1:0] BRESP = axi4_in.bresp;
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wire [BUSER_MAX:0] BUSER = 0;
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wire BVALID = axi4_in.bvalid;
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wire BREADY = axi4_in.bready;
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// INDEX: - Read Address Channel
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// =====
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wire [(I-1):0] ARID = axi4_in.arid;
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wire [(A-1):0] ARADDR = axi4_in.araddr;
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wire [7:0] ARLEN = axi4_in.arlen;
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wire [2:0] ARSIZE = axi4_in.arsize;
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wire [1:0] ARBURST = axi4_in.arburst;
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wire [3:0] ARCACHE = axi4_in.arcache;
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wire [3:0] ARQOS = axi4_in.arqos;
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wire [3:0] ARREGION = axi4_in.arregion;
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wire [2:0] ARPROT = axi4_in.arprot;
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wire ARLOCK = axi4_in.arlock;
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wire [ARUSER_MAX:0] ARUSER = 0;
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wire ARVALID = axi4_in.arvalid;
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wire ARREADY = axi4_in.arready;
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// INDEX: - Read Data Channel
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// =====
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wire [(I-1):0] RID = axi4_in.rid;
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wire [(8*N)-1:0] RDATA = axi4_in.rdata;
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wire [1:0] RRESP = axi4_in.rresp;
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wire [RUSER_MAX:0] RUSER = 0;
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wire RLAST = axi4_in.rlast;
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wire RVALID = axi4_in.rvalid;
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wire RREADY = axi4_in.rready;
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// INDEX: - Low Power Interface
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// =====
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wire CACTIVE = 1;
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wire CSYSREQ = 0;
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wire CSYSACK = 0;
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//---------------------------------------------------
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//
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Axi4PC_ace
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#(
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// Set DATA_WIDTH to the data-bus width required
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.DATA_WIDTH(8*N), // = 64; // data bus width, default = 64-bit
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// Select the number of channel ID bits required
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.WID_WIDTH(I), // = 4; // (A|W|R|B)ID width
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.RID_WIDTH(I), // = 4; // (A|W|R|B)ID width
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// Select the size of the USER buses, default = 32-bit
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.AWUSER_WIDTH(0), // = 32; // width of the user AW sideband field
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.WUSER_WIDTH(0), // = 32; // width of the user W sideband field
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.BUSER_WIDTH(0), // = 32; // width of the user B sideband field
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.ARUSER_WIDTH(0), // = 32; // width of the user AR sideband field
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.RUSER_WIDTH(0), // = 32; // width of the user R sideband field
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// Size of CAMs for storing outstanding read bursts, this should match or
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// exceed the number of outstanding read addresses accepted into the slave
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// interface
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.MAXRBURSTS(MAXRBURSTS), // = 16;
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// Size of CAMs for storing outstanding write bursts, this should match or
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// exceed the number of outstanding write bursts into the slave interface
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.MAXWBURSTS(MAXWBURSTS), // = 16;
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// Maximum number of cycles between VALID -> READY high before a warning is
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// generated
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.MAXWAITS(MAXWAITS), // = 16;
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// Recommended Rules Enable
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// enable/disable reporting of all AXI4_REC*_* rules
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.RecommendOn(RecommendOn), // = 1'b1;
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// enable/disable reporting of just AXI4_REC*_MAX_WAIT rules
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.RecMaxWaitOn(RecMaxWaitOn), // = 1'b1;
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// Set the protocol - used to disable some AXI4 checks for ACE
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qaztronic |
// .PROTOCOL(PROTOCOL), // = `AXI4PC_AMBA_AXI4;
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qaztronic |
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// Set ADDR_WIDTH to the address-bus width required
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.ADDR_WIDTH(A), // = 32; // address bus width, default = 32-bit
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// Set EXMON_WIDTH to the exclusive access monitor width required
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.EXMON_WIDTH(EXMON_WIDTH) // = 4; // exclusive access width, default = 4-bit
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)
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Axi4PC_ace_i(.*);
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//---------------------------------------------------
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//
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endmodule
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