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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_vtb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Mos6502
T6502
def_vtb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      tb.vtb
    
  

 
 
 
 

 
 
 
 
 


    TIMEOUT10000

 
 
       
 
              
              Params
              
              
                                   ipxact:library="Mos6502"
                                   ipxact:name="T6502"
                                   ipxact:version="def_dut.params"/>
              
 
              
 
 
 
 
 
              
              verilator
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilator"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 

 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.int_m
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.vtb
        verilogSourcefragment
      
 
   
 
 
 
 
 
   
      fs-syn
 
      
        
        ../verilog/common/tb.vtb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/common/tb.vtb
        verilogSourcemodule
      
 
 
   
 
 
 

 
 
 
 
 
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def_vtb`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47
48	135	jt_eaton
49			`gen_verilog`
50			`104.0`
51			`none`
52			`:common:`
53			`tools/verilog/gen_verilog`
54
55
56			`destination`
57			`tb.vtb`
58
59
60
61	131	jt_eaton
62
63
64
65	135	jt_eaton
66	131	jt_eaton
67
68
69
70
71	135	jt_eaton
72
73			`TIMEOUT10000`
74
75	131	jt_eaton
76
77	135	jt_eaton
78	131	jt_eaton
79	135	jt_eaton
80			`Params`
81
82
83			`ipxact:library="Mos6502"`
84			`ipxact:name="T6502"`
85			`ipxact:version="def_dut.params"/>`
86
87	131	jt_eaton
88	135	jt_eaton
89	131	jt_eaton
90
91
92
93
94	135	jt_eaton
95			`verilator`
96
97
98			`ipxact:library="Testbench"`
99			`ipxact:name="toolflow"`
100			`ipxact:version="verilator"/>`
101
102
103	131	jt_eaton
104
105
106	135	jt_eaton
107			`common:common:`
108			`Verilog`
109
110
111			`fs-common`
112
113
114	131	jt_eaton
115
116
117
118	135	jt_eaton
119			`syn:Synthesis:`
120			`Verilog`
121
122
123			`fs-syn`
124
125
126	131	jt_eaton
127
128	135	jt_eaton
129			`lint:Lint:`
130			`Verilog`
131
132
133			`fs-lint`
134
135
136	131	jt_eaton
137
138	135	jt_eaton
139	131	jt_eaton
140
141
142
143
144	135	jt_eaton
145	131	jt_eaton
146
147
148	135	jt_eaton
149	131	jt_eaton
150
151
152	135	jt_eaton
153			`fs-common`
154	131	jt_eaton
155	135	jt_eaton
156
157			`../verilog/sram.load`
158			`verilogSourcefragment`
159
160	131	jt_eaton
161
162	135	jt_eaton
163
164			`../verilog/tb.int_m`
165			`verilogSourcefragment`
166
167	131	jt_eaton
168
169	135	jt_eaton
170
171			`../verilog/top.vtb`
172			`verilogSourcefragment`
173
174	131	jt_eaton
175	135	jt_eaton
176	131	jt_eaton
177
178
179
180
181	135	jt_eaton
182			`fs-syn`
183	131	jt_eaton
184	135	jt_eaton
185
186			`../verilog/common/tb.vtb`
187			`verilogSourcemodule`
188
189	131	jt_eaton
190
191	135	jt_eaton
192	131	jt_eaton
193
194	135	jt_eaton
195			`fs-lint`
196	131	jt_eaton
197	135	jt_eaton
198
199			`../verilog/common/tb.vtb`
200			`verilogSourcemodule`
201
202	131	jt_eaton
203
204	135	jt_eaton
205	131	jt_eaton
206
207
208	135	jt_eaton
209	131	jt_eaton
210
211
212
213
214
215
216
217	135	jt_eaton
218	131	jt_eaton
219
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_vtb.xml] - Blame information for rev 135