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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_rcvr.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
serial
rcvr
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      serial_rcvr
    
  

 
 
 
 
 
 

 
 
 
 
 
 

 
 
                
                        
                                verilog
                                verilog
                                cde_serial_rcvr
                                
                                        
                                                WIDTH
                                                8
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
  
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

WIDTH8
SIZE4
BREAK0
 

 

 
clk

wire
in

 
reset

wire
in

 
edge_enable

wire
in

 
parity_enable

wire
in

 
 
parity_type

wire
in

 
ser_in

wire
in

 
parity_force

wire
in

 
 
 
shift_buffer

reg
out
WIDTH-10

 
stop_cnt

reg
out

 
last_cnt

reg
out

 
parity_calc

reg
out

 
parity_samp

reg
out

 
 
 
frame_err

reg
out

 
 
break_detect

reg
out

 

 

 
 
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/serial_rcvr
        verilogSourcefragment
      
 
    
 
 
 
 
   
      fs-sim
 
     
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/serial_rcvr
        verilogSourcemodule
      
 
 
      
dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
     
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
 
      
        
        ../verilog/common/serial_rcvr
        verilogSourcemodule
      
 
 
 
      
dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 

 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_rcvr.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`serial`
15			`rcvr`
16	131	jt_eaton
17	135	jt_eaton
18	131	jt_eaton
19
20
21
22	135	jt_eaton
23			`gen_verilog`
24			`104.0`
25			`none`
26			`:common:`
27			`tools/verilog/gen_verilog`
28
29
30			`destination`
31			`serial_rcvr`
32
33
34
35	131	jt_eaton
36
37	134	jt_eaton
38
39
40
41	135	jt_eaton
42	131	jt_eaton
43
44
45
46
47
48	135	jt_eaton
49	131	jt_eaton
50	134	jt_eaton
51	135	jt_eaton
52
53			`verilog`
54			`verilog`
55			`cde_serial_rcvr`
56
57
58			`WIDTH`
59			`8`
60
61
62
63			`fs-sim`
64
65
66
67	134	jt_eaton
68
69
70	135	jt_eaton
71	134	jt_eaton
72	135	jt_eaton
73			`rtl`
74			`verilog:Kactus2:`
75			`verilog`
76
77
78	134	jt_eaton
79	135	jt_eaton
80			`verilog`
81
82
83			`ipxact:library="Testbench"`
84			`ipxact:name="toolflow"`
85			`ipxact:version="verilog"/>`
86
87
88	131	jt_eaton
89
90
91	135	jt_eaton
92			`common:common:`
93			`Verilog`
94
95
96			`fs-common`
97
98
99	131	jt_eaton
100
101
102	135	jt_eaton
103			`sim:Simulation:`
104			`Verilog`
105
106
107			`fs-sim`
108
109
110	131	jt_eaton
111	135	jt_eaton
112			`syn:Synthesis:`
113			`Verilog`
114
115
116			`fs-syn`
117
118
119	131	jt_eaton
120
121
122	135	jt_eaton
123			`doc`
124
125
126			`ipxact:library="Testbench"`
127			`ipxact:name="toolflow"`
128			`ipxact:version="documentation"/>`
129
130			`:Documentation:`
131			`Verilog`
132
133	131	jt_eaton
134
135
136	135	jt_eaton
137	131	jt_eaton
138
139
140	135	jt_eaton
141			`WIDTH8`
142			`SIZE4`
143			`BREAK0`
144	131	jt_eaton
145	135	jt_eaton
146	131	jt_eaton
147	135	jt_eaton
148	131	jt_eaton
149	135	jt_eaton	`clk`
150
151			`wire`
152			`in`
153
154	131	jt_eaton
155	135	jt_eaton	`reset`
156
157			`wire`
158			`in`
159
160	131	jt_eaton
161	135	jt_eaton	`edge_enable`
162
163			`wire`
164			`in`
165
166	131	jt_eaton
167	135	jt_eaton	`parity_enable`
168
169			`wire`
170			`in`
171
172	131	jt_eaton
173
174	135	jt_eaton	`parity_type`
175
176			`wire`
177			`in`
178
179	131	jt_eaton
180	135	jt_eaton	`ser_in`
181
182			`wire`
183			`in`
184
185	131	jt_eaton
186	135	jt_eaton	`parity_force`
187
188			`wire`
189			`in`
190
191	131	jt_eaton
192
193	134	jt_eaton
194	135	jt_eaton	`shift_buffer`
195
196			`reg`
197			`out`
198			`WIDTH-10`
199
200	134	jt_eaton
201	135	jt_eaton	`stop_cnt`
202
203			`reg`
204			`out`
205
206	131	jt_eaton
207	135	jt_eaton	`last_cnt`
208
209			`reg`
210			`out`
211
212	131	jt_eaton
213	135	jt_eaton	`parity_calc`
214
215			`reg`
216			`out`
217
218	134	jt_eaton
219	135	jt_eaton	`parity_samp`
220
221			`reg`
222			`out`
223
224	131	jt_eaton
225
226
227	135	jt_eaton	`frame_err`
228
229			`reg`
230			`out`
231
232	131	jt_eaton
233
234	135	jt_eaton	`break_detect`
235
236			`reg`
237			`out`
238
239	131	jt_eaton
240	135	jt_eaton
241	131	jt_eaton
242	135	jt_eaton
243	134	jt_eaton
244
245
246
247
248	135	jt_eaton
249	134	jt_eaton
250
251
252	135	jt_eaton
253			`fs-common`
254	131	jt_eaton
255	135	jt_eaton
256
257			`../verilog/serial_rcvr`
258			`verilogSourcefragment`
259
260
261
262
263
264
265
266
267			`fs-sim`
268
269
270
271			`../verilog/copyright`
272			`verilogSourceinclude`
273
274	131	jt_eaton
275	135	jt_eaton
276
277			`../verilog/common/serial_rcvr`
278			`verilogSourcemodule`
279
280	134	jt_eaton
281
282	135	jt_eaton
283			`dest_dir`
284			`../views/sim/`
285			`verilogSourcelibraryDir`
286
287	131	jt_eaton
288	135	jt_eaton
289	131	jt_eaton
290
291	135	jt_eaton
292			`fs-syn`
293	131	jt_eaton
294	135	jt_eaton
295
296			`../verilog/copyright`
297			`verilogSourceinclude`
298
299	134	jt_eaton
300
301
302
303	135	jt_eaton
304
305			`../verilog/common/serial_rcvr`
306			`verilogSourcemodule`
307
308	134	jt_eaton
309
310
311	135	jt_eaton
312			`dest_dir`
313			`../views/syn/`
314			`verilogSourcelibraryDir`
315
316	131	jt_eaton
317
318
319	135	jt_eaton
320	131	jt_eaton
321
322	135	jt_eaton
323	131	jt_eaton
324	135	jt_eaton	`fs-lint`
325
326			`dest_dir../views/syn/`
327			`verilogSourcelibraryDir`
328
329	131	jt_eaton
330	135	jt_eaton
331	131	jt_eaton
332
333	135	jt_eaton
334	131	jt_eaton
335
336	135	jt_eaton