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jdoin |
Release 13.1 - xst O.40d (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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jdoin |
Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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jdoin |
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--> Parameter xsthdpdir set to xst
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jdoin |
Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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jdoin |
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--> Reading design: spi_master_atlys_top.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "spi_master_atlys_top.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "spi_master_atlys_top"
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Output Format : NGC
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Target Device : xc6slx45-2-csg324
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---- Source Options
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Top Module Name : spi_master_atlys_top
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Gray
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : No
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ROM Extraction : No
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Shift Register Extraction : NO
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Automatic Register Balancing : No
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---- Target Options
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LUT Combining : Area
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 16
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 2
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Power Reduction : NO
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Parsing *
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=========================================================================
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jdoin |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
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jdoin |
Parsing entity .
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Parsing architecture of entity .
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jdoin |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expression
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WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expression
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WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expression
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Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
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jdoin |
Parsing entity .
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Parsing architecture of entity .
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jdoin |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expression
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WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expression
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WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expression
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WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expression
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Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
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jdoin |
Parsing entity .
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Parsing architecture of entity .
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jdoin |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
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jdoin |
Parsing entity .
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jdoin |
Parsing architecture of entity .
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jdoin |
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=========================================================================
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* HDL Elaboration *
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=========================================================================
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jdoin |
Elaborating entity (architecture ) with generics from library .
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jdoin |
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Elaborating entity (architecture ) with generics from library .
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Elaborating entity (architecture ) with generics from library .
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Elaborating entity (architecture ) with generics from library .
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Elaborating entity (architecture ) with generics from library .
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jdoin |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 460. Case statement is complete. others clause is never selected
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INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 522. Case statement is complete. others clause is never selected
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INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 572. Case statement is complete. others clause is never selected
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jdoin |
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit .
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jdoin |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
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jdoin |
N = 8
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CPOL = '0'
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CPHA = '0'
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PREFETCH = 3
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jdoin |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 225: Output port of the instance is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 234: Output port of the instance is unconnected or connected to loadless signal.
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jdoin |
Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 4-bit register for signal .
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Found 3-bit register for signal .
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Found 3-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 6-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 7 |
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| Transitions | 20 |
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| Inputs | 2 |
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| Outputs | 3 |
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jdoin |
| Clock | pclk_i (rising_edge) |
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jdoin |
| Reset | spi_ssel_o (positive) |
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| Reset type | synchronous |
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| Reset State | st_reset |
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| Power Up State | st_reset |
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| Encoding | Gray |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 11 |
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| Transitions | 36 |
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| Inputs | 11 |
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| Outputs | 10 |
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jdoin |
| Clock | pclk_i (rising_edge) |
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jdoin |
| Reset | clear (positive) |
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| Reset type | synchronous |
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| Reset State | st_reset |
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| Power Up State | st_reset |
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| Encoding | Gray |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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INFO:Xst:1799 - State st_wait_spi_ack_2 is never reached in FSM .
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 8 |
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222 |
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| Transitions | 20 |
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| Inputs | 5 |
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| Outputs | 9 |
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jdoin |
| Clock | pclk_i (rising_edge) |
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jdoin |
| Reset | spi_ssel_o (positive) |
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227 |
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| Reset type | synchronous |
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228 |
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| Reset State | st_reset |
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229 |
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| Power Up State | st_reset |
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230 |
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| Encoding | Gray |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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jdoin |
Found 1-bit adder for signal > created at line 277.
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Found 1-bit adder for signal > created at line 291.
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Found 8-bit comparator equal for signal <_n0380> created at line 363
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Found 6-bit comparator equal for signal <_n0400> created at line 366
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jdoin |
Summary:
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inferred 2 Adder/Subtractor(s).
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inferred 71 D-type flip-flop(s).
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inferred 2 Comparator(s).
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inferred 5 Multiplexer(s).
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inferred 3 Finite State Machine(s).
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Unit synthesized.
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Synthesizing Unit .
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jdoin |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd".
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jdoin |
N = 8
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CPOL = '0'
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CPHA = '0'
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250 |
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PREFETCH = 3
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251 |
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SPI_2X_CLK_DIV = 1
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252 |
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Found 1-bit register for signal .
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253 |
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Found 1-bit register for signal .
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254 |
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Found 1-bit register for signal .
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255 |
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Found 1-bit register for signal .
|
256 |
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Found 1-bit register for signal .
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257 |
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Found 1-bit register for signal .
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258 |
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Found 1-bit register for signal .
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259 |
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Found 1-bit register for signal .
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260 |
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Found 1-bit register for signal .
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261 |
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Found 1-bit register for signal .
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262 |
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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264 |
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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266 |
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Found 4-bit register for signal .
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Found 8-bit register for signal .
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272 |
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Found 1-bit register for signal .
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273 |
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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277 |
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Found 1-bit register for signal .
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278 |
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Found 1-bit register for signal .
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279 |
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Found 1-bit register for signal .
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22 |
jdoin |
Found 1-bit adder for signal > created at line 330.
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Found 4-bit subtractor for signal > created at line 528.
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282 |
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Found 4-bit comparator greater for signal created at line 521
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Found 4-bit comparator greater for signal created at line 521
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Found 4-bit comparator greater for signal created at line 530
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285 |
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Found 4-bit comparator greater for signal created at line 530
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jdoin |
Summary:
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287 |
|
|
inferred 2 Adder/Subtractor(s).
|
288 |
|
|
inferred 52 D-type flip-flop(s).
|
289 |
|
|
inferred 4 Comparator(s).
|
290 |
|
|
inferred 13 Multiplexer(s).
|
291 |
|
|
Unit synthesized.
|
292 |
|
|
|
293 |
|
|
Synthesizing Unit .
|
294 |
24 |
jdoin |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd".
|
295 |
20 |
jdoin |
N = 8
|
296 |
|
|
CPOL = '0'
|
297 |
|
|
CPHA = '0'
|
298 |
|
|
PREFETCH = 3
|
299 |
22 |
jdoin |
Found 1-bit register for signal .
|
300 |
20 |
jdoin |
Found 4-bit register for signal .
|
301 |
|
|
Found 1-bit register for signal .
|
302 |
|
|
Found 1-bit register for signal .
|
303 |
|
|
Found 1-bit register for signal .
|
304 |
|
|
Found 1-bit register for signal .
|
305 |
|
|
Found 1-bit register for signal .
|
306 |
|
|
Found 1-bit register for signal .
|
307 |
|
|
Found 1-bit register for signal .
|
308 |
|
|
Found 1-bit register for signal .
|
309 |
|
|
Found 1-bit register for signal .
|
310 |
|
|
Found 8-bit register for signal .
|
311 |
|
|
Found 1-bit register for signal .
|
312 |
|
|
Found 8-bit register for signal .
|
313 |
|
|
Found 8-bit register for signal .
|
314 |
|
|
Found 1-bit register for signal .
|
315 |
|
|
Found 1-bit register for signal .
|
316 |
|
|
Found 1-bit register for signal .
|
317 |
|
|
Found 1-bit register for signal .
|
318 |
|
|
Found 1-bit register for signal .
|
319 |
22 |
jdoin |
Found 4-bit subtractor for signal > created at line 376.
|
320 |
|
|
Found 4-bit comparator greater for signal created at line 369
|
321 |
|
|
Found 4-bit comparator greater for signal created at line 369
|
322 |
|
|
Found 4-bit comparator greater for signal created at line 378
|
323 |
|
|
Found 4-bit comparator greater for signal created at line 378
|
324 |
20 |
jdoin |
Summary:
|
325 |
|
|
inferred 1 Adder/Subtractor(s).
|
326 |
22 |
jdoin |
inferred 44 D-type flip-flop(s).
|
327 |
20 |
jdoin |
inferred 4 Comparator(s).
|
328 |
|
|
inferred 22 Multiplexer(s).
|
329 |
|
|
Unit synthesized.
|
330 |
|
|
|
331 |
|
|
Synthesizing Unit .
|
332 |
24 |
jdoin |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
|
333 |
20 |
jdoin |
N = 8
|
334 |
24 |
jdoin |
CNT_VAL = 200
|
335 |
20 |
jdoin |
Found 8-bit register for signal .
|
336 |
|
|
Found 8-bit register for signal .
|
337 |
24 |
jdoin |
Found 1-bit register for signal .
|
338 |
20 |
jdoin |
Found 8-bit register for signal .
|
339 |
24 |
jdoin |
Found 8-bit register for signal .
|
340 |
|
|
Found 9-bit adder for signal created at line 167.
|
341 |
|
|
Found 8-bit comparator not equal for signal created at line 192
|
342 |
|
|
Found 8-bit comparator not equal for signal created at line 194
|
343 |
20 |
jdoin |
Summary:
|
344 |
|
|
inferred 1 Adder/Subtractor(s).
|
345 |
24 |
jdoin |
inferred 33 D-type flip-flop(s).
|
346 |
20 |
jdoin |
inferred 2 Comparator(s).
|
347 |
|
|
Unit synthesized.
|
348 |
|
|
|
349 |
|
|
Synthesizing Unit .
|
350 |
24 |
jdoin |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
|
351 |
20 |
jdoin |
N = 6
|
352 |
24 |
jdoin |
CNT_VAL = 200
|
353 |
20 |
jdoin |
Found 6-bit register for signal .
|
354 |
|
|
Found 6-bit register for signal .
|
355 |
24 |
jdoin |
Found 1-bit register for signal .
|
356 |
20 |
jdoin |
Found 6-bit register for signal .
|
357 |
24 |
jdoin |
Found 8-bit register for signal .
|
358 |
|
|
Found 9-bit adder for signal created at line 167.
|
359 |
|
|
Found 6-bit comparator not equal for signal created at line 192
|
360 |
|
|
Found 6-bit comparator not equal for signal created at line 194
|
361 |
20 |
jdoin |
Summary:
|
362 |
|
|
inferred 1 Adder/Subtractor(s).
|
363 |
24 |
jdoin |
inferred 27 D-type flip-flop(s).
|
364 |
20 |
jdoin |
inferred 2 Comparator(s).
|
365 |
|
|
Unit synthesized.
|
366 |
|
|
|
367 |
|
|
=========================================================================
|
368 |
|
|
HDL Synthesis Report
|
369 |
|
|
|
370 |
|
|
Macro Statistics
|
371 |
|
|
# Adders/Subtractors : 7
|
372 |
|
|
1-bit adder : 3
|
373 |
|
|
4-bit subtractor : 2
|
374 |
24 |
jdoin |
9-bit adder : 2
|
375 |
|
|
# Registers : 75
|
376 |
|
|
1-bit register : 51
|
377 |
20 |
jdoin |
4-bit register : 2
|
378 |
|
|
6-bit register : 4
|
379 |
24 |
jdoin |
8-bit register : 18
|
380 |
20 |
jdoin |
# Comparators : 14
|
381 |
|
|
4-bit comparator greater : 8
|
382 |
|
|
6-bit comparator equal : 1
|
383 |
|
|
6-bit comparator not equal : 2
|
384 |
|
|
8-bit comparator equal : 1
|
385 |
|
|
8-bit comparator not equal : 2
|
386 |
|
|
# Multiplexers : 40
|
387 |
|
|
1-bit 2-to-1 multiplexer : 13
|
388 |
|
|
4-bit 2-to-1 multiplexer : 12
|
389 |
|
|
8-bit 2-to-1 multiplexer : 15
|
390 |
|
|
# FSMs : 3
|
391 |
|
|
|
392 |
|
|
=========================================================================
|
393 |
|
|
|
394 |
|
|
=========================================================================
|
395 |
|
|
* Advanced HDL Synthesis *
|
396 |
|
|
=========================================================================
|
397 |
|
|
|
398 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
399 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
400 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
401 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
402 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
403 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
404 |
|
|
|
405 |
|
|
Synthesizing (advanced) Unit .
|
406 |
|
|
The following registers are absorbed into counter : 1 register on signal .
|
407 |
|
|
Unit synthesized (advanced).
|
408 |
|
|
|
409 |
|
|
Synthesizing (advanced) Unit .
|
410 |
|
|
The following registers are absorbed into counter : 1 register on signal .
|
411 |
|
|
Unit synthesized (advanced).
|
412 |
|
|
|
413 |
|
|
Synthesizing (advanced) Unit .
|
414 |
|
|
The following registers are absorbed into counter : 1 register on signal .
|
415 |
|
|
Unit synthesized (advanced).
|
416 |
|
|
|
417 |
|
|
Synthesizing (advanced) Unit .
|
418 |
|
|
The following registers are absorbed into counter : 1 register on signal .
|
419 |
|
|
The following registers are absorbed into counter : 1 register on signal .
|
420 |
|
|
Unit synthesized (advanced).
|
421 |
|
|
|
422 |
|
|
=========================================================================
|
423 |
|
|
Advanced HDL Synthesis Report
|
424 |
|
|
|
425 |
|
|
Macro Statistics
|
426 |
|
|
# Adders/Subtractors : 2
|
427 |
|
|
4-bit subtractor : 2
|
428 |
|
|
# Counters : 5
|
429 |
|
|
1-bit up counter : 3
|
430 |
24 |
jdoin |
8-bit up counter : 2
|
431 |
|
|
# Registers : 208
|
432 |
|
|
Flip-Flops : 208
|
433 |
20 |
jdoin |
# Comparators : 14
|
434 |
|
|
4-bit comparator greater : 8
|
435 |
|
|
6-bit comparator equal : 1
|
436 |
|
|
6-bit comparator not equal : 2
|
437 |
|
|
8-bit comparator equal : 1
|
438 |
|
|
8-bit comparator not equal : 2
|
439 |
22 |
jdoin |
# Multiplexers : 47
|
440 |
|
|
1-bit 2-to-1 multiplexer : 21
|
441 |
20 |
jdoin |
4-bit 2-to-1 multiplexer : 12
|
442 |
|
|
8-bit 2-to-1 multiplexer : 14
|
443 |
|
|
# FSMs : 3
|
444 |
|
|
|
445 |
|
|
=========================================================================
|
446 |
|
|
|
447 |
|
|
=========================================================================
|
448 |
|
|
* Low Level Synthesis *
|
449 |
|
|
=========================================================================
|
450 |
|
|
WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
451 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
452 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
453 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed :
|
454 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
455 |
|
|
Optimizing FSM on signal with Gray encoding.
|
456 |
|
|
--------------------------------------
|
457 |
|
|
State | Encoding
|
458 |
|
|
--------------------------------------
|
459 |
|
|
st_reset | 000
|
460 |
|
|
st_wait_spi_do_valid_1 | 001
|
461 |
|
|
st_wait_spi_n_do_valid_1 | 011
|
462 |
|
|
st_wait_spi_do_valid_2 | 010
|
463 |
|
|
st_wait_spi_n_do_valid_2 | 110
|
464 |
|
|
st_wait_spi_do_valid_3 | 111
|
465 |
|
|
st_wait_spi_n_do_valid_3 | 101
|
466 |
|
|
--------------------------------------
|
467 |
|
|
Optimizing FSM on signal with Gray encoding.
|
468 |
|
|
----------------------------------
|
469 |
|
|
State | Encoding
|
470 |
|
|
----------------------------------
|
471 |
|
|
st_reset | 0000
|
472 |
|
|
st_wait_spi_idle | 0001
|
473 |
|
|
st_wait_new_switch | 0011
|
474 |
|
|
st_send_spi_data_sw | 0110
|
475 |
|
|
st_wait_spi_ack_sw | 0111
|
476 |
|
|
st_send_spi_data_1 | 0010
|
477 |
|
|
st_wait_spi_ack_1 | 0100
|
478 |
|
|
st_wait_spi_di_req_2 | 0101
|
479 |
|
|
st_wait_spi_ack_2 | 1100
|
480 |
|
|
st_wait_spi_di_req_3 | 1101
|
481 |
|
|
st_wait_spi_ack_3 | 1111
|
482 |
|
|
----------------------------------
|
483 |
|
|
Optimizing FSM on signal with Gray encoding.
|
484 |
|
|
------------------------------------
|
485 |
|
|
State | Encoding
|
486 |
|
|
------------------------------------
|
487 |
|
|
st_reset | 000
|
488 |
|
|
st_wait_spi_start | 001
|
489 |
|
|
st_wait_spi_di_req_2 | 011
|
490 |
|
|
st_wait_spi_ack_2 | unreached
|
491 |
|
|
st_wait_spi_do_valid_1 | 010
|
492 |
|
|
st_wait_spi_di_req_3 | 110
|
493 |
|
|
st_wait_spi_ack_3 | 111
|
494 |
|
|
st_wait_spi_end | 101
|
495 |
|
|
------------------------------------
|
496 |
|
|
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_6 hinder the constant cleaning in the block spi_master_atlys_top.
|
497 |
|
|
You should achieve better results by setting this init to 1.
|
498 |
|
|
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.
|
499 |
|
|
You should achieve better results by setting this init to 1.
|
500 |
|
|
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.
|
501 |
|
|
You should achieve better results by setting this init to 1.
|
502 |
22 |
jdoin |
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed :
|
503 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
504 |
20 |
jdoin |
|
505 |
|
|
Optimizing unit ...
|
506 |
|
|
|
507 |
|
|
Optimizing unit ...
|
508 |
|
|
|
509 |
|
|
Optimizing unit ...
|
510 |
|
|
|
511 |
|
|
Optimizing unit ...
|
512 |
|
|
|
513 |
|
|
Optimizing unit ...
|
514 |
24 |
jdoin |
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
515 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
516 |
20 |
jdoin |
WARNING:Xst:1293 - FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
517 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
518 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
519 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
520 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
521 |
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
522 |
22 |
jdoin |
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed :
|
523 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
524 |
20 |
jdoin |
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
525 |
|
|
INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following 2 FFs/Latches, which will be removed :
|
526 |
|
|
|
527 |
|
|
Mapping all equations...
|
528 |
|
|
Building and optimizing final netlist ...
|
529 |
|
|
Found area constraint ratio of 100 (+ 5) on block spi_master_atlys_top, actual ratio is 1.
|
530 |
|
|
FlipFlop Inst_spi_slave_port/state_reg_0 has been replicated 1 time(s)
|
531 |
|
|
FlipFlop Inst_spi_slave_port/state_reg_1 has been replicated 1 time(s)
|
532 |
|
|
FlipFlop Inst_spi_slave_port/state_reg_2 has been replicated 2 time(s)
|
533 |
|
|
|
534 |
|
|
Final Macro Processing ...
|
535 |
|
|
|
536 |
|
|
=========================================================================
|
537 |
|
|
Final Register Report
|
538 |
|
|
|
539 |
|
|
Macro Statistics
|
540 |
24 |
jdoin |
# Registers : 218
|
541 |
|
|
Flip-Flops : 218
|
542 |
20 |
jdoin |
|
543 |
|
|
=========================================================================
|
544 |
|
|
|
545 |
|
|
=========================================================================
|
546 |
|
|
* Partition Report *
|
547 |
|
|
=========================================================================
|
548 |
|
|
|
549 |
|
|
Partition Implementation Status
|
550 |
|
|
-------------------------------
|
551 |
|
|
|
552 |
|
|
No Partitions were found in this design.
|
553 |
|
|
|
554 |
|
|
-------------------------------
|
555 |
|
|
|
556 |
|
|
=========================================================================
|
557 |
|
|
* Design Summary *
|
558 |
|
|
=========================================================================
|
559 |
|
|
|
560 |
|
|
Top Level Output File Name : spi_master_atlys_top.ngc
|
561 |
|
|
|
562 |
|
|
Primitive and Black Box Usage:
|
563 |
|
|
------------------------------
|
564 |
24 |
jdoin |
# BELS : 202
|
565 |
20 |
jdoin |
# GND : 1
|
566 |
|
|
# INV : 4
|
567 |
24 |
jdoin |
# LUT1 : 14
|
568 |
|
|
# LUT2 : 4
|
569 |
|
|
# LUT3 : 28
|
570 |
20 |
jdoin |
# LUT4 : 17
|
571 |
24 |
jdoin |
# LUT5 : 54
|
572 |
|
|
# LUT6 : 45
|
573 |
|
|
# MUXCY : 14
|
574 |
20 |
jdoin |
# MUXF7 : 4
|
575 |
|
|
# VCC : 1
|
576 |
24 |
jdoin |
# XORCY : 16
|
577 |
|
|
# FlipFlops/Latches : 218
|
578 |
|
|
# FD : 84
|
579 |
20 |
jdoin |
# FD_1 : 1
|
580 |
|
|
# FDC : 8
|
581 |
24 |
jdoin |
# FDE : 110
|
582 |
22 |
jdoin |
# FDP_1 : 1
|
583 |
20 |
jdoin |
# FDR : 10
|
584 |
|
|
# FDRE : 4
|
585 |
24 |
jdoin |
# Clock Buffers : 3
|
586 |
20 |
jdoin |
# BUFG : 1
|
587 |
24 |
jdoin |
# BUFGP : 2
|
588 |
20 |
jdoin |
# IO Buffers : 62
|
589 |
|
|
# IBUF : 14
|
590 |
|
|
# OBUF : 48
|
591 |
|
|
|
592 |
|
|
Device utilization summary:
|
593 |
|
|
---------------------------
|
594 |
|
|
|
595 |
|
|
Selected Device : 6slx45csg324-2
|
596 |
|
|
|
597 |
|
|
|
598 |
|
|
Slice Logic Utilization:
|
599 |
24 |
jdoin |
Number of Slice Registers: 218 out of 54576 0%
|
600 |
|
|
Number of Slice LUTs: 166 out of 27288 0%
|
601 |
|
|
Number used as Logic: 166 out of 27288 0%
|
602 |
20 |
jdoin |
|
603 |
|
|
Slice Logic Distribution:
|
604 |
24 |
jdoin |
Number of LUT Flip Flop pairs used: 272
|
605 |
|
|
Number with an unused Flip Flop: 54 out of 272 19%
|
606 |
|
|
Number with an unused LUT: 106 out of 272 38%
|
607 |
|
|
Number of fully used LUT-FF pairs: 112 out of 272 41%
|
608 |
|
|
Number of unique control sets: 24
|
609 |
20 |
jdoin |
|
610 |
|
|
IO Utilization:
|
611 |
24 |
jdoin |
Number of IOs: 64
|
612 |
|
|
Number of bonded IOBs: 64 out of 218 29%
|
613 |
20 |
jdoin |
|
614 |
|
|
Specific Feature Utilization:
|
615 |
24 |
jdoin |
Number of BUFG/BUFGCTRLs: 3 out of 16 18%
|
616 |
20 |
jdoin |
|
617 |
|
|
---------------------------
|
618 |
|
|
Partition Resource Summary:
|
619 |
|
|
---------------------------
|
620 |
|
|
|
621 |
|
|
No Partitions were found in this design.
|
622 |
|
|
|
623 |
|
|
---------------------------
|
624 |
|
|
|
625 |
|
|
|
626 |
|
|
=========================================================================
|
627 |
|
|
Timing Report
|
628 |
|
|
|
629 |
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
630 |
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
631 |
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
632 |
|
|
|
633 |
|
|
Clock Information:
|
634 |
|
|
------------------
|
635 |
|
|
-----------------------------------+------------------------+-------+
|
636 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
637 |
|
|
-----------------------------------+------------------------+-------+
|
638 |
24 |
jdoin |
pclk_i | BUFGP | 161 |
|
639 |
|
|
sclk_i | BUFGP | 28 |
|
640 |
22 |
jdoin |
Inst_spi_master_port/spi_clk_reg | BUFG | 29 |
|
641 |
20 |
jdoin |
-----------------------------------+------------------------+-------+
|
642 |
|
|
|
643 |
|
|
Asynchronous Control Signals Information:
|
644 |
|
|
----------------------------------------
|
645 |
|
|
No asynchronous control signals found in this design
|
646 |
|
|
|
647 |
|
|
Timing Summary:
|
648 |
|
|
---------------
|
649 |
|
|
Speed Grade: -2
|
650 |
|
|
|
651 |
24 |
jdoin |
Minimum period: 5.283ns (Maximum Frequency: 189.286MHz)
|
652 |
20 |
jdoin |
Minimum input arrival time before clock: 2.083ns
|
653 |
22 |
jdoin |
Maximum output required time after clock: 7.216ns
|
654 |
20 |
jdoin |
Maximum combinational path delay: No path found
|
655 |
|
|
|
656 |
|
|
Timing Details:
|
657 |
|
|
---------------
|
658 |
|
|
All values displayed in nanoseconds (ns)
|
659 |
|
|
|
660 |
|
|
=========================================================================
|
661 |
24 |
jdoin |
Timing constraint: Default period analysis for Clock 'pclk_i'
|
662 |
|
|
Clock period: 5.283ns (frequency: 189.286MHz)
|
663 |
|
|
Total number of paths / destination ports: 1509 / 201
|
664 |
20 |
jdoin |
-------------------------------------------------------------------------
|
665 |
24 |
jdoin |
Delay: 5.283ns (Levels of Logic = 4)
|
666 |
20 |
jdoin |
Source: sw_reg_5 (FF)
|
667 |
24 |
jdoin |
Destination: btn_reg_0 (FF)
|
668 |
|
|
Source Clock: pclk_i rising
|
669 |
|
|
Destination Clock: pclk_i rising
|
670 |
20 |
jdoin |
|
671 |
24 |
jdoin |
Data Path: sw_reg_5 to btn_reg_0
|
672 |
20 |
jdoin |
Gate Net
|
673 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
674 |
|
|
---------------------------------------- ------------
|
675 |
|
|
FDE:C->Q 3 0.525 1.196 sw_reg_5 (sw_reg_5)
|
676 |
|
|
LUT6:I1->O 2 0.254 0.834 _n038082 (_n038081)
|
677 |
24 |
jdoin |
LUT6:I4->O 3 0.250 0.766 _n038083 (_n0380)
|
678 |
|
|
LUT5:I4->O 6 0.254 0.876 _n0418_inv1_rstpot (_n0418_inv1_rstpot)
|
679 |
|
|
LUT3:I2->O 1 0.254 0.000 btn_reg_0_dpot (btn_reg_0_dpot)
|
680 |
|
|
FDE:D 0.074 btn_reg_0
|
681 |
20 |
jdoin |
----------------------------------------
|
682 |
24 |
jdoin |
Total 5.283ns (1.611ns logic, 3.672ns route)
|
683 |
|
|
(30.5% logic, 69.5% route)
|
684 |
20 |
jdoin |
|
685 |
|
|
=========================================================================
|
686 |
24 |
jdoin |
Timing constraint: Default period analysis for Clock 'sclk_i'
|
687 |
|
|
Clock period: 3.764ns (frequency: 265.675MHz)
|
688 |
|
|
Total number of paths / destination ports: 173 / 52
|
689 |
|
|
-------------------------------------------------------------------------
|
690 |
|
|
Delay: 3.764ns (Levels of Logic = 1)
|
691 |
|
|
Source: Inst_spi_master_port/state_reg_3 (FF)
|
692 |
|
|
Destination: Inst_spi_master_port/sh_reg_7 (FF)
|
693 |
|
|
Source Clock: sclk_i rising
|
694 |
|
|
Destination Clock: sclk_i rising
|
695 |
|
|
|
696 |
|
|
Data Path: Inst_spi_master_port/state_reg_3 to Inst_spi_master_port/sh_reg_7
|
697 |
|
|
Gate Net
|
698 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
699 |
|
|
---------------------------------------- ------------
|
700 |
|
|
FDRE:C->Q 21 0.525 1.740 Inst_spi_master_port/state_reg_3 (Inst_spi_master_port/state_reg_3)
|
701 |
|
|
LUT6:I1->O 8 0.254 0.943 Inst_spi_master_port/_n0278_inv1 (Inst_spi_master_port/_n0278_inv)
|
702 |
|
|
FDE:CE 0.302 Inst_spi_master_port/sh_reg_0
|
703 |
|
|
----------------------------------------
|
704 |
|
|
Total 3.764ns (1.081ns logic, 2.683ns route)
|
705 |
|
|
(28.7% logic, 71.3% route)
|
706 |
|
|
|
707 |
|
|
=========================================================================
|
708 |
20 |
jdoin |
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
|
709 |
|
|
Clock period: 4.344ns (frequency: 230.203MHz)
|
710 |
|
|
Total number of paths / destination ports: 214 / 36
|
711 |
|
|
-------------------------------------------------------------------------
|
712 |
|
|
Delay: 2.172ns (Levels of Logic = 2)
|
713 |
|
|
Source: Inst_spi_slave_port/state_reg_1_1 (FF)
|
714 |
|
|
Destination: Inst_spi_slave_port/tx_bit_reg (FF)
|
715 |
|
|
Source Clock: Inst_spi_master_port/spi_clk_reg rising
|
716 |
|
|
Destination Clock: Inst_spi_master_port/spi_clk_reg falling
|
717 |
|
|
|
718 |
|
|
Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg
|
719 |
|
|
Gate Net
|
720 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
721 |
|
|
---------------------------------------- ------------
|
722 |
|
|
FDC:C->Q 2 0.525 1.156 Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
|
723 |
24 |
jdoin |
LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N14)
|
724 |
20 |
jdoin |
MUXF7:I0->O 1 0.163 0.000 Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
|
725 |
|
|
FD_1:D 0.074 Inst_spi_slave_port/tx_bit_reg
|
726 |
|
|
----------------------------------------
|
727 |
|
|
Total 2.172ns (1.016ns logic, 1.156ns route)
|
728 |
|
|
(46.8% logic, 53.2% route)
|
729 |
|
|
|
730 |
|
|
=========================================================================
|
731 |
24 |
jdoin |
Timing constraint: Default OFFSET IN BEFORE for Clock 'pclk_i'
|
732 |
20 |
jdoin |
Total number of paths / destination ports: 14 / 14
|
733 |
|
|
-------------------------------------------------------------------------
|
734 |
|
|
Offset: 2.083ns (Levels of Logic = 1)
|
735 |
|
|
Source: sw_i<7> (PAD)
|
736 |
|
|
Destination: Inst_sw_debouncer/reg_A_7 (FF)
|
737 |
24 |
jdoin |
Destination Clock: pclk_i rising
|
738 |
20 |
jdoin |
|
739 |
|
|
Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
|
740 |
|
|
Gate Net
|
741 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
742 |
|
|
---------------------------------------- ------------
|
743 |
|
|
IBUF:I->O 1 1.328 0.681 sw_i_7_IBUF (sw_i_7_IBUF)
|
744 |
|
|
FD:D 0.074 Inst_sw_debouncer/reg_A_7
|
745 |
|
|
----------------------------------------
|
746 |
|
|
Total 2.083ns (1.402ns logic, 0.681ns route)
|
747 |
|
|
(67.3% logic, 32.7% route)
|
748 |
|
|
|
749 |
|
|
=========================================================================
|
750 |
24 |
jdoin |
Timing constraint: Default OFFSET OUT AFTER for Clock 'pclk_i'
|
751 |
|
|
Total number of paths / destination ports: 17 / 16
|
752 |
20 |
jdoin |
-------------------------------------------------------------------------
|
753 |
24 |
jdoin |
Offset: 5.464ns (Levels of Logic = 2)
|
754 |
|
|
Source: Inst_spi_master_port/wren (FF)
|
755 |
22 |
jdoin |
Destination: spi_mosi_o (PAD)
|
756 |
24 |
jdoin |
Source Clock: pclk_i rising
|
757 |
20 |
jdoin |
|
758 |
24 |
jdoin |
Data Path: Inst_spi_master_port/wren to spi_mosi_o
|
759 |
20 |
jdoin |
Gate Net
|
760 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
761 |
|
|
---------------------------------------- ------------
|
762 |
24 |
jdoin |
FD:C->Q 8 0.525 1.052 Inst_spi_master_port/wren (Inst_spi_master_port/wren)
|
763 |
|
|
LUT6:I4->O 2 0.250 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
|
764 |
22 |
jdoin |
OBUF:I->O 2.912 spi_mosi_o_OBUF (spi_mosi_o)
|
765 |
20 |
jdoin |
----------------------------------------
|
766 |
24 |
jdoin |
Total 5.464ns (3.687ns logic, 1.777ns route)
|
767 |
|
|
(67.5% logic, 32.5% route)
|
768 |
20 |
jdoin |
|
769 |
|
|
=========================================================================
|
770 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
|
771 |
22 |
jdoin |
Total number of paths / destination ports: 19 / 18
|
772 |
20 |
jdoin |
-------------------------------------------------------------------------
|
773 |
22 |
jdoin |
Offset: 5.307ns (Levels of Logic = 2)
|
774 |
|
|
Source: Inst_spi_slave_port/preload_miso (FF)
|
775 |
20 |
jdoin |
Destination: spi_miso_o (PAD)
|
776 |
22 |
jdoin |
Source Clock: Inst_spi_master_port/spi_clk_reg falling
|
777 |
20 |
jdoin |
|
778 |
22 |
jdoin |
Data Path: Inst_spi_slave_port/preload_miso to spi_miso_o
|
779 |
20 |
jdoin |
Gate Net
|
780 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
781 |
|
|
---------------------------------------- ------------
|
782 |
22 |
jdoin |
FDP_1:C->Q 2 0.525 0.954 Inst_spi_slave_port/preload_miso (Inst_spi_slave_port/preload_miso)
|
783 |
|
|
LUT3:I0->O 1 0.235 0.681 Inst_spi_slave_port/Mmux_spi_miso_o11 (spi_miso_o_OBUF)
|
784 |
20 |
jdoin |
OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o)
|
785 |
|
|
----------------------------------------
|
786 |
22 |
jdoin |
Total 5.307ns (3.672ns logic, 1.635ns route)
|
787 |
|
|
(69.2% logic, 30.8% route)
|
788 |
20 |
jdoin |
|
789 |
|
|
=========================================================================
|
790 |
24 |
jdoin |
Timing constraint: Default OFFSET OUT AFTER for Clock 'sclk_i'
|
791 |
|
|
Total number of paths / destination ports: 20 / 16
|
792 |
|
|
-------------------------------------------------------------------------
|
793 |
|
|
Offset: 7.216ns (Levels of Logic = 3)
|
794 |
|
|
Source: Inst_spi_master_port/state_reg_2 (FF)
|
795 |
|
|
Destination: spi_mosi_o (PAD)
|
796 |
|
|
Source Clock: sclk_i rising
|
797 |
20 |
jdoin |
|
798 |
24 |
jdoin |
Data Path: Inst_spi_master_port/state_reg_2 to spi_mosi_o
|
799 |
|
|
Gate Net
|
800 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
801 |
|
|
---------------------------------------- ------------
|
802 |
|
|
FDRE:C->Q 20 0.525 1.394 Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2)
|
803 |
|
|
LUT2:I0->O 2 0.250 1.156 Inst_spi_master_port/spi_mosi_o_SW0 (N4)
|
804 |
|
|
LUT6:I1->O 2 0.254 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
|
805 |
|
|
OBUF:I->O 2.912 spi_mosi_o_OBUF (spi_mosi_o)
|
806 |
|
|
----------------------------------------
|
807 |
|
|
Total 7.216ns (3.941ns logic, 3.275ns route)
|
808 |
|
|
(54.6% logic, 45.4% route)
|
809 |
|
|
|
810 |
|
|
=========================================================================
|
811 |
|
|
|
812 |
20 |
jdoin |
Cross Clock Domains Report:
|
813 |
|
|
--------------------------
|
814 |
|
|
|
815 |
|
|
Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg
|
816 |
|
|
--------------------------------+---------+---------+---------+---------+
|
817 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
818 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
819 |
|
|
--------------------------------+---------+---------+---------+---------+
|
820 |
22 |
jdoin |
Inst_spi_master_port/spi_clk_reg| 3.682| | 2.224| |
|
821 |
24 |
jdoin |
pclk_i | 3.012| | 2.135| |
|
822 |
|
|
sclk_i | 4.633| | 3.198| |
|
823 |
20 |
jdoin |
--------------------------------+---------+---------+---------+---------+
|
824 |
|
|
|
825 |
24 |
jdoin |
Clock to Setup on destination clock pclk_i
|
826 |
20 |
jdoin |
--------------------------------+---------+---------+---------+---------+
|
827 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
828 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
829 |
|
|
--------------------------------+---------+---------+---------+---------+
|
830 |
24 |
jdoin |
Inst_spi_master_port/spi_clk_reg| 2.078| | | |
|
831 |
|
|
pclk_i | 5.283| | | |
|
832 |
|
|
sclk_i | 3.198| | | |
|
833 |
20 |
jdoin |
--------------------------------+---------+---------+---------+---------+
|
834 |
|
|
|
835 |
24 |
jdoin |
Clock to Setup on destination clock sclk_i
|
836 |
|
|
--------------------------------+---------+---------+---------+---------+
|
837 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
838 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
839 |
|
|
--------------------------------+---------+---------+---------+---------+
|
840 |
|
|
Inst_spi_master_port/spi_clk_reg| | 1.855| | |
|
841 |
|
|
pclk_i | 3.244| | | |
|
842 |
|
|
sclk_i | 3.764| | | |
|
843 |
|
|
--------------------------------+---------+---------+---------+---------+
|
844 |
|
|
|
845 |
20 |
jdoin |
=========================================================================
|
846 |
|
|
|
847 |
|
|
|
848 |
22 |
jdoin |
Total REAL time to Xst completion: 6.00 secs
|
849 |
24 |
jdoin |
Total CPU time to Xst completion: 6.39 secs
|
850 |
20 |
jdoin |
|
851 |
|
|
-->
|
852 |
|
|
|
853 |
24 |
jdoin |
Total memory usage is 179340 kilobytes
|
854 |
20 |
jdoin |
|
855 |
|
|
Number of errors : 0 ( 0 filtered)
|
856 |
24 |
jdoin |
Number of warnings : 28 ( 0 filtered)
|
857 |
22 |
jdoin |
Number of infos : 24 ( 0 filtered)
|
858 |
20 |
jdoin |
|