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[/] [ss_pcm/] [trunk/] [rtl/] [verilog/] [pcm_slv_top.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  PCM IO Slave Module                                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ss_pcm/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: pcm_slv_top.v,v 1.2 2002-09-17 15:32:50 rudi Exp $
//
//  $Date: 2002-09-17 15:32:50 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2002/09/17 15:17:25  rudi
//               Initial Checkin
//
//
//
//
//
//
//
//
 
`include "timescale.v"
 
/*
PCM Interface
===============================
PCM_CLK
PCM_SYNC
PCM_DIN
PCM_DOUT
*/
 
module pcm_slv_top(     clk, rst,
 
                        ssel,
 
                        // PCM
                        pcm_clk_i, pcm_sync_i, pcm_din_i, pcm_dout_o,
 
                        // Internal Interface
                        din_i, dout_o, re_i, we_i);
 
input           clk, rst;
input   [2:0]    ssel;   // Number of bits to delay (0-7)
input           pcm_clk_i, pcm_sync_i, pcm_din_i;
output          pcm_dout_o;
input   [7:0]    din_i;
output  [7:0]    dout_o;
input           re_i;
input   [1:0]    we_i;
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
reg             pclk_t, pclk_s, pclk_r;
wire            pclk_ris, pclk_fal;
reg             psync;
reg             pcm_sync_r1, pcm_sync_r2, pcm_sync_r3;
reg             tx_go;
wire            tx_data_le;
reg     [15:0]   tx_hold_reg;
reg     [7:0]    tx_hold_byte_h, tx_hold_byte_l;
reg     [3:0]    tx_cnt;
wire            tx_done;
reg     [15:0]   rx_hold_reg, rx_reg;
wire            rx_data_le;
reg             rxd_t, rxd;
reg             tx_go_r1, tx_go_r2;
reg     [7:0]    psa;
 
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk)
        pclk_t <= #1 pcm_clk_i;
 
always @(posedge clk)
        pclk_s <= #1 pclk_t;
 
always @(posedge clk)
        pclk_r <= #1 pclk_s;
 
assign pclk_ris = !pclk_r &  pclk_s;
assign pclk_fal =  pclk_r & !pclk_s;
 
///////////////////////////////////////////////////////////////////
//
// Retrieve Sync Signal
//
 
always @(posedge clk)   // Latch it at falling edge
        if(pclk_fal)    pcm_sync_r1 <= #1 pcm_sync_i;
 
always @(posedge clk)   // resync to rising edge
        if(pclk_ris)    psa <= #1 {psa[6:0], pcm_sync_r1};
 
always @(posedge clk)   //delay bit N
        pcm_sync_r2 <= #1 psa[ssel];
 
always @(posedge clk)   // edge detector
        pcm_sync_r3 <= #1 pcm_sync_r2;
 
always @(posedge clk)
        psync <= #1 !pcm_sync_r3 & pcm_sync_r2;
 
///////////////////////////////////////////////////////////////////
//
// Transmit Logic
//
 
assign tx_data_le = tx_go & pclk_ris;
 
always @(posedge clk)
        if(we_i[1])     tx_hold_byte_h <= #1 din_i;
 
always @(posedge clk)
        if(we_i[0])      tx_hold_byte_l <= #1 din_i;
 
always @(posedge clk)
        if(!rst)        tx_go <= #1 1'b0;
        else
        if(psync)       tx_go <= #1 1'b1;
        else
        if(tx_done)     tx_go <= #1 1'b0;
 
always @(posedge clk)
        if(!rst)        tx_hold_reg <= #1 16'h0;
        else
        if(psync)       tx_hold_reg <= #1 {tx_hold_byte_h, tx_hold_byte_l};
        else
        if(tx_data_le)  tx_hold_reg <= #1 {tx_hold_reg[14:0],1'b0};
 
assign  pcm_dout_o = tx_hold_reg[15];
 
always @(posedge clk)
        if(!rst)        tx_cnt <= #1 4'h0;
        else
        if(tx_data_le)  tx_cnt <= tx_cnt + 4'h1;
 
assign tx_done = (tx_cnt == 4'hf) & tx_data_le;
 
///////////////////////////////////////////////////////////////////
//
// Recieve Logic
//
 
always @(posedge clk)
        if(pclk_ris)    tx_go_r1 <= #1 tx_go;
 
always @(posedge clk)
        if(pclk_ris)    tx_go_r2 <= #1 tx_go_r1;
 
// Receive is in sync with transmit ...
always @(posedge clk)
        if(pclk_fal)    rxd_t <= #1 pcm_din_i;
 
always @(posedge clk)
        rxd <= #1 rxd_t;
 
assign rx_data_le = (tx_go_r1 | tx_go) & pclk_fal;
 
always @(posedge clk)
        if(!rst)        rx_hold_reg <= #1 16'h0;
        else
        if(rx_data_le)  rx_hold_reg <= #1 {rx_hold_reg[14:0], rxd};
 
always @(posedge clk)
        if(!rst)                                rx_reg <= #1 16'h0;
        else
        if(tx_go_r1 & !tx_go & pclk_ris)        rx_reg <= #1 rx_hold_reg;
 
assign dout_o = re_i ? rx_reg[15:8] : rx_reg[7:0];
 
endmodule
 

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Subversion Repositories ss_pcm

[/] [ss_pcm/] [trunk/] [rtl/] [verilog/] [pcm_slv_top.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// PCM IO Slave Module ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/ss_pcm/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	4	rudi	`// $Id: pcm_slv_top.v,v 1.2 2002-09-17 15:32:50 rudi Exp $`
42	2	rudi	`//`
43	4	rudi	`// $Date: 2002-09-17 15:32:50 $`
44			`// $Revision: 1.2 $`
45	2	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	4	rudi	`// Revision 1.1.1.1 2002/09/17 15:17:25 rudi`
52			`// Initial Checkin`
53	2	rudi	`//`
54			`//`
55			`//`
56			`//`
57			`//`
58			`//`
59			`//`
60	4	rudi	`//`
61	2	rudi
62			`include "timescale.v"
63
64			`/*`
65			`PCM Interface`
66			`===============================`
67			`PCM_CLK`
68			`PCM_SYNC`
69			`PCM_DIN`
70			`PCM_DOUT`
71			`*/`
72
73			`module pcm_slv_top( clk, rst,`
74
75			`ssel,`
76
77			`// PCM`
78			`pcm_clk_i, pcm_sync_i, pcm_din_i, pcm_dout_o,`
79
80			`// Internal Interface`
81			`din_i, dout_o, re_i, we_i);`
82
83			`input clk, rst;`
84			`input [2:0] ssel; // Number of bits to delay (0-7)`
85			`input pcm_clk_i, pcm_sync_i, pcm_din_i;`
86			`output pcm_dout_o;`
87			`input [7:0] din_i;`
88			`output [7:0] dout_o;`
89			`input re_i;`
90			`input [1:0] we_i;`
91
92			`///////////////////////////////////////////////////////////////////`
93			`//`
94			`// Local Wires and Registers`
95			`//`
96
97			`reg pclk_t, pclk_s, pclk_r;`
98			`wire pclk_ris, pclk_fal;`
99			`reg psync;`
100			`reg pcm_sync_r1, pcm_sync_r2, pcm_sync_r3;`
101			`reg tx_go;`
102			`wire tx_data_le;`
103			`reg [15:0] tx_hold_reg;`
104			`reg [7:0] tx_hold_byte_h, tx_hold_byte_l;`
105			`reg [3:0] tx_cnt;`
106			`wire tx_done;`
107			`reg [15:0] rx_hold_reg, rx_reg;`
108			`wire rx_data_le;`
109			`reg rxd_t, rxd;`
110			`reg tx_go_r1, tx_go_r2;`
111			`reg [7:0] psa;`
112
113			`///////////////////////////////////////////////////////////////////`
114			`//`
115			`// Misc Logic`
116			`//`
117
118			`always @(posedge clk)`
119			`pclk_t <= #1 pcm_clk_i;`
120
121			`always @(posedge clk)`
122			`pclk_s <= #1 pclk_t;`
123
124			`always @(posedge clk)`
125			`pclk_r <= #1 pclk_s;`
126
127			`assign pclk_ris = !pclk_r & pclk_s;`
128			`assign pclk_fal = pclk_r & !pclk_s;`
129
130			`///////////////////////////////////////////////////////////////////`
131			`//`
132			`// Retrieve Sync Signal`
133			`//`
134
135			`always @(posedge clk) // Latch it at falling edge`
136			`if(pclk_fal) pcm_sync_r1 <= #1 pcm_sync_i;`
137
138			`always @(posedge clk) // resync to rising edge`
139			`if(pclk_ris) psa <= #1 {psa[6:0], pcm_sync_r1};`
140
141			`always @(posedge clk) //delay bit N`
142			`pcm_sync_r2 <= #1 psa[ssel];`
143
144			`always @(posedge clk) // edge detector`
145			`pcm_sync_r3 <= #1 pcm_sync_r2;`
146
147			`always @(posedge clk)`
148			`psync <= #1 !pcm_sync_r3 & pcm_sync_r2;`
149
150			`///////////////////////////////////////////////////////////////////`
151			`//`
152			`// Transmit Logic`
153			`//`
154
155			`assign tx_data_le = tx_go & pclk_ris;`
156
157			`always @(posedge clk)`
158			`if(we_i[1]) tx_hold_byte_h <= #1 din_i;`
159
160			`always @(posedge clk)`
161			`if(we_i[0]) tx_hold_byte_l <= #1 din_i;`
162
163			`always @(posedge clk)`
164			`if(!rst) tx_go <= #1 1'b0;`
165			`else`
166			`if(psync) tx_go <= #1 1'b1;`
167			`else`
168			`if(tx_done) tx_go <= #1 1'b0;`
169
170			`always @(posedge clk)`
171			`if(!rst) tx_hold_reg <= #1 16'h0;`
172			`else`
173			`if(psync) tx_hold_reg <= #1 {tx_hold_byte_h, tx_hold_byte_l};`
174			`else`
175			`if(tx_data_le) tx_hold_reg <= #1 {tx_hold_reg[14:0],1'b0};`
176
177			`assign pcm_dout_o = tx_hold_reg[15];`
178
179			`always @(posedge clk)`
180			`if(!rst) tx_cnt <= #1 4'h0;`
181			`else`
182			`if(tx_data_le) tx_cnt <= tx_cnt + 4'h1;`
183
184			`assign tx_done = (tx_cnt == 4'hf) & tx_data_le;`
185
186			`///////////////////////////////////////////////////////////////////`
187			`//`
188			`// Recieve Logic`
189			`//`
190
191			`always @(posedge clk)`
192			`if(pclk_ris) tx_go_r1 <= #1 tx_go;`
193
194			`always @(posedge clk)`
195			`if(pclk_ris) tx_go_r2 <= #1 tx_go_r1;`
196
197			`// Receive is in sync with transmit ...`
198			`always @(posedge clk)`
199			`if(pclk_fal) rxd_t <= #1 pcm_din_i;`
200
201			`always @(posedge clk)`
202			`rxd <= #1 rxd_t;`
203
204			`assign rx_data_le = (tx_go_r1 \| tx_go) & pclk_fal;`
205
206			`always @(posedge clk)`
207			`if(!rst) rx_hold_reg <= #1 16'h0;`
208			`else`
209			`if(rx_data_le) rx_hold_reg <= #1 {rx_hold_reg[14:0], rxd};`
210
211			`always @(posedge clk)`
212			`if(!rst) rx_reg <= #1 16'h0;`
213			`else`
214			`if(tx_go_r1 & !tx_go & pclk_ris) rx_reg <= #1 rx_hold_reg;`
215
216			`assign dout_o = re_i ? rx_reg[15:8] : rx_reg[7:0];`
217
218			`endmodule`
219