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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [debug_if/] [debug_if_ip.v] - Blame information for rev 22

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// debug_if_from_mod_synchronization_module.v
2 
// debug_if_defines.v
3 
module debug_if_from_mod_synchronization_module
4 
(
5 
    src_rst_i       ,
6 
    src_clr_i       ,
7 
    src_clk_i       ,
8 
    src_clk_en_i    ,
9 
    src_mux_comb_i  ,
10 
    src_i           ,
11 
    src_o           ,
12 
    sff_rst_i       ,
13 
    sff_clr_i       ,
14 
    sff_clk_i       ,
15 
    sff_clk_en_i    ,
16 
    sff_o           ,
17 
    dst_rst_i       ,
18 
    dst_clr_i       ,
19 
    dst_clk_i       ,
20 
    dst_clk_en_i    ,
21 
    dst_o
22 
) ;
23 
parameter width         = 1             ;   // Width parameter of Input and Output signals
24 
parameter rst_val       = 0             ;   // Reset value parameter of Flip-Flop Output signals
25 
input                   src_rst_i       ;   // Source reset
26 
input                   src_clr_i       ;   // Source clear
27 
input                   src_clk_i       ;   // Source clock
28 
input                   src_clk_en_i    ;   // Source clock enable for source Flip-Flop
29 
input                   src_mux_comb_i  ;   // Source multiplexer select for combinatorial source input (i.e. from input PAD)
30 
input   [width - 1: 0]  src_i           ;   // Source input
31 
output  [width - 1: 0]  src_o           ;   // Source output - not synchronized
32 
input                   sff_rst_i       ;   // Synchronizer reset (i.e. same as destination reset)
33 
input                   sff_clr_i       ;   // Synchronizer clear
34 
input                   sff_clk_i       ;   // Synchronizer clock (i.e. same as destination clock)
35 
input                   sff_clk_en_i    ;   // Synchronizer clok enable for synchronizer Flip-Flop
36 
output  [width - 1: 0]  sff_o           ;   // Synchronizer output
37 
input                   dst_rst_i       ;   // Destination reset
38 
input                   dst_clr_i       ;   // Destination clear
39 
input                   dst_clk_i       ;   // Destination clock
40 
input                   dst_clk_en_i    ;   // Destination clock enable for destination Flip-Flop
41 
output  [width - 1: 0]  dst_o           ;   // Destination output
42 
reg     [width - 1: 0]  src_o           ;
43 
reg     [width - 1: 0]  sff_o           ;
44 
reg     [width - 1: 0]  dst_o           ;
45 
reg     [width - 1: 0]  src             ;
46 
reg     [width - 1: 0]  sff_i           ;
47 
always @(posedge src_clk_i undefined)
48 
begin
49 
    if (src_rst_i == undefined)
50 
        src <= rst_val ;
51 
    else if (src_clr_i)
52 
        src <= rst_val ;
53 
    else if (src_clk_en_i)
54 
        src <= src_i ;
55 
end
56 
always @(src_i or src or src_mux_comb_i)
57 
begin
58 
    if (src_mux_comb_i)
59 
        src_o = src_i ;
60 
    else
61 
        src_o = src ;
62 
end
63 
always @(src_o)
64 
    sff_i = src_o ;
65 
always @(posedge sff_clk_i or posedge sff_rst_i)
66 
begin
67 
    if (sff_rst_i)
68 
        sff_o <= rst_val ;
69 
    else if (sff_clr_i)
70 
        sff_o <= rst_val ;
71 
    else if (sff_clk_en_i)
72 
        sff_o <= sff_i ;
73 
end
74 
always @(posedge dst_clk_i or posedge dst_rst_i)
75 
begin
76 
    if (dst_rst_i)
77 
        dst_o <= rst_val ;
78 
    else if (dst_clr_i)
79 
        dst_o <= rst_val ;
80 
    else if (dst_clk_en_i)
81 
        dst_o <= sff_o ;
82 
end
83 
endmodule // debug_if_synchronization_module
84 
// debug_if_to_mod_synchronization_module.v
85 
// debug_if_defines.v
86 
module debug_if_to_mod_synchronization_module
87 
(
88 
    src_rst_i       ,
89 
    src_clr_i       ,
90 
    src_clk_i       ,
91 
    src_clk_en_i    ,
92 
    src_mux_comb_i  ,
93 
    src_i           ,
94 
    src_o           ,
95 
    sff_rst_i       ,
96 
    sff_clr_i       ,
97 
    sff_clk_i       ,
98 
    sff_clk_en_i    ,
99 
    sff_o           ,
100 
    dst_rst_i       ,
101 
    dst_clr_i       ,
102 
    dst_clk_i       ,
103 
    dst_clk_en_i    ,
104 
    dst_o
105 
) ;
106 
parameter width         = 1             ;   // Width parameter of Input and Output signals
107 
parameter rst_val       = 0             ;   // Reset value parameter of Flip-Flop Output signals
108 
input                   src_rst_i       ;   // Source reset
109 
input                   src_clr_i       ;   // Source clear
110 
input                   src_clk_i       ;   // Source clock
111 
input                   src_clk_en_i    ;   // Source clock enable for source Flip-Flop
112 
input                   src_mux_comb_i  ;   // Source multiplexer select for combinatorial source input (i.e. from input PAD)
113 
input   [width - 1: 0]  src_i           ;   // Source input
114 
output  [width - 1: 0]  src_o           ;   // Source output - not synchronized
115 
input                   sff_rst_i       ;   // Synchronizer reset (i.e. same as destination reset)
116 
input                   sff_clr_i       ;   // Synchronizer clear
117 
input                   sff_clk_i       ;   // Synchronizer clock (i.e. same as destination clock)
118 
input                   sff_clk_en_i    ;   // Synchronizer clok enable for synchronizer Flip-Flop
119 
output  [width - 1: 0]  sff_o           ;   // Synchronizer output
120 
input                   dst_rst_i       ;   // Destination reset
121 
input                   dst_clr_i       ;   // Destination clear
122 
input                   dst_clk_i       ;   // Destination clock
123 
input                   dst_clk_en_i    ;   // Destination clock enable for destination Flip-Flop
124 
output  [width - 1: 0]  dst_o           ;   // Destination output
125 
reg     [width - 1: 0]  src_o           ;
126 
reg     [width - 1: 0]  sff_o           ;
127 
reg     [width - 1: 0]  dst_o           ;
128 
reg     [width - 1: 0]  src             ;
129 
reg     [width - 1: 0]  sff_i           ;
130 
always @(posedge src_clk_i or posedge src_rst_i)
131 
begin
132 
    if (src_rst_i)
133 
        src <= rst_val ;
134 
    else if (src_clr_i)
135 
        src <= rst_val ;
136 
    else if (src_clk_en_i)
137 
        src <= src_i ;
138 
end
139 
always @(src_i or src or src_mux_comb_i)
140 
begin
141 
    if (src_mux_comb_i)
142 
        src_o = src_i ;
143 
    else
144 
        src_o = src ;
145 
end
146 
always @(src_o)
147 
    sff_i = src_o ;
148 
always @(posedge sff_clk_i undefined)
149 
begin
150 
    if (sff_rst_i == undefined)
151 
        sff_o <= rst_val ;
152 
    else if (sff_clr_i)
153 
        sff_o <= rst_val ;
154 
    else if (sff_clk_en_i)
155 
        sff_o <= sff_i ;
156 
end
157 
always @(posedge dst_clk_i undefined)
158 
begin
159 
    if (dst_rst_i == undefined)
160 
        dst_o <= rst_val ;
161 
    else if (dst_clr_i)
162 
        dst_o <= rst_val ;
163 
    else if (dst_clk_en_i)
164 
        dst_o <= sff_o ;
165 
end
166 
endmodule // debug_if_synchronization_module
167 
// debug_if_crc.v
168 
// debug_if_defines.v
169 
// synopsys translate_off
170 
// timescale.v
171 
`timescale 1ns/10ps
172 
// synopsys translate_on
173 
module debug_if_crc
174 
(
175 
    clk_i       , // TAP clock
176 
    rst_i       , // TAP reset
177 
    clear_i     , // clear CRC register
178 
    enable_i    , // enable CRC calculation
179 
    shift_i     , // shift CRC register
180 
    data_i      , // serial DATA input
181 
    crc_msb_o   , // serial CRC output
182 
    crc_ok_o      // CRC status
183 
) ;
184 
input           clk_i       ;
185 
input           rst_i       ;
186 
input           clear_i     ;
187 
input           enable_i    ;
188 
input           shift_i     ;
189 
input           data_i      ;
190 
output          crc_msb_o   ;
191 
output          crc_ok_o    ;
192 
reg     [ 7: 0] crc_reg         ;
193 
wire    [ 7: 0] crc_poly        ;
194 
wire            poly_sel        ;
195 
wire            crc_reg_msb     ;
196 
wire            crc_poly_msb    ;
197 
assign  crc_poly = 8'h83 ;
198 
assign  crc_reg_msb  = crc_reg [7] ;
199 
assign  crc_poly_msb = crc_poly[7] ;
200 
assign  poly_sel = (data_i) ^^ (crc_poly_msb && crc_reg_msb) ;
201 
always @(posedge clk_i or posedge rst_i)
202 
    begin
203 
        if (rst_i)
204 
            crc_reg <= 8'h00;
205 
        else if (clear_i)
206 
            crc_reg <= 8'h00;
207 
        else if (enable_i) begin
208 
            crc_reg[7] <= crc_reg[6] ^ (crc_poly[6] & poly_sel) ;
209 
            crc_reg[6] <= crc_reg[5] ^ (crc_poly[5] & poly_sel) ;
210 
            crc_reg[5] <= crc_reg[4] ^ (crc_poly[4] & poly_sel) ;
211 
            crc_reg[4] <= crc_reg[3] ^ (crc_poly[3] & poly_sel) ;
212 
            crc_reg[3] <= crc_reg[2] ^ (crc_poly[2] & poly_sel) ;
213 
            crc_reg[2] <= crc_reg[1] ^ (crc_poly[1] & poly_sel) ;
214 
            crc_reg[1] <= crc_reg[0] ^ (crc_poly[0] & poly_sel) ;
215 
            crc_reg[0] <= poly_sel ;
216 
        end
217 
        else if (shift_i)
218 
            crc_reg[7:0] <= {crc_reg[6:0], 1'b0} ;
219 
    end
220 
assign  crc_ok_o  = ~(|crc_reg) ;
221 
assign  crc_msb_o = crc_reg_msb ;
222 
endmodule
223 
// debug_if_bus_module.v
224 
// debug_if_defines.v
225 
// synopsys translate_off
226 
// timescale.v
227 
`timescale 1ns/10ps
228 
// synopsys translate_on
229 
module debug_if_bus_module
230 
(
231 
    tck_pad_i           , // JTAG Test ClocK pad
232 
    trst_neg_pad_i      , // JTAG Test ReSeT negated pad
233 
    mod_tap_reset_i     ,
234 
    mod_clear_i         ,
235 
    mod_sync_cmd_i      ,
236 
    mod_sync_stat_i     ,
237 
    mod_synced_cmd_o    ,
238 
    mod_synced_stat_o   ,
239 
    mod_command_i       ,
240 
    mod_byte_sel_i      ,
241 
    mod_address_i       ,
242 
    mod_write_data_i    ,
243 
    mod_read_data_o     ,
244 
    mod_bus_ack_o       ,
245 
    mod_bus_rty_o       ,
246 
    mod_bus_err_o       ,
247 
    wb_clk_i            ,
248 
    wb_rst_i            ,
249 
    wb_cyc_o            ,
250 
    wb_stb_o            ,
251 
    wb_we_o             ,
252 
    wb_sel_o            ,
253 
    wb_adr_o            ,
254 
    wb_dat_o            ,
255 
    wb_dat_i            ,
256 
    wb_ack_i            ,
257 
    wb_rty_i            ,
258 
    wb_err_i            ,
259 
    cpu_bp_i            ,
260 
    cpu_stall_o         ,
261 
    cpu_rst_o
262 
) ;
263 
input           tck_pad_i           ; // JTAG Test ClocK pad
264 
input           trst_neg_pad_i      ; // JTAG Test ReSeT negated pad
265 
input           mod_tap_reset_i     ;
266 
input           mod_clear_i         ;
267 
input           mod_sync_cmd_i      ;
268 
input           mod_sync_stat_i     ;
269 
output          mod_synced_cmd_o    ;
270 
output          mod_synced_stat_o   ;
271 
input   [ 3: 0] mod_command_i       ;
272 
input   [ 3: 0] mod_byte_sel_i      ;
273 
input   [31: 0] mod_address_i       ;
274 
input   [31: 0] mod_write_data_i    ;
275 
output  [31: 0] mod_read_data_o     ;
276 
output          mod_bus_ack_o       ;
277 
output          mod_bus_rty_o       ;
278 
output          mod_bus_err_o       ;
279 
input           wb_clk_i            ;
280 
input           wb_rst_i            ;
281 
output          wb_cyc_o            ;
282 
output          wb_stb_o            ;
283 
output          wb_we_o             ;
284 
output  [ 3: 0] wb_sel_o            ;
285 
output  [31: 0] wb_adr_o            ;
286 
output  [31: 0] wb_dat_o            ;
287 
input   [31: 0] wb_dat_i            ;
288 
input           wb_ack_i            ;
289 
input           wb_rty_i            ;
290 
input           wb_err_i            ;
291 
input           cpu_bp_i            ;
292 
output          cpu_stall_o         ;
293 
output          cpu_rst_o           ;
294 
reg             wb_cyc_o            ;
295 
reg             wb_stb_o            ;
296 
reg             wb_we_o             ;
297 
wire    [ 3: 0] src_mod_sync            ;
298 
wire    [ 3: 0] dst_mod_sync            ;
299 
wire            dst_mod_sync_cmd        ;
300 
wire            dst_mod_sync_stat       ;
301 
wire            wb_mod_clear            ;
302 
wire            wb_tap_reset            ;
303 
reg             dst_mod_sync_cmd_d1     ;
304 
reg             dst_mod_sync_cmd_d2     ;
305 
reg             dst_mod_sync_stat_d     ;
306 
wire    [ 1: 0] src_mod_synced          ;
307 
wire    [ 1: 0] dst_mod_synced          ;
308 
wire            dst_mod_synced_cmd      ;
309 
wire            dst_mod_synced_stat     ;
310 
reg             dst_mod_synced_stat_d   ;
311 
wire    [71: 0] src_mod_data            ;
312 
wire    [71: 0] dst_mod_data            ;
313 
wire            dst_mod_data_sync_en    ;
314 
wire    [ 3: 0] dst_command             ;
315 
wire    [ 3: 0] dst_byte_sel            ;
316 
wire    [31: 0] dst_address             ;
317 
wire    [31: 0] dst_write_data          ;
318 
wire    [34: 0] src_wb_data             ;
319 
wire    [34: 0] dst_wb_data             ;
320 
wire            dst_wb_data_clk_en      ;
321 
reg             mod_clear_d             ;
322 
wire            command_valid           ;
323 
reg             status_ready            ;
324 
reg             src_wb_ack              ;
325 
reg             src_wb_rty              ;
326 
reg             src_wb_err              ;
327 
reg             cpu_stall_reg           ;
328 
reg             cpu_reset_reg           ;
329 
reg     [31: 0] src_wb_rdat             ;
330 
assign  src_mod_sync[3:0]   = {mod_tap_reset_i, mod_clear_i, mod_sync_stat_i, mod_sync_cmd_i} ;
331 
debug_if_to_mod_synchronization_module #(4, 8) i_debug_if_to_mod_synchronization_module  // #(width, reset) value
332 
(
333 
    .src_rst_i      (   trst_neg_pad_i      ),
334 
    .src_clr_i      (   mod_tap_reset_i     ),
335 
    .src_clk_i      (   tck_pad_i           ),
336 
    .src_clk_en_i   (   1'b1                ),
337 
    .src_mux_comb_i (   1'b0                ),
338 
    .src_i          (   src_mod_sync        ),
339 
    .src_o          (                       ),
340 
    .sff_rst_i      (   wb_rst_i            ),
341 
    .sff_clr_i      (   1'b0                ),
342 
    .sff_clk_i      (   wb_clk_i            ),
343 
    .sff_clk_en_i   (   1'b1                ),
344 
    .sff_o          (                       ),
345 
    .dst_rst_i      (   wb_rst_i            ),
346 
    .dst_clr_i      (   1'b0                ),
347 
    .dst_clk_i      (   wb_clk_i            ),
348 
    .dst_clk_en_i   (   1'b1                ),
349 
    .dst_o          (   dst_mod_sync        )
350 
) ;
351 
assign  dst_mod_sync_cmd  = dst_mod_sync[0] ;
352 
assign  dst_mod_sync_stat = dst_mod_sync[1] ;
353 
assign  wb_mod_clear      = dst_mod_sync[2] ;
354 
assign  wb_tap_reset      = dst_mod_sync[3] ;
355 
always @(posedge wb_clk_i undefined)
356 
    begin
357 
        if (wb_rst_i == undefined) begin
358 
            dst_mod_sync_cmd_d1 <= 1'b0 ;
359 
            dst_mod_sync_cmd_d2 <= 1'b0 ;
360 
            dst_mod_sync_stat_d <= 1'b0 ;
361 
        end
362 
        else begin
363 
            dst_mod_sync_cmd_d1 <= dst_mod_sync_cmd    ;
364 
            dst_mod_sync_cmd_d2 <= dst_mod_sync_cmd_d1 ;
365 
            if (dst_mod_sync_stat && !dst_mod_sync_stat_d && status_ready)
366 
                dst_mod_sync_stat_d <= 1'b1 ;
367 
            else if (!dst_mod_sync_stat)
368 
                dst_mod_sync_stat_d <= 1'b0 ;
369 
        end
370 
    end
371 
assign  src_mod_synced[1:0] = {dst_mod_sync_stat_d, dst_mod_sync_cmd_d1} ;
372 
debug_if_from_mod_synchronization_module #(2, 0) i_debug_if_from_mod_synchronization_module  // #(width, reset) value
373 
(
374 
    .src_rst_i      (   wb_rst_i            ),
375 
    .src_clr_i      (   1'b0                ),
376 
    .src_clk_i      (   wb_clk_i            ),
377 
    .src_clk_en_i   (   1'b1                ),
378 
    .src_mux_comb_i (   1'b0                ),
379 
    .src_i          (   src_mod_synced      ),
380 
    .src_o          (                       ),
381 
    .sff_rst_i      (   trst_neg_pad_i      ),
382 
    .sff_clr_i      (   mod_tap_reset_i     ),
383 
    .sff_clk_i      (   tck_pad_i           ),
384 
    .sff_clk_en_i   (   1'b1                ),
385 
    .sff_o          (                       ),
386 
    .dst_rst_i      (   trst_neg_pad_i      ),
387 
    .dst_clr_i      (   mod_tap_reset_i     ),
388 
    .dst_clk_i      (   tck_pad_i           ),
389 
    .dst_clk_en_i   (   1'b1                ),
390 
    .dst_o          (   dst_mod_synced      )
391 
) ;
392 
assign  dst_mod_synced_cmd  = dst_mod_synced[0] ;
393 
assign  dst_mod_synced_stat = dst_mod_synced[1] ;
394 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
395 
    begin
396 
        if (trst_neg_pad_i)
397 
            dst_mod_synced_stat_d <= 1'b0 ;
398 
        else if (mod_tap_reset_i)
399 
            dst_mod_synced_stat_d <= 1'b0 ;
400 
        else
401 
            dst_mod_synced_stat_d <= dst_mod_synced_stat ;
402 
    end
403 
assign  mod_synced_cmd_o  = dst_mod_synced_cmd    ;
404 
assign  mod_synced_stat_o = dst_mod_synced_stat_d ;
405 
assign  src_mod_data[71:0]   = {mod_command_i[3:0],  mod_byte_sel_i[3:0],
406 
                                mod_address_i[31:0], mod_write_data_i[31:0]} ;
407 
assign  dst_mod_data_sync_en = dst_mod_sync_cmd && !dst_mod_sync_cmd_d1 ;
408 
debug_if_to_mod_synchronization_module #(72, 0) i1_debug_if_to_mod_synchronization_module // #(width, reset) value
409 
(
410 
    .src_rst_i      (   1'b1                            ),
411 
    .src_clr_i      (   1'b1                            ),
412 
    .src_clk_i      (   1'b1                            ),
413 
    .src_clk_en_i   (   1'b1                            ),
414 
    .src_mux_comb_i (   1'b1                            ),
415 
    .src_i          (   src_mod_data                    ),
416 
    .src_o          (                                   ),
417 
    .sff_rst_i      (   wb_rst_i                        ),
418 
    .sff_clr_i      (   1'b0                            ),
419 
    .sff_clk_i      (   wb_clk_i                        ),
420 
    .sff_clk_en_i   (   dst_mod_data_sync_en            ),
421 
    .sff_o          (   dst_mod_data                    ),
422 
    .dst_rst_i      (   undefined    ),
423 
    .dst_clr_i      (   1'b1                            ),
424 
    .dst_clk_i      (   1'b1                            ),
425 
    .dst_clk_en_i   (   1'b1                            ),
426 
    .dst_o          (                                   )
427 
) ;
428 
assign  dst_command   [ 3:0] = dst_mod_data[71:68] ;
429 
assign  dst_byte_sel  [ 3:0] = dst_mod_data[67:64] ;
430 
assign  dst_address   [31:0] = dst_mod_data[63:32] ;
431 
assign  dst_write_data[31:0] = dst_mod_data[31: 0] ;
432 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
433 
    begin
434 
        if (trst_neg_pad_i)
435 
            mod_clear_d <= 1'b1 ;
436 
        else if (mod_tap_reset_i)
437 
            mod_clear_d <= 1'b1 ;
438 
        else
439 
            mod_clear_d <= mod_clear_i ;
440 
    end
441 
assign  src_wb_data[ 2:0]  = mod_clear_i ? 3'h0 : {src_wb_ack, src_wb_rty, src_wb_err} ;
442 
assign  src_wb_data[34:3]  = src_wb_rdat[31:0] ;
443 
assign  dst_wb_data_clk_en = (dst_mod_synced_stat && !dst_mod_synced_stat_d) ||
444 
                             (mod_clear_i         && !mod_clear_d) ;
445 
debug_if_from_mod_synchronization_module #(35, 0) i1_debug_if_from_mod_synchronization_module  // #(width, reset) value
446 
(
447 
    .src_rst_i      (   undefined  ),
448 
    .src_clr_i      (   1'b1                            ),
449 
    .src_clk_i      (   1'b1                            ),
450 
    .src_clk_en_i   (   1'b1                            ),
451 
    .src_mux_comb_i (   1'b1                            ),
452 
    .src_i          (   src_wb_data                     ),
453 
    .src_o          (                                   ),
454 
    .sff_rst_i      (   trst_neg_pad_i                  ),
455 
    .sff_clr_i      (   mod_tap_reset_i                 ),
456 
    .sff_clk_i      (   tck_pad_i                       ),
457 
    .sff_clk_en_i   (   dst_wb_data_clk_en              ),
458 
    .sff_o          (   dst_wb_data                     ),
459 
    .dst_rst_i      (   1'b1                            ),
460 
    .dst_clr_i      (   1'b1                            ),
461 
    .dst_clk_i      (   1'b1                            ),
462 
    .dst_clk_en_i   (   1'b1                            ),
463 
    .dst_o          (                                   )
464 
) ;
465 
assign  mod_read_data_o = dst_wb_data[34:3] ;
466 
assign  mod_bus_ack_o   = dst_wb_data[2]    ;
467 
assign  mod_bus_rty_o   = dst_wb_data[1]    ;
468 
assign  mod_bus_err_o   = dst_wb_data[0]    ;
469 
assign  command_valid = dst_mod_sync_cmd_d1 && !dst_mod_sync_cmd_d2 ;
470 
always @(posedge wb_clk_i undefined)
471 
    begin
472 
        if (wb_rst_i == undefined)
473 
            status_ready <= 1'b0 ;
474 
        else if (wb_tap_reset)
475 
            status_ready <= 1'b0 ;
476 
        else begin
477 
            if (command_valid)
478 
                status_ready <= 1'b0 ;
479 
            else if ( (dst_command[3:0] == 4'd04) ||
480 
                      (dst_command[3:0] == 4'd05)      ||
481 
                      (dst_command[3:0] == 4'd06)       ||
482 
                      (((dst_command[3:0] == 4'd02) ||
483 
                        (dst_command[3:0] == 4'd03)) &&
484 
                       (wb_stb_o && (wb_ack_i || wb_rty_i || wb_err_i))) )
485 
                status_ready <= 1'b1 ;
486 
        end
487 
    end
488 
assign  wb_sel_o = dst_byte_sel  [ 3:0] ;
489 
assign  wb_adr_o = dst_address   [31:0] ;
490 
assign  wb_dat_o = dst_write_data[31:0] ;
491 
always @(posedge wb_clk_i undefined)
492 
    begin
493 
        if (wb_rst_i == undefined) begin
494 
            wb_cyc_o <= 1'b0 ;
495 
            wb_stb_o <= 1'b0 ;
496 
            wb_we_o  <= 1'b0 ;
497 
        end
498 
        else if (wb_tap_reset) begin
499 
            wb_cyc_o <= 1'b0 ;
500 
            wb_stb_o <= 1'b0 ;
501 
            wb_we_o  <= 1'b0 ;
502 
        end
503 
        else begin
504 
            if (wb_ack_i || wb_rty_i || wb_err_i ||
505 
                (command_valid &&
506 
                 (dst_command[3:0] == 4'd04))) begin
507 
                wb_cyc_o <= 1'b0 ;
508 
                wb_stb_o <= 1'b0 ;
509 
            end
510 
            else if (command_valid &&
511 
                     ((dst_command[3:0] == 4'd02) ||
512 
                      (dst_command[3:0] == 4'd03))) begin
513 
                wb_cyc_o <= 1'b1 ;
514 
                wb_stb_o <= 1'b1 ;
515 
            end
516 
            if (command_valid && (dst_command[3:0] == 4'd02))
517 
                wb_we_o  <= 1'b1 ;
518 
            else if (command_valid && (dst_command[3:0] == 4'd03))
519 
                wb_we_o  <= 1'b0 ;
520 
        end
521 
    end
522 
always @(posedge wb_clk_i undefined)
523 
    begin
524 
        if (wb_rst_i == undefined) begin
525 
            src_wb_ack <= 1'b0 ;
526 
            src_wb_rty <= 1'b0 ;
527 
            src_wb_err <= 1'b0 ;
528 
        end
529 
        else if (wb_tap_reset) begin
530 
            src_wb_ack <= 1'b0 ;
531 
            src_wb_rty <= 1'b0 ;
532 
            src_wb_err <= 1'b0 ;
533 
        end
534 
        else if (wb_stb_o && (wb_ack_i || wb_rty_i || wb_err_i)) begin
535 
            src_wb_ack <= wb_ack_i ;
536 
            src_wb_rty <= wb_rty_i ;
537 
            src_wb_err <= wb_err_i ;
538 
        end
539 
        else if (command_valid) begin
540 
            src_wb_ack <= 1'b0 ;
541 
            src_wb_rty <= 1'b0 ;
542 
            src_wb_err <= 1'b0 ;
543 
        end
544 
        else if (wb_mod_clear) begin
545 
            src_wb_ack <= 1'b0 ;
546 
            src_wb_rty <= 1'b0 ;
547 
            src_wb_err <= 1'b0 ;
548 
        end
549 
    end
550 
always @(posedge wb_clk_i undefined)
551 
    begin
552 
        if (wb_rst_i == undefined) begin
553 
            cpu_stall_reg <= 1'b0 ;
554 
            cpu_reset_reg <= 1'b0 ;
555 
        end
556 
        else if (wb_tap_reset) begin
557 
            cpu_stall_reg <= 1'b0 ;
558 
            cpu_reset_reg <= 1'b0 ;
559 
        end
560 
        else begin
561 
            if (cpu_bp_i)
562 
                cpu_stall_reg <= 1'b1 ;
563 
            else if (command_valid && (dst_command[3:0] == 4'd05))
564 
                cpu_stall_reg <= dst_write_data[0] ;
565 
            if (command_valid && (dst_command[3:0] == 4'd05))
566 
                cpu_reset_reg <= dst_write_data[1] ;
567 
        end
568 
    end
569 
assign  cpu_stall_o = cpu_stall_reg || cpu_bp_i ;
570 
assign  cpu_rst_o   = cpu_reset_reg ;
571 
always @(posedge wb_clk_i/* undefined*/)
572 
    begin
573 
        if (wb_rst_i == undefined)
574 
            src_wb_rdat[31:0] <= 32'h0 ;
575 
        else if (wb_tap_reset)
576 
            src_wb_rdat[31:0] <= 32'h0 ;
577 
        else begin
578 
            if (wb_stb_o && wb_ack_i && (dst_command[3:0] == 4'd03))
579 
                src_wb_rdat[31:0] <= wb_dat_i ;
580 
            else if (command_valid && (dst_command[3:0] == 4'd06))
581 
                src_wb_rdat[31:0] <= 32'h0 | (cpu_reset_reg << 1) |
582 
                                             (cpu_stall_reg << 0) ;
583 
        end
584 
    end
585 
endmodule
586 
// debug_if.v
587 
// debug_if_defines.v
588 
// synopsys translate_off
589 
// timescale.v
590 
`timescale 1ns/10ps
591 
// synopsys translate_on
592 
module debug_if
593 
(
594 
    tck_pad_i       , // JTAG Test ClocK pad
595 
    trst_neg_pad_i  , // JTAG Test ReSeT negated pad
596 
    tdi_i           , // TAP TDO signal
597 
    tdo_o           , // DEBUG TDO signal
598 
    debug_select_i  ,
599 
    capture_dr_i    ,
600 
    shift_dr_i      ,
601 
    pause_dr_i      ,
602 
    update_dr_i     ,
603 
    mod_wb_clk_i    ,
604 
    mod_wb_rst_i    ,
605 
    mod_wb_cyc_o    ,
606 
    mod_wb_stb_o    ,
607 
    mod_wb_we_o     ,
608 
    mod_wb_sel_o    ,
609 
    mod_wb_adr_o    ,
610 
    mod_wb_dat_o    ,
611 
    mod_wb_dat_i    ,
612 
    mod_wb_ack_i    ,
613 
    mod_wb_rty_i    ,
614 
    mod_wb_err_i    ,
615 
    mod_cpu_bp_i    ,
616 
    mod_cpu_stall_o ,
617 
    mod_cpu_rst_o
618 
) ;
619 
input           tck_pad_i           ; // JTAG Test ClocK pad
620 
input           trst_neg_pad_i      ; // JTAG Test ReSeT negated pad
621 
input           tdi_i               ; // TAP TDO signal
622 
output          tdo_o               ; // DEBUG TDO signal
623 
input           debug_select_i      ;
624 
input           capture_dr_i        ;
625 
input           shift_dr_i          ;
626 
input           pause_dr_i          ;
627 
input           update_dr_i         ;
628 
input   [   (4'd1+1)-1: 0] mod_wb_clk_i ;
629 
input   [   (4'd1+1)-1: 0] mod_wb_rst_i ;
630 
output  [   (4'd1+1)-1: 0] mod_wb_cyc_o ;
631 
output  [   (4'd1+1)-1: 0] mod_wb_stb_o ;
632 
output  [   (4'd1+1)-1: 0] mod_wb_we_o  ;
633 
output  [ 4*(4'd1+1)-1: 0] mod_wb_sel_o ;
634 
output  [32*(4'd1+1)-1: 0] mod_wb_adr_o ;
635 
output  [32*(4'd1+1)-1: 0] mod_wb_dat_o ;
636 
input   [32*(4'd1+1)-1: 0] mod_wb_dat_i ;
637 
input   [   (4'd1+1)-1: 0] mod_wb_ack_i ;
638 
input   [   (4'd1+1)-1: 0] mod_wb_rty_i ;
639 
input   [   (4'd1+1)-1: 0] mod_wb_err_i ;
640 
input   [   (4'd1+1)-1: 0] mod_cpu_bp_i    ;
641 
output  [   (4'd1+1)-1: 0] mod_cpu_stall_o ;
642 
output  [   (4'd1+1)-1: 0] mod_cpu_rst_o   ;
643 
reg             tdo_o               ;
644 
reg     [ 6: 0] shift_cnt           ;
645 
reg     [79: 0] shift_reg           ;
646 
wire            latch_module_valid  ;
647 
wire            latch_cancel_valid  ;
648 
wire            latch_reg_valid     ;
649 
reg     [15: 0] cs_module           ;
650 
reg     [ 3: 0] cs_modnum           ;
651 
reg     [ 3: 0] command             ;
652 
reg     [ 3: 0] byte_sel            ;
653 
reg     [31: 0] address             ;
654 
reg     [31: 0] write_data          ;
655 
reg     [31: 0] read_data           ;
656 
wire            bus_ack             ;
657 
wire            bus_rty             ;
658 
wire            bus_err             ;
659 
wire    [ 7: 0] impl_ver            ;
660 
wire    [ 7: 0] debug_ver           ;
661 
wire    [23: 0] status              ;
662 
reg             stat_crc_err        ;
663 
reg             stat_overrun        ;
664 
reg             stat_wrong_mod      ;
665 
reg             stat_bus_err        ;
666 
reg             stat_bus_rty        ;
667 
reg             stat_bus_ack        ;
668 
wire            stat_hw_busy        ;
669 
wire            stat_hw_sync        ;
670 
reg             stat_hw_busy_reg    ;
671 
reg             stat_hw_sync_reg    ;
672 
reg             stat_wrong_cmd      ;
673 
wire            crc_out_clear       ;
674 
wire            crc_out_enable      ;
675 
wire            crc_out_shift       ;
676 
wire            crc_in_clear        ;
677 
wire            crc_in_enable       ;
678 
wire            crc_in_shift        ;
679 
wire            crc_out_msb         ;
680 
wire            crc_in_ok           ;
681 
reg             crc_in_ok_reg       ;
682 
reg     [2:0] cur_state ;
683 
reg     [2:0] nxt_state ;
684 
reg             tap_reset           ;
685 
reg             sync_cmd            ;
686 
reg             sync_stat           ;
687 
wire            synced_cmd          ;
688 
wire            synced_stat         ;
689 
reg             synced_stat_d       ;
690 
wire            mod_tap_reset       ;
691 
wire    [15: 0] mod_clear           ;
692 
wire    [15: 0] mod_sync_cmd        ;
693 
wire    [15: 0] mod_sync_stat       ;
694 
wire    [15: 0] mod_synced_cmd      ;
695 
wire    [15: 0] mod_synced_stat     ;
696 
wire   [511: 0] mod_read_data       ;
697 
wire    [15: 0] mod_bus_ack         ;
698 
wire    [15: 0] mod_bus_rty         ;
699 
wire    [15: 0] mod_bus_err         ;
700 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
701 
    begin
702 
        if (trst_neg_pad_i)
703 
            shift_cnt <= 7'd0 ;
704 
        else if (!debug_select_i)
705 
            shift_cnt <= 7'd0 ;
706 
        else begin
707 
            if (capture_dr_i)
708 
                shift_cnt <= 7'd0 ;
709 
            else if (shift_dr_i && (shift_cnt < 7'd82))
710 
                shift_cnt <= shift_cnt + 1'b1 ;
711 
        end
712 
    end
713 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
714 
    begin
715 
        if (trst_neg_pad_i)
716 
            shift_reg[79:0] <= 80'h0 ;
717 
        else if (!debug_select_i)
718 
            shift_reg[79:0] <= 80'h0 ;
719 
        else begin
720 
            if (capture_dr_i) begin
721 
                shift_reg[79:72] <= 8'h0 ;
722 
                shift_reg[71:40] <= read_data[31:0] ;
723 
                shift_reg[39:16] <= status   [23:0] ;
724 
                shift_reg[15: 8] <= impl_ver [ 7:0] ;
725 
                shift_reg[ 7: 0] <= debug_ver[ 7:0] ;
726 
            end
727 
            else if (shift_dr_i)
728 
                shift_reg[79:0] <= {tdi_i, shift_reg[79:1]} ;
729 
        end
730 
    end
731 
always @(shift_cnt or shift_reg or crc_out_msb)
732 
    begin
733 
        if ((shift_cnt >= 7'd72) && (shift_cnt < 7'd80))
734 
            tdo_o = crc_out_msb ;
735 
        else
736 
            tdo_o = shift_reg[0] ;
737 
    end
738 
assign  latch_module_valid = crc_in_ok_reg &&
739 
            (shift_reg[3:0] == 4'd01) && !stat_hw_busy_reg &&
740 
            (shift_reg[43:40] <= 4'd1) ;
741 
assign  latch_cancel_valid = crc_in_ok_reg &&
742 
            (shift_reg[3:0] == 4'd04) && !stat_hw_sync_reg ;
743 
assign  latch_reg_valid = crc_in_ok_reg &&
744 
            (((shift_reg[3:0] == 4'd02  ) && !stat_hw_busy_reg) ||
745 
             ((shift_reg[3:0] == 4'd03   ) && !stat_hw_busy_reg) ||
746 
             ((shift_reg[3:0] == 4'd05) && !stat_hw_busy_reg) ||
747 
             ((shift_reg[3:0] == 4'd06 ) && !stat_hw_busy_reg)) ;
748 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
749 
    begin
750 
        if (trst_neg_pad_i) begin
751 
            cs_module[15:0] <= 16'h1 ;
752 
            cs_modnum       <=  4'd0 ;
753 
        end
754 
        else if (!debug_select_i) begin
755 
            cs_module[15:0] <= 16'h1 ;
756 
            cs_modnum       <=  4'd0 ;
757 
        end
758 
        else if (update_dr_i && latch_module_valid) begin
759 
            case (shift_reg[43:40])
760 
            4'd15 : cs_module[15:0] <= 16'h8000 ;
761 
            4'd14 : cs_module[15:0] <= 16'h4000 ;
762 
            4'd13 : cs_module[15:0] <= 16'h2000 ;
763 
            4'd12 : cs_module[15:0] <= 16'h1000 ;
764 
            4'd11 : cs_module[15:0] <= 16'h0800 ;
765 
            4'd10 : cs_module[15:0] <= 16'h0400 ;
766 
            4'd09  : cs_module[15:0] <= 16'h0200 ;
767 
            4'd08  : cs_module[15:0] <= 16'h0100 ;
768 
            4'd07  : cs_module[15:0] <= 16'h0080 ;
769 
            4'd06  : cs_module[15:0] <= 16'h0040 ;
770 
            4'd05  : cs_module[15:0] <= 16'h0020 ;
771 
            4'd04  : cs_module[15:0] <= 16'h0010 ;
772 
            4'd03  : cs_module[15:0] <= 16'h0008 ;
773 
            4'd02  : cs_module[15:0] <= 16'h0004 ;
774 
            4'd01  : cs_module[15:0] <= 16'h0002 ;
775 
            4'd00  : cs_module[15:0] <= 16'h0001 ;
776 
            default                 : cs_module[15:0] <= 16'hxxxx ;
777 
            endcase
778 
            case (shift_reg[43:40])
779 
            4'd15 : cs_modnum <= 4'd15 ;
780 
            4'd14 : cs_modnum <= 4'd14 ;
781 
            4'd13 : cs_modnum <= 4'd13 ;
782 
            4'd12 : cs_modnum <= 4'd12 ;
783 
            4'd11 : cs_modnum <= 4'd11 ;
784 
            4'd10 : cs_modnum <= 4'd10 ;
785 
            4'd09  : cs_modnum <= 4'd9  ;
786 
            4'd08  : cs_modnum <= 4'd8  ;
787 
            4'd07  : cs_modnum <= 4'd7  ;
788 
            4'd06  : cs_modnum <= 4'd6  ;
789 
            4'd05  : cs_modnum <= 4'd5  ;
790 
            4'd04  : cs_modnum <= 4'd4  ;
791 
            4'd03  : cs_modnum <= 4'd3  ;
792 
            4'd02  : cs_modnum <= 4'd2  ;
793 
            4'd01  : cs_modnum <= 4'd1  ;
794 
            4'd00  : cs_modnum <= 4'd0  ;
795 
            default                 : cs_modnum <= 4'hx  ;
796 
            endcase
797 
        end
798 
    end
799 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
800 
    begin
801 
        if (trst_neg_pad_i)
802 
            command[3:0] <= 4'd04 ;
803 
        else if (!debug_select_i)
804 
            command[3:0] <= 4'd04 ;
805 
        else if (update_dr_i && (latch_reg_valid || latch_cancel_valid))
806 
            command[3:0] <= shift_reg[3:0] ;
807 
    end
808 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
809 
    begin
810 
        if (trst_neg_pad_i)
811 
            byte_sel[3:0] <= 4'h0 ;
812 
        else if (!debug_select_i)
813 
            byte_sel[3:0] <= 4'h0 ;
814 
        else if (debug_select_i && update_dr_i && latch_reg_valid)
815 
            byte_sel[3:0] <= shift_reg[7:4] ;
816 
    end
817 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
818 
    begin
819 
        if (trst_neg_pad_i)
820 
            address[31:0] <= 32'h0 ;
821 
        else if (!debug_select_i)
822 
            address[31:0] <= 32'h0 ;
823 
        else if (debug_select_i && update_dr_i && latch_reg_valid)
824 
            address[31:0] <= shift_reg[39:8] ;
825 
    end
826 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
827 
    begin
828 
        if (trst_neg_pad_i)
829 
            write_data[31:0] <= 32'h0 ;
830 
        else if (!debug_select_i)
831 
            write_data[31:0] <= 32'h0 ;
832 
        else if (debug_select_i && update_dr_i && latch_reg_valid)
833 
            write_data[31:0] <= shift_reg[71:40] ;
834 
    end
835 
assign  impl_ver[7:0] = 8'h00 ;
836 
assign  debug_ver[7:0] = 8'h03 ;
837 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
838 
    begin
839 
        if (trst_neg_pad_i)
840 
            stat_crc_err <= 1'b0 ;
841 
        else if (!debug_select_i)
842 
            stat_crc_err <= 1'b0 ;
843 
        else begin
844 
            if (update_dr_i && crc_in_ok_reg)
845 
                stat_crc_err <= 1'b0 ;
846 
            else if (update_dr_i)
847 
                stat_crc_err <= 1'b1 ;
848 
        end
849 
    end
850 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
851 
    begin
852 
        if (trst_neg_pad_i)
853 
            stat_overrun <= 1'b0 ;
854 
        else if (!debug_select_i)
855 
            stat_overrun <= 1'b0 ;
856 
        else begin
857 
            if (update_dr_i &&
858 
                (((shift_reg[3:0] == 4'd02  ) && stat_hw_busy_reg) ||
859 
                 ((shift_reg[3:0] == 4'd03   ) && stat_hw_busy_reg) ||
860 
                 ((shift_reg[3:0] == 4'd05) && stat_hw_busy_reg) ||
861 
                 ((shift_reg[3:0] == 4'd06 ) && stat_hw_busy_reg) ||
862 
                 ((shift_reg[3:0] == 4'd01   ) && stat_hw_busy_reg) ||
863 
                 ((shift_reg[3:0] == 4'd04) && stat_hw_sync_reg)))
864 
                stat_overrun <= 1'b1 ;
865 
            else if (update_dr_i)
866 
                stat_overrun <= 1'b0 ;
867 
        end
868 
    end
869 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
870 
    begin
871 
        if (trst_neg_pad_i)
872 
            stat_wrong_mod <= 1'b0 ;
873 
        else if (!debug_select_i)
874 
            stat_wrong_mod <= 1'b0 ;
875 
        else begin
876 
            if (update_dr_i &&
877 
                (shift_reg[3:0] == 4'd01) &&
878 
                (shift_reg[43:40] > 4'd1))
879 
                stat_wrong_mod <= 1'b1 ;
880 
            else if (update_dr_i)
881 
                stat_wrong_mod <= 1'b0 ;
882 
        end
883 
    end
884 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
885 
    begin
886 
        if (trst_neg_pad_i) begin
887 
            stat_bus_ack <= 1'b0 ;
888 
            stat_bus_rty <= 1'b0 ;
889 
            stat_bus_err <= 1'b0 ;
890 
        end
891 
        else if (!debug_select_i) begin
892 
            stat_bus_ack <= 1'b0 ;
893 
            stat_bus_rty <= 1'b0 ;
894 
            stat_bus_err <= 1'b0 ;
895 
        end
896 
        else begin
897 
            if (update_dr_i && !stat_hw_busy_reg) begin
898 
                stat_bus_ack <= 1'b0 ;
899 
                stat_bus_rty <= 1'b0 ;
900 
                stat_bus_err <= 1'b0 ;
901 
            end
902 
            else if (synced_stat && !synced_stat_d) begin
903 
                stat_bus_ack <= bus_ack ;
904 
                stat_bus_rty <= bus_rty ;
905 
                stat_bus_err <= bus_err ;
906 
            end
907 
        end
908 
    end
909 
assign  stat_hw_busy = sync_cmd || synced_cmd || sync_stat || synced_stat ;
910 
assign  stat_hw_sync = sync_cmd || synced_cmd ;
911 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
912 
    begin
913 
        if (trst_neg_pad_i) begin
914 
            stat_hw_busy_reg <= 1'b0 ;
915 
            stat_hw_sync_reg <= 1'b0 ;
916 
        end
917 
        else if (!debug_select_i) begin
918 
            stat_hw_busy_reg <= 1'b0 ;
919 
            stat_hw_sync_reg <= 1'b0 ;
920 
        end
921 
        else begin
922 
            if (capture_dr_i) begin
923 
                stat_hw_busy_reg <= stat_hw_busy ;
924 
                stat_hw_sync_reg <= stat_hw_sync ;
925 
            end
926 
        end
927 
    end
928 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
929 
    begin
930 
        if (trst_neg_pad_i)
931 
            stat_wrong_cmd <= 1'b0 ;
932 
        else if (!debug_select_i)
933 
            stat_wrong_cmd <= 1'b0 ;
934 
        else begin
935 
            if (update_dr_i &&
936 
                ((shift_reg[3:0] == 4'd00      ) ||
937 
                 (shift_reg[3:0] == 4'd02  ) ||
938 
                 (shift_reg[3:0] == 4'd03   ) ||
939 
                 (shift_reg[3:0] == 4'd05) ||
940 
                 (shift_reg[3:0] == 4'd06 ) ||
941 
                 (shift_reg[3:0] == 4'd01   ) ||
942 
                 (shift_reg[3:0] == 4'd04)))
943 
                stat_wrong_cmd <= 1'b0 ;
944 
            else if (update_dr_i)
945 
                stat_wrong_cmd <= 1'b1 ;
946 
        end
947 
    end
948 
assign  status[0]   = stat_crc_err   ;
949 
assign  status[1]   = stat_overrun   ;
950 
assign  status[2] = stat_wrong_mod ;
951 
assign  status[3]   = stat_bus_err   ;
952 
assign  status[4]   = stat_bus_rty   ;
953 
assign  status[5]   = stat_bus_ack   ;
954 
assign  status[6]   = stat_hw_busy   ;
955 
assign  status[7] = stat_wrong_cmd ;
956 
assign  status[23:8] = 'h0 ;
957 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
958 
    begin
959 
        if (trst_neg_pad_i)
960 
            synced_stat_d <= 1'b0 ;
961 
        else if (!debug_select_i)
962 
            synced_stat_d <= 1'b0 ;
963 
        else
964 
            synced_stat_d <= synced_stat ;
965 
    end
966 
assign  crc_out_clear   = capture_dr_i ;
967 
assign  crc_out_enable  = debug_select_i && shift_dr_i && (shift_cnt <  7'd72) ;
968 
assign  crc_out_shift   = debug_select_i && shift_dr_i && (shift_cnt >= 7'd72) ;
969 
assign  crc_in_clear    = capture_dr_i ;
970 
assign  crc_in_enable   = debug_select_i && shift_dr_i ;
971 
assign  crc_in_shift    = 1'b0 ;
972 
debug_if_crc i_debug_if_crc_out
973 
(
974 
    .clk_i          (   tck_pad_i       ), // TAP clock
975 
    .rst_i          (   trst_neg_pad_i  ), // TAP reset
976 
    .clear_i        (   crc_out_clear   ), // clear CRC register
977 
    .enable_i       (   crc_out_enable  ), // enable CRC calculation
978 
    .shift_i        (   crc_out_shift   ), // shift CRC register
979 
    .data_i         (   shift_reg[0]    ), // serial DATA input
980 
    .crc_msb_o      (   crc_out_msb     ), // serial CRC output
981 
    .crc_ok_o       (                   )  // CRC status
982 
) ;
983 
debug_if_crc i_debug_if_crc_in
984 
(
985 
    .clk_i          (   tck_pad_i       ), // TAP clock
986 
    .rst_i          (   trst_neg_pad_i  ), // TAP reset
987 
    .clear_i        (   crc_in_clear    ), // clear CRC register
988 
    .enable_i       (   crc_in_enable   ), // enable CRC calculation
989 
    .shift_i        (   crc_in_shift    ), // shift CRC register
990 
    .data_i         (   tdi_i           ), // serial DATA input
991 
    .crc_msb_o      (                   ), // serial CRC output
992 
    .crc_ok_o       (   crc_in_ok       )  // CRC status
993 
) ;
994 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
995 
    begin
996 
        if (trst_neg_pad_i)
997 
            crc_in_ok_reg <= 1'b1 ;
998 
        else if (!debug_select_i)
999 
            crc_in_ok_reg <= 1'b1 ;
1000 
        else
1001 
            crc_in_ok_reg <= crc_in_ok ;
1002 
    end
1003 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
1004 
    begin
1005 
        if (trst_neg_pad_i)
1006 
            cur_state <= 3'h0 ;
1007 
        else if (!debug_select_i)
1008 
            cur_state <= 3'h0 ;
1009 
        else
1010 
            cur_state <= nxt_state ;
1011 
    end
1012 
always @(cur_state or synced_cmd or synced_stat or
1013 
         update_dr_i or latch_reg_valid or latch_cancel_valid)
1014 
    begin
1015 
        case (cur_state)
1016 
        3'h4 :
1017 
            begin
1018 
                if (synced_cmd) begin
1019 
                    nxt_state = 3'h1 ;
1020 
                    sync_cmd  = 1'b0 ;
1021 
                end
1022 
                else begin
1023 
                    nxt_state = 3'h4 ;
1024 
                    sync_cmd  = 1'b1 ;
1025 
                end
1026 
                sync_stat = 1'b0 ;
1027 
            end
1028 
        3'h1 :
1029 
            begin
1030 
                if (!synced_cmd) begin
1031 
                    nxt_state = 3'h2 ;
1032 
                    sync_stat = 1'b1 ;
1033 
                end
1034 
                else begin
1035 
                    nxt_state = 3'h1 ;
1036 
                    sync_stat = 1'b0 ;
1037 
                end
1038 
                sync_cmd  = 1'b0 ;
1039 
            end
1040 
        3'h2 :
1041 
            begin
1042 
                if (synced_stat) begin
1043 
                    nxt_state = 3'h3 ;
1044 
                    sync_cmd  = 1'b0 ;
1045 
                    sync_stat = 1'b0 ;
1046 
                end
1047 
                else if (update_dr_i && latch_cancel_valid) begin
1048 
                    nxt_state = 3'h4 ;
1049 
                    sync_cmd  = 1'b1 ;
1050 
                    sync_stat = 1'b0 ;
1051 
                end
1052 
                else begin
1053 
                    nxt_state = 3'h2 ;
1054 
                    sync_cmd  = 1'b0 ;
1055 
                    sync_stat = 1'b1 ;
1056 
                end
1057 
            end
1058 
        3'h3 :
1059 
            begin
1060 
                if (!synced_stat) begin
1061 
                    nxt_state = 3'h0 ;
1062 
                    sync_cmd  = 1'b0 ;
1063 
                end
1064 
                else if (update_dr_i && latch_cancel_valid) begin
1065 
                    nxt_state = 3'h4 ;
1066 
                    sync_cmd  = 1'b1 ;
1067 
                end
1068 
                else begin
1069 
                    nxt_state = 3'h3 ;
1070 
                    sync_cmd  = 1'b0 ;
1071 
                end
1072 
                sync_stat = 1'b0 ;
1073 
            end
1074 
        default : // 3'h0
1075 
            begin
1076 
                if (update_dr_i && (latch_reg_valid || latch_cancel_valid)) begin
1077 
                    nxt_state = 3'h4 ;
1078 
                    sync_cmd  = 1'b1 ;
1079 
                end
1080 
                else begin
1081 
                    nxt_state = 3'h0 ;
1082 
                    sync_cmd  = 1'b0 ;
1083 
                end
1084 
                sync_stat = 1'b0 ;
1085 
            end
1086 
        endcase
1087 
    end
1088 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
1089 
    begin
1090 
        if (trst_neg_pad_i)
1091 
            tap_reset <= 1'b1 ;
1092 
        else if (!debug_select_i)
1093 
            tap_reset <= 1'b1 ;
1094 
        else
1095 
            tap_reset <= 1'b0 ;
1096 
    end
1097 
assign  mod_tap_reset       = tap_reset ;
1098 
assign  mod_clear    [15:0] = ~cs_module[15:0] ;
1099 
assign  mod_sync_cmd [15:0] = {16{sync_cmd}}  & cs_module[15:0] ;
1100 
assign  mod_sync_stat[15:0] = {16{sync_stat}} & cs_module[15:0] ;
1101 
assign  synced_cmd          = |mod_synced_cmd [15:0] ;
1102 
assign  synced_stat         = |mod_synced_stat[15:0] ;
1103 
always @(cs_modnum or mod_read_data)
1104 
    begin
1105 
        case (cs_modnum[3:0])
1106 
        4'd15 : read_data = mod_read_data[32] ;
1107 
        4'd14 : read_data = mod_read_data[32] ;
1108 
        4'd13 : read_data = mod_read_data[32] ;
1109 
        4'd12 : read_data = mod_read_data[32] ;
1110 
        4'd11 : read_data = mod_read_data[32] ;
1111 
        4'd10 : read_data = mod_read_data[32] ;
1112 
        4'd09  : read_data = mod_read_data[32]  ;
1113 
        4'd08  : read_data = mod_read_data[32]  ;
1114 
        4'd07  : read_data = mod_read_data[32]  ;
1115 
        4'd06  : read_data = mod_read_data[32]  ;
1116 
        4'd05  : read_data = mod_read_data[32]  ;
1117 
        4'd04  : read_data = mod_read_data[32]  ;
1118 
        4'd03  : read_data = mod_read_data[32]  ;
1119 
        4'd02  : read_data = mod_read_data[32]  ;
1120 
        4'd01  : read_data = mod_read_data[32]  ;
1121 
        4'd00  : read_data = mod_read_data[32]  ;
1122 
        default                 : read_data = 32'hxxxx_xxxx ;
1123 
        endcase
1124 
    end
1125 
assign  bus_ack = |mod_bus_ack[15:0] ;
1126 
assign  bus_rty = |mod_bus_rty[15:0] ;
1127 
assign  bus_err = |mod_bus_err[15:0] ;
1128 
debug_if_bus_module i0_debug_if_bus_module
1129 
(
1130 
    .tck_pad_i          (   tck_pad_i                                       ),
1131 
    .trst_neg_pad_i     (   trst_neg_pad_i                                  ),
1132 
    .mod_tap_reset_i    (   mod_tap_reset                                   ),
1133 
    .mod_clear_i        (   mod_clear      [4'd00]         ),
1134 
    .mod_sync_cmd_i     (   mod_sync_cmd   [4'd00]         ),
1135 
    .mod_sync_stat_i    (   mod_sync_stat  [4'd00]         ),
1136 
    .mod_synced_cmd_o   (   mod_synced_cmd [4'd00]         ),
1137 
    .mod_synced_stat_o  (   mod_synced_stat[4'd00]         ),
1138 
    .mod_command_i      (   command        [ 3:0]                           ),
1139 
    .mod_byte_sel_i     (   byte_sel       [ 3:0]                           ),
1140 
    .mod_address_i      (   address        [31:0]                           ),
1141 
    .mod_write_data_i   (   write_data     [31:0]                           ),
1142 
    .mod_read_data_o    (   mod_read_data  [32]   ),
1143 
    .mod_bus_ack_o      (   mod_bus_ack    [4'd00]         ),
1144 
    .mod_bus_rty_o      (   mod_bus_rty    [4'd00]         ),
1145 
    .mod_bus_err_o      (   mod_bus_err    [4'd00]         ),
1146 
    .wb_clk_i           (   mod_wb_clk_i   [4'd00]         ),
1147 
    .wb_rst_i           (   mod_wb_rst_i   [4'd00]         ),
1148 
    .wb_cyc_o           (   mod_wb_cyc_o   [4'd00]         ),
1149 
    .wb_stb_o           (   mod_wb_stb_o   [4'd00]         ),
1150 
    .wb_we_o            (   mod_wb_we_o    [4'd00]         ),
1151 
    .wb_sel_o           (   mod_wb_sel_o   [4]   ),
1152 
    .wb_adr_o           (   mod_wb_adr_o   [32]   ),
1153 
    .wb_dat_o           (   mod_wb_dat_o   [32]   ),
1154 
    .wb_dat_i           (   mod_wb_dat_i   [32]   ),
1155 
    .wb_ack_i           (   mod_wb_ack_i   [4'd00]         ),
1156 
    .wb_rty_i           (   mod_wb_rty_i   [4'd00]         ),
1157 
    .wb_err_i           (   mod_wb_err_i   [4'd00]         ),
1158 
    .cpu_bp_i           (   mod_cpu_bp_i   [4'd00]         ),
1159 
    .cpu_stall_o        (   mod_cpu_stall_o[4'd00]         ),
1160 
    .cpu_rst_o          (   mod_cpu_rst_o  [4'd00]         )
1161 
) ;
1162 
debug_if_bus_module i1_debug_if_bus_module
1163 
(
1164 
    .tck_pad_i          (   tck_pad_i                                       ),
1165 
    .trst_neg_pad_i     (   trst_neg_pad_i                                  ),
1166 
    .mod_tap_reset_i    (   mod_tap_reset                                   ),
1167 
    .mod_clear_i        (   mod_clear      [4'd01]         ),
1168 
    .mod_sync_cmd_i     (   mod_sync_cmd   [4'd01]         ),
1169 
    .mod_sync_stat_i    (   mod_sync_stat  [4'd01]         ),
1170 
    .mod_synced_cmd_o   (   mod_synced_cmd [4'd01]         ),
1171 
    .mod_synced_stat_o  (   mod_synced_stat[4'd01]         ),
1172 
    .mod_command_i      (   command        [ 3:0]                           ),
1173 
    .mod_byte_sel_i     (   byte_sel       [ 3:0]                           ),
1174 
    .mod_address_i      (   address        [31:0]                           ),
1175 
    .mod_write_data_i   (   write_data     [31:0]                           ),
1176 
    .mod_read_data_o    (   mod_read_data  [32]   ),
1177 
    .mod_bus_ack_o      (   mod_bus_ack    [4'd01]         ),
1178 
    .mod_bus_rty_o      (   mod_bus_rty    [4'd01]         ),
1179 
    .mod_bus_err_o      (   mod_bus_err    [4'd01]         ),
1180 
    .wb_clk_i           (   mod_wb_clk_i   [4'd01]         ),
1181 
    .wb_rst_i           (   mod_wb_rst_i   [4'd01]         ),
1182 
    .wb_cyc_o           (   mod_wb_cyc_o   [4'd01]         ),
1183 
    .wb_stb_o           (   mod_wb_stb_o   [4'd01]         ),
1184 
    .wb_we_o            (   mod_wb_we_o    [4'd01]         ),
1185 
    .wb_sel_o           (   mod_wb_sel_o   [4]   ),
1186 
    .wb_adr_o           (   mod_wb_adr_o   [32]   ),
1187 
    .wb_dat_o           (   mod_wb_dat_o   [32]   ),
1188 
    .wb_dat_i           (   mod_wb_dat_i   [32]   ),
1189 
    .wb_ack_i           (   mod_wb_ack_i   [4'd01]         ),
1190 
    .wb_rty_i           (   mod_wb_rty_i   [4'd01]         ),
1191 
    .wb_err_i           (   mod_wb_err_i   [4'd01]         ),
1192 
    .cpu_bp_i           (   mod_cpu_bp_i   [4'd01]         ),
1193 
    .cpu_stall_o        (   mod_cpu_stall_o[4'd01]         ),
1194 
    .cpu_rst_o          (   mod_cpu_rst_o  [4'd01]         )
1195 
) ;
1196 
    assign  mod_synced_cmd [4'd02]         =  1'b0 ;
1197 
    assign  mod_synced_stat[4'd02]         =  1'b0 ;
1198 
    assign  mod_read_data  [32]   = 32'h0 ;
1199 
    assign  mod_bus_ack    [4'd02]         =  1'b0 ;
1200 
    assign  mod_bus_rty    [4'd02]         =  1'b0 ;
1201 
    assign  mod_bus_err    [4'd02]         =  1'b0 ;
1202 
    assign  mod_synced_cmd [4'd03]         =  1'b0 ;
1203 
    assign  mod_synced_stat[4'd03]         =  1'b0 ;
1204 
    assign  mod_read_data  [32]   = 32'h0 ;
1205 
    assign  mod_bus_ack    [4'd03]         =  1'b0 ;
1206 
    assign  mod_bus_rty    [4'd03]         =  1'b0 ;
1207 
    assign  mod_bus_err    [4'd03]         =  1'b0 ;
1208 
    assign  mod_synced_cmd [4'd04]         =  1'b0 ;
1209 
    assign  mod_synced_stat[4'd04]         =  1'b0 ;
1210 
    assign  mod_read_data  [32]   = 32'h0 ;
1211 
    assign  mod_bus_ack    [4'd04]         =  1'b0 ;
1212 
    assign  mod_bus_rty    [4'd04]         =  1'b0 ;
1213 
    assign  mod_bus_err    [4'd04]         =  1'b0 ;
1214 
    assign  mod_synced_cmd [4'd05]         =  1'b0 ;
1215 
    assign  mod_synced_stat[4'd05]         =  1'b0 ;
1216 
    assign  mod_read_data  [32]   = 32'h0 ;
1217 
    assign  mod_bus_ack    [4'd05]         =  1'b0 ;
1218 
    assign  mod_bus_rty    [4'd05]         =  1'b0 ;
1219 
    assign  mod_bus_err    [4'd05]         =  1'b0 ;
1220 
    assign  mod_synced_cmd [4'd06]         =  1'b0 ;
1221 
    assign  mod_synced_stat[4'd06]         =  1'b0 ;
1222 
    assign  mod_read_data  [32]   = 32'h0 ;
1223 
    assign  mod_bus_ack    [4'd06]         =  1'b0 ;
1224 
    assign  mod_bus_rty    [4'd06]         =  1'b0 ;
1225 
    assign  mod_bus_err    [4'd06]         =  1'b0 ;
1226 
    assign  mod_synced_cmd [4'd07]         =  1'b0 ;
1227 
    assign  mod_synced_stat[4'd07]         =  1'b0 ;
1228 
    assign  mod_read_data  [32]   = 32'h0 ;
1229 
    assign  mod_bus_ack    [4'd07]         =  1'b0 ;
1230 
    assign  mod_bus_rty    [4'd07]         =  1'b0 ;
1231 
    assign  mod_bus_err    [4'd07]         =  1'b0 ;
1232 
    assign  mod_synced_cmd [4'd08]         =  1'b0 ;
1233 
    assign  mod_synced_stat[4'd08]         =  1'b0 ;
1234 
    assign  mod_read_data  [32]   = 32'h0 ;
1235 
    assign  mod_bus_ack    [4'd08]         =  1'b0 ;
1236 
    assign  mod_bus_rty    [4'd08]         =  1'b0 ;
1237 
    assign  mod_bus_err    [4'd08]         =  1'b0 ;
1238 
    assign  mod_synced_cmd [4'd09]         =  1'b0 ;
1239 
    assign  mod_synced_stat[4'd09]         =  1'b0 ;
1240 
    assign  mod_read_data  [32]   = 32'h0 ;
1241 
    assign  mod_bus_ack    [4'd09]         =  1'b0 ;
1242 
    assign  mod_bus_rty    [4'd09]         =  1'b0 ;
1243 
    assign  mod_bus_err    [4'd09]         =  1'b0 ;
1244 
    assign  mod_synced_cmd [4'd10]        =  1'b0 ;
1245 
    assign  mod_synced_stat[4'd10]        =  1'b0 ;
1246 
    assign  mod_read_data  [32]  = 32'h0 ;
1247 
    assign  mod_bus_ack    [4'd10]        =  1'b0 ;
1248 
    assign  mod_bus_rty    [4'd10]        =  1'b0 ;
1249 
    assign  mod_bus_err    [4'd10]        =  1'b0 ;
1250 
    assign  mod_synced_cmd [4'd11]        =  1'b0 ;
1251 
    assign  mod_synced_stat[4'd11]        =  1'b0 ;
1252 
    assign  mod_read_data  [32]  = 32'h0 ;
1253 
    assign  mod_bus_ack    [4'd11]        =  1'b0 ;
1254 
    assign  mod_bus_rty    [4'd11]        =  1'b0 ;
1255 
    assign  mod_bus_err    [4'd11]        =  1'b0 ;
1256 
    assign  mod_synced_cmd [4'd12]        =  1'b0 ;
1257 
    assign  mod_synced_stat[4'd12]        =  1'b0 ;
1258 
    assign  mod_read_data  [32]  = 32'h0 ;
1259 
    assign  mod_bus_ack    [4'd12]        =  1'b0 ;
1260 
    assign  mod_bus_rty    [4'd12]        =  1'b0 ;
1261 
    assign  mod_bus_err    [4'd12]        =  1'b0 ;
1262 
    assign  mod_synced_cmd [4'd13]        =  1'b0 ;
1263 
    assign  mod_synced_stat[4'd13]        =  1'b0 ;
1264 
    assign  mod_read_data  [32]  = 32'h0 ;
1265 
    assign  mod_bus_ack    [4'd13]        =  1'b0 ;
1266 
    assign  mod_bus_rty    [4'd13]        =  1'b0 ;
1267 
    assign  mod_bus_err    [4'd13]        =  1'b0 ;
1268 
    assign  mod_synced_cmd [4'd14]        =  1'b0 ;
1269 
    assign  mod_synced_stat[4'd14]        =  1'b0 ;
1270 
    assign  mod_read_data  [32]  = 32'h0 ;
1271 
    assign  mod_bus_ack    [4'd14]        =  1'b0 ;
1272 
    assign  mod_bus_rty    [4'd14]        =  1'b0 ;
1273 
    assign  mod_bus_err    [4'd14]        =  1'b0 ;
1274 
    assign  mod_synced_cmd [4'd15]        =  1'b0 ;
1275 
    assign  mod_synced_stat[4'd15]        =  1'b0 ;
1276 
    assign  mod_read_data  [32]  = 32'h0 ;
1277 
    assign  mod_bus_ack    [4'd15]        =  1'b0 ;
1278 
    assign  mod_bus_rty    [4'd15]        =  1'b0 ;
1279 
    assign  mod_bus_err    [4'd15]        =  1'b0 ;
1280 
endmodule

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