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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [tap/] [tap.v] - Blame information for rev 42

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`include "tap_defines.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// TAP controller 
// -------------- 
// Fully JTAG compliant (IEEE Std 1149.1-2001) 
// Includes mandatory BYPASS register and optional ID register 
// Support for external mandatory BOUNDARY SCAN register 
// Support for external optional MEMORY BIST and DEBUG registers 
 
module tap
(
    // JTAG I/O pads
    tms_pad_i               , // JTAG Test Mode Select pad                    
    tck_pad_i               , // JTAG Test ClocK pad                          
    tck_neg_pad_i           , // JTAG Test ClocK negated pad                          
    trst_neg_pad_i          , // JTAG Test ReSeT negated pad                          
    tdi_pad_i               , // JTAG Test Data Input pad                     
    tdo_pad_o               , // JTAG Test Data Output pad                    
    tdo_padoe_o             , // output enable for JTAG Test Data Output pad 
    // TAP states
    capture_dr_o            ,
    shift_dr_o              ,
    pause_dr_o              ,
    update_dr_o             ,
    run_test_idle_o         ,
    test_logic_reset_o      ,
    // external TAP registers select signals 
    extest_select_o         ,
    sample_preload_select_o ,
    debug_select_o          ,
    mbist_select_o          ,
    // TDO signal for external TAP resgisters 
    tdo_o                   ,
    // TDI signals from external TAP resgisters 
    bscan_tdi_i             , // from boundary scan register 
    debug_tdi_i             , // from debug register (module)
    mbist_tdi_i               // from memory bist register 
) ;
 
 
// JTAG I/O pads
input           tms_pad_i               ; // JTAG Test Mode Select pad
input           tck_pad_i               ; // JTAG Test ClocK pad
input           tck_neg_pad_i           ; // JTAG Test ClocK negated pad
input           trst_neg_pad_i          ; // JTAG Test ReSeT negated pad
input           tdi_pad_i               ; // JTAG Test Data Input pad
output          tdo_pad_o               ; // JTAG Test Data Output pad
output          tdo_padoe_o             ; // output enable for JTAG Test Data Output pad 
// TAP states
output          capture_dr_o            ;
output          shift_dr_o              ;
output          pause_dr_o              ;
output          update_dr_o             ;
output          run_test_idle_o         ;
output          test_logic_reset_o      ;
// external TAP registers select signals 
output          extest_select_o         ;
output          sample_preload_select_o ;
output          debug_select_o          ;
output          mbist_select_o          ;
// TDO signal for external TAP resgisters 
output          tdo_o                   ;
// TDI signals from external TAP resgisters 
input           bscan_tdi_i             ; // from boundary scan register 
input           debug_tdi_i             ; // from debug register (module)
input           mbist_tdi_i             ; // from memory bist register  
 
 
reg             tdo_pad_o               ;
reg             tdo_padoe_o             ;
 
 
 
// internal signals 
reg             test_logic_reset        ;
reg             run_test_idle           ;
reg             select_dr_scan          ;
reg             capture_dr              ;
reg             shift_dr                ;
reg             exit1_dr                ;
reg             pause_dr                ;
reg             exit2_dr                ;
reg             update_dr               ;
reg             select_ir_scan          ;
reg             capture_ir              ;
reg             shift_ir                ;
reg             exit1_ir                ;
reg             pause_ir                ;
reg             exit2_ir                ;
reg             update_ir               ;
 
reg     [ 3: 0] jtag_inst_reg           ;
reg     [ 3: 0] latched_jtag_inst_reg   ;
reg     [31: 0] jtag_id_reg             ;
reg             jtag_bypass_reg         ;
 
reg             extest_select           ;
reg             sample_preload_select   ;
reg             id_reg_select           ;
reg             mbist_select            ;
reg             debug_select            ;
reg             bypass_reg_select       ;
 
reg             tms_q1                  ;
reg             tms_q2                  ;
reg             tms_q3                  ;
reg             tms_q4                  ;
wire            tms_reset               ;
 
 
 
//=============================================================================
//
// TMS Reset control logic 
//      5 consecutive logic '1' on TMS input causes reset 
//      
//=============================================================================
 
// registering TMS 
always @(posedge tck_pad_i)
    begin
        tms_q1 <= tms_pad_i ;
        tms_q2 <= tms_q1    ;
        tms_q3 <= tms_q2    ;
        tms_q4 <= tms_q3    ;
    end
 
// TMS reset 
assign  tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i ;
 
 
//=============================================================================
//
// TAP State Machine 
// 
//=============================================================================
 
// test_logic_reset state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            test_logic_reset <= 1'b1 ;
        else if (tms_reset)
            test_logic_reset <= 1'b1 ;
        else begin
            if (tms_pad_i & (test_logic_reset | select_ir_scan))
                test_logic_reset <= 1'b1 ;
            else
                test_logic_reset <= 1'b0 ;
        end
    end
 
// run_test_idle state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            run_test_idle <= 1'b0 ;
        else if (tms_reset)
            run_test_idle <= 1'b0 ;
        else begin
            if (~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
                run_test_idle <= 1'b1 ;
            else
                run_test_idle <= 1'b0 ;
        end
    end
 
// select_dr_scan state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            select_dr_scan <= 1'b0 ;
        else if (tms_reset)
            select_dr_scan <= 1'b0 ;
        else begin
            if (tms_pad_i & (run_test_idle | update_dr | update_ir))
                select_dr_scan <= 1'b1 ;
            else
                select_dr_scan <= 1'b0 ;
        end
    end
 
// capture_dr state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            capture_dr <= 1'b0 ;
        else if (tms_reset)
            capture_dr <= 1'b0 ;
        else begin
            if (~tms_pad_i & select_dr_scan)
                capture_dr <= 1'b1 ;
            else
                capture_dr <= 1'b0 ;
        end
    end
 
// shift_dr state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            shift_dr <= 1'b0 ;
        else if (tms_reset)
            shift_dr <= 1'b0 ;
        else begin
            if (~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
                shift_dr <= 1'b1 ;
            else
                shift_dr <= 1'b0 ;
        end
    end
 
// exit1_dr state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            exit1_dr <= 1'b0 ;
        else if (tms_reset)
            exit1_dr <= 1'b0 ;
        else begin
            if (tms_pad_i & (capture_dr | shift_dr))
                exit1_dr <= 1'b1 ;
            else
                exit1_dr <= 1'b0 ;
        end
    end
 
// pause_dr state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            pause_dr <= 1'b0 ;
        else if (tms_reset)
            pause_dr <= 1'b0 ;
        else begin
            if (~tms_pad_i & (exit1_dr | pause_dr))
                pause_dr <= 1'b1 ;
            else
                pause_dr <= 1'b0 ;
        end
    end
 
// exit2_dr state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            exit2_dr <= 1'b0 ;
        else if (tms_reset)
            exit2_dr <= 1'b0 ;
        else begin
            if (tms_pad_i & pause_dr)
                exit2_dr <= 1'b1 ;
            else
                exit2_dr <= 1'b0 ;
        end
    end
 
// update_dr state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            update_dr <= 1'b0 ;
        else if (tms_reset)
            update_dr <= 1'b0 ;
        else begin
            if (tms_pad_i & (exit1_dr | exit2_dr))
                update_dr <= 1'b1 ;
            else
                update_dr <= 1'b0 ;
        end
    end
 
// select_ir_scan state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            select_ir_scan <= 1'b0 ;
        else if (tms_reset)
            select_ir_scan <= 1'b0 ;
        else begin
            if (tms_pad_i & select_dr_scan)
                select_ir_scan <= 1'b1 ;
            else
                select_ir_scan <= 1'b0 ;
        end
    end
 
// capture_ir state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            capture_ir <= 1'b0 ;
        else if (tms_reset)
            capture_ir <= 1'b0 ;
        else begin
            if (~tms_pad_i & select_ir_scan)
                capture_ir <= 1'b1 ;
            else
                capture_ir <= 1'b0 ;
        end
    end
 
// shift_ir state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            shift_ir <= 1'b0 ;
        else if (tms_reset)
            shift_ir <= 1'b0 ;
        else begin
            if (~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
                shift_ir <= 1'b1 ;
            else
                shift_ir <= 1'b0 ;
        end
    end
 
// exit1_ir state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            exit1_ir <= 1'b0 ;
        else if (tms_reset)
            exit1_ir <= 1'b0 ;
        else begin
            if (tms_pad_i & (capture_ir | shift_ir))
                exit1_ir <= 1'b1 ;
            else
                exit1_ir <= 1'b0 ;
        end
    end
 
// pause_ir state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            pause_ir <= 1'b0 ;
        else if (tms_reset)
            pause_ir <= 1'b0 ;
        else begin
            if (~tms_pad_i & (exit1_ir | pause_ir))
                pause_ir <= 1'b1 ;
            else
                pause_ir <= 1'b0 ;
        end
    end
 
// exit2_ir state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            exit2_ir <= 1'b0 ;
        else if (tms_reset)
            exit2_ir <= 1'b0 ;
        else begin
            if (tms_pad_i & pause_ir)
                exit2_ir <= 1'b1 ;
            else
                exit2_ir <= 1'b0 ;
        end
    end
 
// update_ir state
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            update_ir <= 1'b0 ;
        else if (tms_reset)
            update_ir <= 1'b0 ;
        else begin
            if (tms_pad_i & (exit1_ir | exit2_ir))
                update_ir <= 1'b1 ;
            else
                update_ir <= 1'b0 ;
        end
    end
 
 
//=============================================================================
//
// JTAG Instruction Register (jtag_inst_reg) 
//      
//=============================================================================
 
// jtag_inst_reg
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            jtag_inst_reg <= 4'b0 ;
        else if (capture_ir)
            jtag_inst_reg <= 4'b0101 ; // This value is fixed for easier fault detection
        else if (shift_ir)
            jtag_inst_reg <= {tdi_pad_i, jtag_inst_reg[3:1]} ;
    end
 
// latched_jtag_inst_reg 
always @(posedge tck_neg_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            latched_jtag_inst_reg <= `TAP_IDCODE ;   // IDCODE selected after reset
        else if (test_logic_reset)
            latched_jtag_inst_reg <= `TAP_IDCODE ;   // IDCODE selected 
        else if (update_ir)
            latched_jtag_inst_reg <= jtag_inst_reg ;
    end
 
 
//=============================================================================
//
// JTAG ID Register (jtag_id_reg) 
//      
//=============================================================================
 
always @(posedge tck_pad_i)
    begin
        if (id_reg_select & shift_dr)
            jtag_id_reg <= {tdi_pad_i, jtag_id_reg[31:1]} ;
        else
            jtag_id_reg <= `TAP_IDCODE_VALUE ;
    end
 
 
//=============================================================================
//
// JTAG Bypass Register (jtag_bypass_reg) 
//      
//=============================================================================
 
always @(posedge tck_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            jtag_bypass_reg <= 1'b0 ;
        else if (capture_dr)
            jtag_bypass_reg <= 1'b0 ;
        else if (shift_dr)
            jtag_bypass_reg <= tdi_pad_i ;
    end
 
 
//=============================================================================
//
// TAP register selection  
//      
//=============================================================================
 
always @(latched_jtag_inst_reg)
    begin
        extest_select           = 1'b0 ;
        sample_preload_select   = 1'b0 ;
        id_reg_select           = 1'b0 ;
        mbist_select            = 1'b0 ;
        debug_select            = 1'b0 ;
        bypass_reg_select       = 1'b0 ;
 
        case (latched_jtag_inst_reg)
            `TAP_EXTEST         : extest_select         = 1'b1 ; // External test
            `TAP_SAMPLE_PRELOAD : sample_preload_select = 1'b1 ; // Sample preload
            `TAP_IDCODE         : id_reg_select         = 1'b1 ; // ID Code
            `TAP_MBIST          : mbist_select          = 1'b1 ; // Mbist test
            `TAP_DEBUG          : debug_select          = 1'b1 ; // Debug
            `TAP_BYPASS         : bypass_reg_select     = 1'b1 ; // BYPASS
            default             : bypass_reg_select     = 1'b1 ; // BYPASS
        endcase
    end
 
 
//=============================================================================
//
// Multiplexing JTAG TDO 
//      JTAG outputs have to be registered on falling edge of TCK 
//      
//=============================================================================
 
// JTAG Test Data Output 
always @(posedge tck_neg_pad_i or posedge trst_neg_pad_i)
    begin
        if (trst_neg_pad_i)
            tdo_pad_o <= 1'b1 ;
        else begin
            if (shift_ir)
                tdo_pad_o <= jtag_inst_reg[0] ;
            else begin
                case (latched_jtag_inst_reg)
                    `TAP_IDCODE         : tdo_pad_o <= jtag_id_reg      ;
                    `TAP_DEBUG          : tdo_pad_o <= debug_tdi_i      ;
                    `TAP_SAMPLE_PRELOAD : tdo_pad_o <= bscan_tdi_i      ;
                    `TAP_EXTEST         : tdo_pad_o <= bscan_tdi_i      ;
                    `TAP_MBIST          : tdo_pad_o <= mbist_tdi_i      ;
                    default             : tdo_pad_o <= jtag_bypass_reg  ;
                endcase
            end
        end
    end
 
// output enable for JTAG Test Data Output 
always @(posedge tck_neg_pad_i)
    begin
        tdo_padoe_o <= shift_ir | shift_dr ;
    end
 
 
//=============================================================================
//
// Output assignments for external TAP registers 
//      External registers need to know when they are selected and in which 
//      specific state TAP controller is when operating with Data Register. 
//      
//=============================================================================
 
// TAP data register state assignments 
assign  capture_dr_o        = capture_dr        ;
assign  shift_dr_o          = shift_dr          ;
assign  pause_dr_o          = pause_dr          ;
assign  update_dr_o         = update_dr         ;
assign  run_test_idle_o     = run_test_idle     ;
assign  test_logic_reset_o  = test_logic_reset  ;
 
// external TAP register select assignments 
assign  extest_select_o         = extest_select         ;
assign  sample_preload_select_o = sample_preload_select ;
assign  mbist_select_o          = mbist_select          ;
assign  debug_select_o          = debug_select          ;
 
// TDO for external TAP register assignment 
assign  tdo_o = tdi_pad_i ;
 
 
 
endmodule

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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [tap/] [tap.v] - Blame information for rev 42

Line No.	Rev	Author	Line
1	18	unneback	`include "tap_defines.v"
2
3			`// synopsys translate_off`
4			`include "timescale.v"
5			`// synopsys translate_on`
6
7			`// TAP controller`
8			`// --------------`
9			`// Fully JTAG compliant (IEEE Std 1149.1-2001)`
10			`// Includes mandatory BYPASS register and optional ID register`
11			`// Support for external mandatory BOUNDARY SCAN register`
12			`// Support for external optional MEMORY BIST and DEBUG registers`
13
14			`module tap`
15			`(`
16			`// JTAG I/O pads`
17			`tms_pad_i , // JTAG Test Mode Select pad`
18			`tck_pad_i , // JTAG Test ClocK pad`
19			`tck_neg_pad_i , // JTAG Test ClocK negated pad`
20			`trst_neg_pad_i , // JTAG Test ReSeT negated pad`
21			`tdi_pad_i , // JTAG Test Data Input pad`
22			`tdo_pad_o , // JTAG Test Data Output pad`
23			`tdo_padoe_o , // output enable for JTAG Test Data Output pad`
24			`// TAP states`
25			`capture_dr_o ,`
26			`shift_dr_o ,`
27			`pause_dr_o ,`
28			`update_dr_o ,`
29			`run_test_idle_o ,`
30			`test_logic_reset_o ,`
31			`// external TAP registers select signals`
32			`extest_select_o ,`
33			`sample_preload_select_o ,`
34			`debug_select_o ,`
35			`mbist_select_o ,`
36			`// TDO signal for external TAP resgisters`
37			`tdo_o ,`
38			`// TDI signals from external TAP resgisters`
39			`bscan_tdi_i , // from boundary scan register`
40			`debug_tdi_i , // from debug register (module)`
41			`mbist_tdi_i // from memory bist register`
42			`) ;`
43
44
45			`// JTAG I/O pads`
46			`input tms_pad_i ; // JTAG Test Mode Select pad`
47			`input tck_pad_i ; // JTAG Test ClocK pad`
48			`input tck_neg_pad_i ; // JTAG Test ClocK negated pad`
49			`input trst_neg_pad_i ; // JTAG Test ReSeT negated pad`
50			`input tdi_pad_i ; // JTAG Test Data Input pad`
51			`output tdo_pad_o ; // JTAG Test Data Output pad`
52			`output tdo_padoe_o ; // output enable for JTAG Test Data Output pad`
53			`// TAP states`
54			`output capture_dr_o ;`
55			`output shift_dr_o ;`
56			`output pause_dr_o ;`
57			`output update_dr_o ;`
58			`output run_test_idle_o ;`
59			`output test_logic_reset_o ;`
60			`// external TAP registers select signals`
61			`output extest_select_o ;`
62			`output sample_preload_select_o ;`
63			`output debug_select_o ;`
64			`output mbist_select_o ;`
65			`// TDO signal for external TAP resgisters`
66			`output tdo_o ;`
67			`// TDI signals from external TAP resgisters`
68			`input bscan_tdi_i ; // from boundary scan register`
69			`input debug_tdi_i ; // from debug register (module)`
70			`input mbist_tdi_i ; // from memory bist register`
71
72
73			`reg tdo_pad_o ;`
74			`reg tdo_padoe_o ;`
75
76
77
78			`// internal signals`
79			`reg test_logic_reset ;`
80			`reg run_test_idle ;`
81			`reg select_dr_scan ;`
82			`reg capture_dr ;`
83			`reg shift_dr ;`
84			`reg exit1_dr ;`
85			`reg pause_dr ;`
86			`reg exit2_dr ;`
87			`reg update_dr ;`
88			`reg select_ir_scan ;`
89			`reg capture_ir ;`
90			`reg shift_ir ;`
91			`reg exit1_ir ;`
92			`reg pause_ir ;`
93			`reg exit2_ir ;`
94			`reg update_ir ;`
95
96			`reg [ 3: 0] jtag_inst_reg ;`
97			`reg [ 3: 0] latched_jtag_inst_reg ;`
98			`reg [31: 0] jtag_id_reg ;`
99			`reg jtag_bypass_reg ;`
100
101			`reg extest_select ;`
102			`reg sample_preload_select ;`
103			`reg id_reg_select ;`
104			`reg mbist_select ;`
105			`reg debug_select ;`
106			`reg bypass_reg_select ;`
107
108			`reg tms_q1 ;`
109			`reg tms_q2 ;`
110			`reg tms_q3 ;`
111			`reg tms_q4 ;`
112			`wire tms_reset ;`
113
114
115
116			`//=============================================================================`
117			`//`
118			`// TMS Reset control logic`
119			`// 5 consecutive logic '1' on TMS input causes reset`
120			`//`
121			`//=============================================================================`
122
123			`// registering TMS`
124			`always @(posedge tck_pad_i)`
125			`begin`
126			`tms_q1 <= tms_pad_i ;`
127			`tms_q2 <= tms_q1 ;`
128			`tms_q3 <= tms_q2 ;`
129			`tms_q4 <= tms_q3 ;`
130			`end`
131
132			`// TMS reset`
133			`assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i ;`
134
135
136			`//=============================================================================`
137			`//`
138			`// TAP State Machine`
139			`//`
140			`//=============================================================================`
141
142			`// test_logic_reset state`
143			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
144			`begin`
145			`if (trst_neg_pad_i)`
146			`test_logic_reset <= 1'b1 ;`
147			`else if (tms_reset)`
148			`test_logic_reset <= 1'b1 ;`
149			`else begin`
150			`if (tms_pad_i & (test_logic_reset \| select_ir_scan))`
151			`test_logic_reset <= 1'b1 ;`
152			`else`
153			`test_logic_reset <= 1'b0 ;`
154			`end`
155			`end`
156
157			`// run_test_idle state`
158			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
159			`begin`
160			`if (trst_neg_pad_i)`
161			`run_test_idle <= 1'b0 ;`
162			`else if (tms_reset)`
163			`run_test_idle <= 1'b0 ;`
164			`else begin`
165			`if (~tms_pad_i & (test_logic_reset \| run_test_idle \| update_dr \| update_ir))`
166			`run_test_idle <= 1'b1 ;`
167			`else`
168			`run_test_idle <= 1'b0 ;`
169			`end`
170			`end`
171
172			`// select_dr_scan state`
173			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
174			`begin`
175			`if (trst_neg_pad_i)`
176			`select_dr_scan <= 1'b0 ;`
177			`else if (tms_reset)`
178			`select_dr_scan <= 1'b0 ;`
179			`else begin`
180			`if (tms_pad_i & (run_test_idle \| update_dr \| update_ir))`
181			`select_dr_scan <= 1'b1 ;`
182			`else`
183			`select_dr_scan <= 1'b0 ;`
184			`end`
185			`end`
186
187			`// capture_dr state`
188			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
189			`begin`
190			`if (trst_neg_pad_i)`
191			`capture_dr <= 1'b0 ;`
192			`else if (tms_reset)`
193			`capture_dr <= 1'b0 ;`
194			`else begin`
195			`if (~tms_pad_i & select_dr_scan)`
196			`capture_dr <= 1'b1 ;`
197			`else`
198			`capture_dr <= 1'b0 ;`
199			`end`
200			`end`
201
202			`// shift_dr state`
203			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
204			`begin`
205			`if (trst_neg_pad_i)`
206			`shift_dr <= 1'b0 ;`
207			`else if (tms_reset)`
208			`shift_dr <= 1'b0 ;`
209			`else begin`
210			`if (~tms_pad_i & (capture_dr \| shift_dr \| exit2_dr))`
211			`shift_dr <= 1'b1 ;`
212			`else`
213			`shift_dr <= 1'b0 ;`
214			`end`
215			`end`
216
217			`// exit1_dr state`
218			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
219			`begin`
220			`if (trst_neg_pad_i)`
221			`exit1_dr <= 1'b0 ;`
222			`else if (tms_reset)`
223			`exit1_dr <= 1'b0 ;`
224			`else begin`
225			`if (tms_pad_i & (capture_dr \| shift_dr))`
226			`exit1_dr <= 1'b1 ;`
227			`else`
228			`exit1_dr <= 1'b0 ;`
229			`end`
230			`end`
231
232			`// pause_dr state`
233			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
234			`begin`
235			`if (trst_neg_pad_i)`
236			`pause_dr <= 1'b0 ;`
237			`else if (tms_reset)`
238			`pause_dr <= 1'b0 ;`
239			`else begin`
240			`if (~tms_pad_i & (exit1_dr \| pause_dr))`
241			`pause_dr <= 1'b1 ;`
242			`else`
243			`pause_dr <= 1'b0 ;`
244			`end`
245			`end`
246
247			`// exit2_dr state`
248			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
249			`begin`
250			`if (trst_neg_pad_i)`
251			`exit2_dr <= 1'b0 ;`
252			`else if (tms_reset)`
253			`exit2_dr <= 1'b0 ;`
254			`else begin`
255			`if (tms_pad_i & pause_dr)`
256			`exit2_dr <= 1'b1 ;`
257			`else`
258			`exit2_dr <= 1'b0 ;`
259			`end`
260			`end`
261
262			`// update_dr state`
263			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
264			`begin`
265			`if (trst_neg_pad_i)`
266			`update_dr <= 1'b0 ;`
267			`else if (tms_reset)`
268			`update_dr <= 1'b0 ;`
269			`else begin`
270			`if (tms_pad_i & (exit1_dr \| exit2_dr))`
271			`update_dr <= 1'b1 ;`
272			`else`
273			`update_dr <= 1'b0 ;`
274			`end`
275			`end`
276
277			`// select_ir_scan state`
278			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
279			`begin`
280			`if (trst_neg_pad_i)`
281			`select_ir_scan <= 1'b0 ;`
282			`else if (tms_reset)`
283			`select_ir_scan <= 1'b0 ;`
284			`else begin`
285			`if (tms_pad_i & select_dr_scan)`
286			`select_ir_scan <= 1'b1 ;`
287			`else`
288			`select_ir_scan <= 1'b0 ;`
289			`end`
290			`end`
291
292			`// capture_ir state`
293			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
294			`begin`
295			`if (trst_neg_pad_i)`
296			`capture_ir <= 1'b0 ;`
297			`else if (tms_reset)`
298			`capture_ir <= 1'b0 ;`
299			`else begin`
300			`if (~tms_pad_i & select_ir_scan)`
301			`capture_ir <= 1'b1 ;`
302			`else`
303			`capture_ir <= 1'b0 ;`
304			`end`
305			`end`
306
307			`// shift_ir state`
308			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
309			`begin`
310			`if (trst_neg_pad_i)`
311			`shift_ir <= 1'b0 ;`
312			`else if (tms_reset)`
313			`shift_ir <= 1'b0 ;`
314			`else begin`
315			`if (~tms_pad_i & (capture_ir \| shift_ir \| exit2_ir))`
316			`shift_ir <= 1'b1 ;`
317			`else`
318			`shift_ir <= 1'b0 ;`
319			`end`
320			`end`
321
322			`// exit1_ir state`
323			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
324			`begin`
325			`if (trst_neg_pad_i)`
326			`exit1_ir <= 1'b0 ;`
327			`else if (tms_reset)`
328			`exit1_ir <= 1'b0 ;`
329			`else begin`
330			`if (tms_pad_i & (capture_ir \| shift_ir))`
331			`exit1_ir <= 1'b1 ;`
332			`else`
333			`exit1_ir <= 1'b0 ;`
334			`end`
335			`end`
336
337			`// pause_ir state`
338			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
339			`begin`
340			`if (trst_neg_pad_i)`
341			`pause_ir <= 1'b0 ;`
342			`else if (tms_reset)`
343			`pause_ir <= 1'b0 ;`
344			`else begin`
345			`if (~tms_pad_i & (exit1_ir \| pause_ir))`
346			`pause_ir <= 1'b1 ;`
347			`else`
348			`pause_ir <= 1'b0 ;`
349			`end`
350			`end`
351
352			`// exit2_ir state`
353			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
354			`begin`
355			`if (trst_neg_pad_i)`
356			`exit2_ir <= 1'b0 ;`
357			`else if (tms_reset)`
358			`exit2_ir <= 1'b0 ;`
359			`else begin`
360			`if (tms_pad_i & pause_ir)`
361			`exit2_ir <= 1'b1 ;`
362			`else`
363			`exit2_ir <= 1'b0 ;`
364			`end`
365			`end`
366
367			`// update_ir state`
368			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
369			`begin`
370			`if (trst_neg_pad_i)`
371			`update_ir <= 1'b0 ;`
372			`else if (tms_reset)`
373			`update_ir <= 1'b0 ;`
374			`else begin`
375			`if (tms_pad_i & (exit1_ir \| exit2_ir))`
376			`update_ir <= 1'b1 ;`
377			`else`
378			`update_ir <= 1'b0 ;`
379			`end`
380			`end`
381
382
383			`//=============================================================================`
384			`//`
385			`// JTAG Instruction Register (jtag_inst_reg)`
386			`//`
387			`//=============================================================================`
388
389			`// jtag_inst_reg`
390			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
391			`begin`
392			`if (trst_neg_pad_i)`
393			`jtag_inst_reg <= 4'b0 ;`
394			`else if (capture_ir)`
395			`jtag_inst_reg <= 4'b0101 ; // This value is fixed for easier fault detection`
396			`else if (shift_ir)`
397			`jtag_inst_reg <= {tdi_pad_i, jtag_inst_reg[3:1]} ;`
398			`end`
399
400			`// latched_jtag_inst_reg`
401			`always @(posedge tck_neg_pad_i or posedge trst_neg_pad_i)`
402			`begin`
403			`if (trst_neg_pad_i)`
404			latched_jtag_inst_reg <= `TAP_IDCODE ; // IDCODE selected after reset
405			`else if (test_logic_reset)`
406			latched_jtag_inst_reg <= `TAP_IDCODE ; // IDCODE selected
407			`else if (update_ir)`
408			`latched_jtag_inst_reg <= jtag_inst_reg ;`
409			`end`
410
411
412			`//=============================================================================`
413			`//`
414			`// JTAG ID Register (jtag_id_reg)`
415			`//`
416			`//=============================================================================`
417
418			`always @(posedge tck_pad_i)`
419			`begin`
420			`if (id_reg_select & shift_dr)`
421			`jtag_id_reg <= {tdi_pad_i, jtag_id_reg[31:1]} ;`
422			`else`
423			jtag_id_reg <= `TAP_IDCODE_VALUE ;
424			`end`
425
426
427			`//=============================================================================`
428			`//`
429			`// JTAG Bypass Register (jtag_bypass_reg)`
430			`//`
431			`//=============================================================================`
432
433			`always @(posedge tck_pad_i or posedge trst_neg_pad_i)`
434			`begin`
435			`if (trst_neg_pad_i)`
436			`jtag_bypass_reg <= 1'b0 ;`
437			`else if (capture_dr)`
438			`jtag_bypass_reg <= 1'b0 ;`
439			`else if (shift_dr)`
440			`jtag_bypass_reg <= tdi_pad_i ;`
441			`end`
442
443
444			`//=============================================================================`
445			`//`
446			`// TAP register selection`
447			`//`
448			`//=============================================================================`
449
450			`always @(latched_jtag_inst_reg)`
451			`begin`
452			`extest_select = 1'b0 ;`
453			`sample_preload_select = 1'b0 ;`
454			`id_reg_select = 1'b0 ;`
455			`mbist_select = 1'b0 ;`
456			`debug_select = 1'b0 ;`
457			`bypass_reg_select = 1'b0 ;`
458
459			`case (latched_jtag_inst_reg)`
460			`TAP_EXTEST : extest_select = 1'b1 ; // External test
461			`TAP_SAMPLE_PRELOAD : sample_preload_select = 1'b1 ; // Sample preload
462			`TAP_IDCODE : id_reg_select = 1'b1 ; // ID Code
463			`TAP_MBIST : mbist_select = 1'b1 ; // Mbist test
464			`TAP_DEBUG : debug_select = 1'b1 ; // Debug
465			`TAP_BYPASS : bypass_reg_select = 1'b1 ; // BYPASS
466			`default : bypass_reg_select = 1'b1 ; // BYPASS`
467			`endcase`
468			`end`
469
470
471			`//=============================================================================`
472			`//`
473			`// Multiplexing JTAG TDO`
474			`// JTAG outputs have to be registered on falling edge of TCK`
475			`//`
476			`//=============================================================================`
477
478			`// JTAG Test Data Output`
479			`always @(posedge tck_neg_pad_i or posedge trst_neg_pad_i)`
480			`begin`
481			`if (trst_neg_pad_i)`
482			`tdo_pad_o <= 1'b1 ;`
483			`else begin`
484			`if (shift_ir)`
485			`tdo_pad_o <= jtag_inst_reg[0] ;`
486			`else begin`
487			`case (latched_jtag_inst_reg)`
488			`TAP_IDCODE : tdo_pad_o <= jtag_id_reg ;
489			`TAP_DEBUG : tdo_pad_o <= debug_tdi_i ;
490			`TAP_SAMPLE_PRELOAD : tdo_pad_o <= bscan_tdi_i ;
491			`TAP_EXTEST : tdo_pad_o <= bscan_tdi_i ;
492			`TAP_MBIST : tdo_pad_o <= mbist_tdi_i ;
493			`default : tdo_pad_o <= jtag_bypass_reg ;`
494			`endcase`
495			`end`
496			`end`
497			`end`
498
499			`// output enable for JTAG Test Data Output`
500			`always @(posedge tck_neg_pad_i)`
501			`begin`
502			`tdo_padoe_o <= shift_ir \| shift_dr ;`
503			`end`
504
505
506			`//=============================================================================`
507			`//`
508			`// Output assignments for external TAP registers`
509			`// External registers need to know when they are selected and in which`
510			`// specific state TAP controller is when operating with Data Register.`
511			`//`
512			`//=============================================================================`
513
514			`// TAP data register state assignments`
515			`assign capture_dr_o = capture_dr ;`
516			`assign shift_dr_o = shift_dr ;`
517			`assign pause_dr_o = pause_dr ;`
518			`assign update_dr_o = update_dr ;`
519			`assign run_test_idle_o = run_test_idle ;`
520			`assign test_logic_reset_o = test_logic_reset ;`
521
522			`// external TAP register select assignments`
523			`assign extest_select_o = extest_select ;`
524			`assign sample_preload_select_o = sample_preload_select ;`
525			`assign mbist_select_o = mbist_select ;`
526			`assign debug_select_o = debug_select ;`
527
528			`// TDO for external TAP register assignment`
529			`assign tdo_o = tdi_pad_i ;`
530
531
532
533			`endmodule`