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// ============================================================================
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// __
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Thor SuperScaler
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// ALU
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//
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// ============================================================================
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//
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`include "Thor_defines.v"
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module Thor_alu(corenum, rst, clk, alu_ld, alu_op, alu_fn, alu_argA, alu_argB, alu_argC, alu_argI, alu_pc, insnsz, o, alu_done, alu_divByZero);
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parameter DBW=64;
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parameter BIG=1;
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parameter FEATURES = 0;
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input [63:0] corenum;
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input rst;
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input clk;
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input alu_ld;
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input [7:0] alu_op;
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input [5:0] alu_fn;
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input [DBW-1:0] alu_argA;
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input [DBW-1:0] alu_argB;
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input [DBW-1:0] alu_argC;
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input [DBW-1:0] alu_argI;
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input [DBW-1:0] alu_pc;
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input [3:0] insnsz;
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output reg [DBW-1:0] o;
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output reg alu_done;
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output alu_divByZero;
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wire signed [DBW-1:0] alu_argAs = alu_argA;
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wire signed [DBW-1:0] alu_argBs = alu_argB;
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wire signed [DBW-1:0] alu_argIs = alu_argI;
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wire [DBW-1:0] andi_res = alu_argA & alu_argI;
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wire [127:0] alu_prod;
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wire [63:0] alu_divq;
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wire [63:0] alu_rem;
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wire [7:0] bcdao,bcdso;
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wire [15:0] bcdmo;
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wire [DBW-1:0] bf_out;
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wire [DBW-1:0] shfto;
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wire alu_mult_done,alu_div_done;
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wire [DBW-1:0] p_out;
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integer n;
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Thor_multiplier #(DBW) umult1
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(
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.rst(rst),
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.clk(clk),
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.ld(alu_ld && ((alu_op==`RR && (alu_fn==`MUL || alu_fn==`MULU)) || alu_op==`MULI || alu_op==`MULUI)),
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.sgn((alu_op==`RR && alu_op==`MUL) || alu_op==`MULI),
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.isMuli(alu_op==`MULI || alu_op==`MULUI),
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.a(alu_argA),
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.b(alu_argB),
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.imm(alu_argI),
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.o(alu_prod),
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.done(alu_mult_done)
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);
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Thor_divider #(DBW) udiv1
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(
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.rst(rst),
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.clk(clk),
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.ld(alu_ld && ((alu_op==`RR && (alu_fn==`DIV || alu_fn==`DIVU)) || alu_op==`DIVI || alu_op==`DIVUI)),
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.sgn((alu_op==`RR && alu_fn==`DIV) || alu_op==`DIVI),
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.isDivi(alu_op==`DIVI || alu_op==`DIVUI),
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.a(alu_argA),
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.b(alu_argB),
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.imm(alu_argI),
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.qo(alu_divq),
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.ro(alu_rem),
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.dvByZr(alu_divByZero),
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.done(alu_div_done)
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);
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Thor_shifter #(DBW) ushft0
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(
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.func(alu_fn),
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.a(alu_argA),
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.b(alu_argB),
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.o(shfto)
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);
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BCDAdd ubcda
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(
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.ci(1'b0),
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.a(alu_argA[7:0]),
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.b(alu_argB[7:0]),
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.o(bcdao),
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.c()
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);
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BCDSub ubcds
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(
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.ci(1'b0),
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.a(alu_argA[7:0]),
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.b(alu_argB[7:0]),
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.o(bcdso),
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.c()
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);
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BCDMul2 ubcdm
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(
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.a(alu_argA),
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.b(alu_argB),
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.o(bcdmo)
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);
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Thor_bitfield #(DBW) ubf1
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(
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.op(alu_fn),
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.a(alu_argA),
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.b(alu_argB),
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.m(alu_argI[11:0]),
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.o(bf_out),
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.masko()
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);
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Thor_P #(DBW) upr1
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(
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.fn(alu_fn),
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.ra(alu_argI[5:0]),
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.rb(alu_argI[11:6]),
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.rt(alu_argI[17:12]),
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.pregs_i(alu_argA),
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.pregs_o(p_out)
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);
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wire [DBW-1:0] cntlzo;
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wire [DBW-1:0] cntloo;
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wire [DBW-1:0] cntpopo;
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generate
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begin : clzg
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if (DBW==64) begin
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cntlz64 u12 ( .i(alu_argA), .o(cntlzo) );
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cntlo64 u13 ( .i(alu_argA), .o(cntloo) );
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cntpop64 u14 ( .i(alu_argA), .o(cntpopo) );
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end
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else begin
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cntlz32 u12 ( .i(alu_argA), .o(cntlzo) );
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cntlo32 u13 ( .i(alu_argA), .o(cntloo) );
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cntpop32 u14 ( .i(alu_argA), .o(cntpopo) );
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end
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end
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endgenerate
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wire faz = alu_argA[DBW-2:0]==63'd0;
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wire fbz = alu_argB[DBW-2:0]==63'd0;
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wire feq = (faz & fbz) || (alu_argA==alu_argB); // special test for zero
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wire fgt1 = alu_argA[DBW-2:0] > alu_argB[DBW-2:0];
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wire flt1 = alu_argA[DBW-2:0] < alu_argB[DBW-2:0];
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wire flt = alu_argA[DBW] ^ alu_argB[DBW] ? alu_argA[DBW] & !(faz & fbz): alu_argA[DBW] ? fgt1 : flt1;
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wire nanA = DBW==32 ? alu_argA[30:23]==8'hFF && (alu_argA[22:0]!=23'd0) : alu_argA[62:52]==11'h7FF && (alu_argA[51:0]!=52'd0);
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wire nanB = DBW==32 ? alu_argB[30:23]==8'hFF && (alu_argB[22:0]!=23'd0) : alu_argB[62:52]==11'h7FF && (alu_argB[51:0]!=52'd0);
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wire fsaz = alu_argA[30:0]==31'd0;
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wire fsbz = alu_argB[30:0]==31'd0;
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wire fseq = (fsaz & fsbz) || (alu_argA[31:0]==alu_argB[31:0]); // special test for zero
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wire fsgt1 = alu_argA[30:0] > alu_argB[30:0];
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wire fslt1 = alu_argA[30:0] < alu_argB[30:0];
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wire fslt = alu_argA[31] ^ alu_argB[31] ? alu_argA[31] & !(fsaz & fsbz): alu_argA[31] ? fsgt1 : fslt1;
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wire snanA = alu_argA[30:23]==8'hFF && (alu_argA[22:0]!=23'd0);
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wire snanB = alu_argB[30:23]==8'hFF && (alu_argB[22:0]!=23'd0);
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always @*
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begin
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casex(alu_op)
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`LDI,`LDIS: o <= alu_argI;
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`RR:
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case(alu_fn)
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`ADD,`ADDU: o <= alu_argA + alu_argB;
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`SUB,`SUBU: o <= alu_argA - alu_argB;
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`_2ADDU: o <= {alu_argA[DBW-2:0],1'b0} + alu_argB;
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`_4ADDU: o <= {alu_argA[DBW-3:0],2'b0} + alu_argB;
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`_8ADDU: o <= {alu_argA[DBW-4:0],3'b0} + alu_argB;
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`_16ADDU: o <= {alu_argA[DBW-5:0],4'b0} + alu_argB;
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`MIN: o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
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`MAX: o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
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`MUL,`MULU: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`DIV,`DIVU: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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`MULI,`MULUI: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`DIVI,`DIVUI: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`_2ADDUI: o <= {alu_argA[DBW-2:0],1'b0} + alu_argI;
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`_4ADDUI: o <= {alu_argA[DBW-3:0],2'b0} + alu_argI;
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`_8ADDUI: o <= {alu_argA[DBW-4:0],3'b0} + alu_argI;
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`_16ADDUI: o <= {alu_argA[DBW-5:0],4'b0} + alu_argI;
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`R:
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case(alu_fn[3:0])
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`MOV: o <= alu_argA;
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`NEG: o <= -alu_argA;
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`NOT: o <= |alu_argA ? 64'd0 : 64'd1;
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`ABS: o <= BIG ? (alu_argA[DBW] ? -alu_argA : alu_argA) : 64'hDEADDEADDEADDEAD;
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`SGN: o <= BIG ? (alu_argA[DBW] ? 64'hFFFFFFFFFFFFFFFF : alu_argA==64'd0 ? 64'd0 : 64'd1) : 64'hDEADDEADDEADDEAD;
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`CNTLZ: o <= BIG ? cntlzo : 64'hDEADDEADDEADDEAD;
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`CNTLO: o <= BIG ? cntloo : 64'hDEADDEADDEADDEAD;
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`CNTPOP: o <= BIG ? cntpopo : 64'hDEADDEADDEADDEAD;
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`ZXB: o <= BIG ? {56'd0,alu_argA[7:0]} : 64'hDEADDEADDEADDEAD;
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`ZXC: o <= BIG ? {48'd0,alu_argA[15:0]} : 64'hDEADDEADDEADDEAD;
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`ZXH: o <= BIG ? {32'd0,alu_argA[31:0]} : 64'hDEADDEADDEADDEAD;
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`COM: o <= ~alu_argA;
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`SXB: o <= BIG ? {{56{alu_argA[7]}},alu_argA[7:0]} : 64'hDEADDEADDEADDEAD;
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`SXC: o <= BIG ? {{48{alu_argA[15]}},alu_argA[15:0]} : 64'hDEADDEADDEADDEAD;
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`SXH: o <= BIG ? {{32{alu_argA[31]}},alu_argA[31:0]} : 64'hDEADDEADDEADDEAD;
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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`R2:
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case(alu_fn)
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`CPUID:
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if (BIG)
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case(alu_argA[4:0])
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5'd0: o <= corenum;
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5'd2: o <= "Finitron";
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5'd3: o <= ""; // vendor ID
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5'd4: o <= "64BitSS"; // class
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5'd6: o <= "Thor"; // Name
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5'd8: o <= "M1"; // model
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5'd9: o <= "1234"; // serial num
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5'd10: o <= FEATURES;
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5'd11: o <= {32'd16384,32'd32768}; // Cache D,I
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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else o <= 64'hDEADDEADDEADDEAD;
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`REDOR: o <= BIG ? |alu_argA : 64'hDEADDEADDEADDEAD;
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`REDAND: o <= BIG ? &alu_argA : 64'hDEADDEADDEADDEAD;
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`PAR: o <= BIG ? ^alu_argA : 64'hDEADDEADDEADDEAD;
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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`P: o <= p_out;
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/*
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`DOUBLE:
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if (BIG) begin
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if (alu_fn[5:4]==2'b00)
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case (alu_fn)
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`FMOV: o <= alu_argA;
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`FNEG: o <= {~alu_argA[DBW-1],alu_argA[DBW-2:0]};
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`FABS: o <= {1'b0,alu_argA[DBW-2:0]};
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`FSIGN: if (DBW==64)
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o <= alu_argA[DBW-2:0]==0 ? {DBW{1'b0}} : {alu_argA[DBW-1],1'b0,{10{1'b1}},{52{1'b0}}};
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else
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o <= alu_argA[DBW-2:0]==0 ? {DBW{1'b0}} : {alu_argA[DBW-1],1'b0,{7{1'b1}},{23{1'b0}}};
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`FMAN: o <= alu_argA[(DBW==64?51:22):0];
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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else
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case (alu_fn)
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`FMOV: o <= alu_argA;
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`FSNEG: o <= {~alu_argA[31],alu_argA[30:0]};
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`FSABS: o <= {1'b0,alu_argA[30:0]};
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`FSSIGN: o <= alu_argA[30:0]==0 ? {DBW{1'b0}} : {alu_argA[31],1'b0,{7{1'b1}},{23{1'b0}}};
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`FSMAN: o <= alu_argA[22:0];
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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end
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else
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o <= 64'hDEADDEADDEADDEAD;
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*/
|
279 |
|
|
|
280 |
|
|
`ADDI,`ADDUI,`ADDUIS:
|
281 |
|
|
o <= alu_argA + alu_argI;
|
282 |
|
|
`SUBI,`SUBUI:
|
283 |
|
|
o <= alu_argA - alu_argI;
|
284 |
|
|
`ANDI: o <= alu_argA & alu_argI;
|
285 |
|
|
`ORI: o <= alu_argA | alu_argI;
|
286 |
|
|
`EORI: o <= alu_argA ^ alu_argI;
|
287 |
|
|
`LOGIC,`MLO:
|
288 |
|
|
case(alu_fn)
|
289 |
|
|
`AND: o <= alu_argA & alu_argB;
|
290 |
|
|
`ANDC: o <= alu_argA & ~alu_argB;
|
291 |
|
|
`OR: o <= alu_argA | alu_argB;
|
292 |
|
|
`ORC: o <= alu_argA | ~alu_argB;
|
293 |
|
|
`EOR: o <= alu_argA ^ alu_argB;
|
294 |
|
|
`NAND: o <= ~(alu_argA & alu_argB);
|
295 |
|
|
`NOR: o <= ~(alu_argA | alu_argB);
|
296 |
|
|
`ENOR: o <= ~(alu_argA ^ alu_argB);
|
297 |
|
|
default: o <= 64'd0;
|
298 |
|
|
endcase
|
299 |
|
|
`BITI:
|
300 |
|
|
begin
|
301 |
|
|
o[0] <= andi_res==64'd0;
|
302 |
|
|
o[1] <= andi_res[DBW-1];
|
303 |
|
|
o[2] <= andi_res[0];
|
304 |
|
|
o[3] <= 1'b0;
|
305 |
|
|
o[DBW-1:4] <= 60'd0;
|
306 |
|
|
end
|
307 |
|
|
`TST:
|
308 |
|
|
case(alu_fn)
|
309 |
|
|
6'd0: // TST - integer
|
310 |
|
|
begin
|
311 |
|
|
o[0] <= alu_argA == 64'd0;
|
312 |
|
|
o[1] <= alu_argA[DBW-1];
|
313 |
|
|
o[2] <= 1'b0;
|
314 |
|
|
o[3] <= 1'b0;
|
315 |
|
|
o[DBW-1:4] <= 60'd0;
|
316 |
|
|
end
|
317 |
|
|
`ifdef FLOATING_POINT
|
318 |
|
|
6'd1: // FSTST - float single
|
319 |
|
|
begin
|
320 |
|
|
o[0] <= alu_argA[30:0]==31'd0; // + or - zero
|
321 |
|
|
o[1] <= alu_argA[31]; // signed less than
|
322 |
|
|
o[2] <= alu_argA[31];
|
323 |
|
|
// unordered
|
324 |
|
|
o[3] <= alu_argA[30:23]==8'hFF && alu_argA[22:0]!=23'd0; // NaN
|
325 |
|
|
o[DBW-1:4] <= 60'd0;
|
326 |
|
|
end
|
327 |
|
|
6'd2: // FTST - float double
|
328 |
|
|
begin
|
329 |
|
|
o[0] <= alu_argA[DBW-2:0]==63'd0; // + or - zero
|
330 |
|
|
o[1] <= alu_argA[DBW-1]; // signed less than
|
331 |
|
|
o[2] <= alu_argA[DBW-1];
|
332 |
|
|
// unordered
|
333 |
|
|
if (DBW==64)
|
334 |
|
|
o[3] <= alu_argA[62:52]==11'h7FF && alu_argA[51:0]!=52'd0; // NaN
|
335 |
|
|
else
|
336 |
|
|
o[3] <= 1'b0;
|
337 |
|
|
o[DBW-1:4] <= 60'd0;
|
338 |
|
|
end
|
339 |
|
|
`endif
|
340 |
|
|
default: o <= 64'd0;
|
341 |
|
|
endcase
|
342 |
|
|
`CMP: begin
|
343 |
|
|
case(alu_fn)
|
344 |
|
|
2'd0: begin // ICMP
|
345 |
|
|
o[0] <= alu_argA == alu_argB;
|
346 |
|
|
o[1] <= alu_argAs < alu_argBs;
|
347 |
|
|
o[2] <= alu_argA < alu_argB;
|
348 |
|
|
o[3] <= 1'b0;
|
349 |
|
|
o[DBW-1:4] <= 60'd0;
|
350 |
|
|
end
|
351 |
|
|
`ifdef FLOATING_POINT
|
352 |
|
|
2'd1: begin // FSCMP
|
353 |
|
|
o[0] <= fseq;
|
354 |
|
|
o[1] <= fslt;
|
355 |
|
|
o[2] <= fslt1;
|
356 |
|
|
o[3] <= snanA | snanB;
|
357 |
|
|
o[DBW-1:4] <= 60'd0;
|
358 |
|
|
end
|
359 |
|
|
2'd2: begin // FCMP
|
360 |
|
|
o[0] <= feq;
|
361 |
|
|
o[1] <= flt;
|
362 |
|
|
o[2] <= flt1;
|
363 |
|
|
o[3] <= nanA | nanB;
|
364 |
|
|
o[DBW-1:4] <= 60'd0;
|
365 |
|
|
end
|
366 |
|
|
`endif
|
367 |
|
|
default: o <= 64'hDEADDEADDEADDEAD;
|
368 |
|
|
endcase
|
369 |
|
|
end
|
370 |
|
|
`CMPI: begin
|
371 |
|
|
o[0] <= alu_argA == alu_argI;
|
372 |
|
|
o[1] <= alu_argAs < alu_argIs;
|
373 |
|
|
o[2] <= alu_argA < alu_argI;
|
374 |
|
|
o[3] <= 1'b0;
|
375 |
|
|
o[DBW-1:4] <= 64'd0;
|
376 |
|
|
end
|
377 |
|
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`SB,`SC,`SH,`SW,`CAS,`LVB,`LVC,`LVH,`LVH,`STI,
|
378 |
|
|
`LWS,`SWS,`LEA,`RTS2,`STS,`STFND,`STCMP:
|
379 |
|
|
begin
|
380 |
|
|
o <= alu_argA + alu_argC + alu_argI;
|
381 |
|
|
end
|
382 |
|
|
`LBX,`LBUX,`SBX,
|
383 |
|
|
`LCX,`LCUX,`SCX,
|
384 |
|
|
`LHX,`LHUX,`SHX,
|
385 |
|
|
`LWX,`SWX:
|
386 |
|
|
case(alu_fn[1:0])
|
387 |
|
|
2'd0: o <= alu_argA + alu_argC + alu_argB;
|
388 |
|
|
2'd1: o <= alu_argA + alu_argC + {alu_argB,1'b0};
|
389 |
|
|
2'd2: o <= alu_argA + alu_argC + {alu_argB,2'b0};
|
390 |
|
|
2'd3: o <= alu_argA + alu_argC + {alu_argB,3'b0};
|
391 |
|
|
endcase
|
392 |
|
|
`ifdef STACKOPS
|
393 |
|
|
`PUSH,`PEA,`LINK: o <= alu_argA + alu_argC - 64'd8;
|
394 |
|
|
`UNLINK: o <= alu_argA + alu_argC + 64'd8;
|
395 |
|
|
`POP: o <= alu_argA + alu_argC;
|
396 |
|
|
`endif
|
397 |
|
|
`JSR,`JSRS,`JSRZ,`SYS: o <= alu_pc + insnsz;
|
398 |
|
|
`INT: o <= alu_pc;
|
399 |
|
|
`MFSPR,`MTSPR: begin
|
400 |
|
|
o <= alu_argA;
|
401 |
|
|
end
|
402 |
|
|
`MUX: begin
|
403 |
|
|
for (n = 0; n < DBW; n = n + 1)
|
404 |
|
|
o[n] <= alu_argA[n] ? alu_argB[n] : alu_argC[n];
|
405 |
|
|
end
|
406 |
|
|
`BCD:
|
407 |
|
|
if (BIG)
|
408 |
|
|
case(alu_fn)
|
409 |
|
|
`BCDADD: o <= bcdao;
|
410 |
|
|
`BCDSUB: o <= bcdso;
|
411 |
|
|
`BCDMUL: o <= bcdmo;
|
412 |
|
|
default: o <= 64'hDEADDEADDEADDEAD;
|
413 |
|
|
endcase
|
414 |
|
|
else
|
415 |
|
|
o <= 64'hDEADDEADDEADDEAD;
|
416 |
|
|
`SHIFT: o <= BIG ? shfto : 64'hDEADDEADDEADDEAD;
|
417 |
|
|
`ifdef BITFIELDOPS
|
418 |
|
|
`BITFIELD: o <= BIG ? bf_out : 64'hDEADDEADDEADDEAD;
|
419 |
|
|
`endif
|
420 |
|
|
`LOOP: o <= alu_argB > 0 ? alu_argB - 64'd1 : alu_argB;
|
421 |
|
|
default: o <= 64'hDEADDEADDEADDEAD;
|
422 |
|
|
endcase
|
423 |
|
|
end
|
424 |
|
|
|
425 |
|
|
// Generate done signal
|
426 |
|
|
always @*
|
427 |
|
|
case(alu_op)
|
428 |
|
|
`RR:
|
429 |
|
|
case(alu_fn)
|
430 |
|
|
`MUL,`MULU: alu_done <= alu_mult_done;
|
431 |
|
|
`DIV,`DIVU: alu_done <= alu_div_done;
|
432 |
|
|
default: alu_done <= `TRUE;
|
433 |
|
|
endcase
|
434 |
|
|
`MULI,`MULUI: alu_done <= alu_mult_done;
|
435 |
|
|
`DIVI,`DIVUI: alu_done <= alu_div_done;
|
436 |
|
|
default: alu_done <= `TRUE;
|
437 |
|
|
endcase
|
438 |
|
|
|
439 |
|
|
endmodule
|