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[/] [tiny_tate_bilinear_pairing/] [trunk/] [group_size_is_151_bits/] [testbench/] [test_tiny.v] - Blame information for rev 14

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`timescale 1ns / 1ps
`define P 20 // clock period 
 
module test_tiny;
 
        // Inputs
        reg clk;
        reg reset;
        reg sel;
        reg [5:0] addr;
        reg w;
        reg [197:0] data;
 
        // Outputs
        wire [197:0] out;
        wire done;
 
        // Instantiate the Unit Under Test (UUT)
        tiny uut (
                .clk(clk),
                .reset(reset),
                .sel(sel),
                .addr(addr),
                .w(w),
                .data(data),
                .out(out),
                .done(done)
        );
 
        initial begin
                // Initialize Inputs
                clk = 0;
                reset = 0;
                sel = 0;
                addr = 0;
                w = 0;
                data = 0;
 
                // Wait 100 ns for global reset to finish
                #100;
 
                // Add stimulus here
        reset = 1; // keep FSM silent
            // init x, y
            write(3, 194'h21181940120548aa020568aa65a5989609251595a89a44598);
            write(5, 194'h0a905590506a8a845592a09644a2095291422910a968a5048);
            write(6, 194'h21181940120548aa020568aa65a5989609251595a89a44598);
            write(7, 194'h0a905590506a8a845592a09644a2095291422910a968a5048);
            /* read back. uncomment me if error happens */
            /* read(3);
            $display("xp = %h", out);
            read(5);
            $display("yp = %h", out);
            read(6);
            $display("xq = %h", out);
            read(7);
            $display("yq = %h", out);*/
        reset = 0;
        sel = 0; w = 0;
        @(posedge done);
        @(negedge clk);
            read(3);
            check(194'h21181940120548aa020568aa65a5989609251595a89a44599);
            read(5);
            check(194'h0560aa60a0954548aa615069885106a16281162056945a084);
            read(6);
            check(194'h21181940120548aa020568aa65a5989609251595a89a44598);
            read(7);
            check(194'h0a905590506a8a845592a09644a2095291422910a968a5048);
            read(9);
            check(194'h09a49266428495042842965645266a2164a1268408a669866);
            read(10);
            check(194'h204446152452400968480544296829199a169a2562a908520);
            read(11);
            check(194'h1699142918666651a156954a80544689590a5094624610281);
            read(12);
            check(194'h2461998924145511611291626a4a295888569280285884661);
            read(13);
            check(194'h1040525045a404150a1881aa91a99156660a1658a090a1091);
            read(14);
            check(194'h2400a94249694808254880924a06494816081900811198925);
            $display("Good");
        $finish;
        end
 
    initial #100 forever #(`P/2) clk = ~clk;
 
    task write;
        input [6:0] adr;
        input [197:0] dat;
        begin
            sel = 1;
            w = 1;
            addr = adr;
            data = dat;
            #(`P);
        end
    endtask
 
    task read;
        input [6:0] adr;
        begin
            sel = 1;
            w = 0;
            addr = adr;
            #(`P);
        end
    endtask
 
    task check;
        input [197:0] wish;
        begin
            if (out !== wish)
                begin $display("Error!"); $finish; end
        end
    endtask
endmodule
 

Line No.	Rev	Author	Line
1	5	homer.hsin	`timescale 1ns / 1ps
2			`define P 20 // clock period
3
4			`module test_tiny;`
5
6			`// Inputs`
7			`reg clk;`
8			`reg reset;`
9			`reg sel;`
10			`reg [5:0] addr;`
11			`reg w;`
12			`reg [197:0] data;`
13
14			`// Outputs`
15			`wire [197:0] out;`
16			`wire done;`
17
18			`// Instantiate the Unit Under Test (UUT)`
19			`tiny uut (`
20			`.clk(clk),`
21			`.reset(reset),`
22			`.sel(sel),`
23			`.addr(addr),`
24			`.w(w),`
25			`.data(data),`
26			`.out(out),`
27			`.done(done)`
28			`);`
29
30			`initial begin`
31			`// Initialize Inputs`
32			`clk = 0;`
33			`reset = 0;`
34			`sel = 0;`
35			`addr = 0;`
36			`w = 0;`
37			`data = 0;`
38
39			`// Wait 100 ns for global reset to finish`
40			`#100;`
41
42			`// Add stimulus here`
43			`reset = 1; // keep FSM silent`
44			`// init x, y`
45	14	homer.hsin	`write(3, 194'h21181940120548aa020568aa65a5989609251595a89a44598);`
46			`write(5, 194'h0a905590506a8a845592a09644a2095291422910a968a5048);`
47			`write(6, 194'h21181940120548aa020568aa65a5989609251595a89a44598);`
48			`write(7, 194'h0a905590506a8a845592a09644a2095291422910a968a5048);`
49	5	homer.hsin	`/* read back. uncomment me if error happens */`
50			`/* read(3);`
51			`$display("xp = %h", out);`
52			`read(5);`
53			`$display("yp = %h", out);`
54			`read(6);`
55			`$display("xq = %h", out);`
56			`read(7);`
57			`$display("yq = %h", out);*/`
58			`reset = 0;`
59			`sel = 0; w = 0;`
60			`@(posedge done);`
61			`@(negedge clk);`
62			`read(3);`
63	14	homer.hsin	`check(194'h21181940120548aa020568aa65a5989609251595a89a44599);`
64	5	homer.hsin	`read(5);`
65	14	homer.hsin	`check(194'h0560aa60a0954548aa615069885106a16281162056945a084);`
66	5	homer.hsin	`read(6);`
67	14	homer.hsin	`check(194'h21181940120548aa020568aa65a5989609251595a89a44598);`
68	5	homer.hsin	`read(7);`
69	14	homer.hsin	`check(194'h0a905590506a8a845592a09644a2095291422910a968a5048);`
70	5	homer.hsin	`read(9);`
71	14	homer.hsin	`check(194'h09a49266428495042842965645266a2164a1268408a669866);`
72	5	homer.hsin	`read(10);`
73	14	homer.hsin	`check(194'h204446152452400968480544296829199a169a2562a908520);`
74	5	homer.hsin	`read(11);`
75	14	homer.hsin	`check(194'h1699142918666651a156954a80544689590a5094624610281);`
76	5	homer.hsin	`read(12);`
77	14	homer.hsin	`check(194'h2461998924145511611291626a4a295888569280285884661);`
78	5	homer.hsin	`read(13);`
79	14	homer.hsin	`check(194'h1040525045a404150a1881aa91a99156660a1658a090a1091);`
80	5	homer.hsin	`read(14);`
81	14	homer.hsin	`check(194'h2400a94249694808254880924a06494816081900811198925);`
82	5	homer.hsin	`$display("Good");`
83			`$finish;`
84			`end`
85
86			initial #100 forever #(`P/2) clk = ~clk;
87
88			`task write;`
89			`input [6:0] adr;`
90			`input [197:0] dat;`
91			`begin`
92			`sel = 1;`
93			`w = 1;`
94			`addr = adr;`
95			`data = dat;`
96			#(`P);
97			`end`
98			`endtask`
99
100			`task read;`
101			`input [6:0] adr;`
102			`begin`
103			`sel = 1;`
104			`w = 0;`
105			`addr = adr;`
106			#(`P);
107			`end`
108	7	homer.hsin	`endtask`
109	5	homer.hsin
110			`task check;`
111			`input [197:0] wish;`
112			`begin`
113			`if (out !== wish)`
114			`begin $display("Error!"); $finish; end`
115			`end`
116			`endtask`
117			`endmodule`
118

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[/] [tiny_tate_bilinear_pairing/] [trunk/] [group_size_is_151_bits/] [testbench/] [test_tiny.v] - Blame information for rev 14