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[/] [viterbi_decoder_axi4s/] [trunk/] [src/] [reorder.vhd] - Blame information for rev 5

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1 2 mfehrenz
--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--!
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--! @file
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--! @brief  Reorder twisted output due to windowing
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--! @author Markus Fehrenz
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--! @date   2011/05/12
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--!
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--! @details The windowing output is twisted.
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--!          The correct order is simply rebuilt by reversing
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--!          the output of each traceback unit.
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--!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library dec_viterbi;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_types.all;
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entity reorder is
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        port(
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                clk :   in std_logic;
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                rst :   in std_logic;
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                --
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                -- Traceback unit output, twisted order
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                --
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                s_axis_input_tvalid     : in  std_logic;
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                s_axis_input_tdata      : in  std_logic;
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                s_axis_input_tlast      : in  std_logic;
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                s_axis_input_last_tuser : in  std_logic;
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                s_axis_input_tready     : out std_logic;
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                --
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                -- Viterbi decoder output, original (input) order.
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                --
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                m_axis_output_tvalid     : out std_logic;
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                m_axis_output_tdata      : out std_logic;
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                m_axis_output_tlast      : out std_logic;
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                m_axis_output_last_tuser : out std_logic; -- Last bit of one traceback window
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                m_axis_output_tready     : in  std_logic
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        );
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end entity reorder;
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architecture rtl of reorder is
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        -- used to store one reversed output of an traceback unit
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        signal buffer_sreg              : unsigned(MAX_WINDOW_LENGTH - 1 downto 0);
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        signal buffer_cnt               : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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        signal buffer_end               : integer range ENCODER_MEMORY_DEPTH downto 0;
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        signal send_output, last_window : boolean;
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        signal s_axis_input_tready_int  : std_logic;
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begin
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        s_axis_input_tready     <= s_axis_input_tready_int;
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        s_axis_input_tready_int <= '1' when not(send_output) else
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                                   '0';
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        m_axis_output_tvalid     <= '1' when send_output and m_axis_output_tready= '1' else
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                                    '0';
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        m_axis_output_tdata      <= buffer_sreg(0);
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        m_axis_output_tlast      <= '1' when buffer_cnt = ENCODER_MEMORY_DEPTH  and last_window else
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                                    '0';
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        -- Reorder the global path given from an tracebackunit with the help of an shift register.
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        pr_reorder : process(clk) is
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        begin
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        if rising_edge(clk) then
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                if rst = '1' then
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                        buffer_sreg              <= (others => '0');
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                        buffer_cnt               <= (others => '0');
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                        send_output              <= false;
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                        last_window              <= false;
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                        buffer_end               <= 0;
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                        m_axis_output_last_tuser <= '0';
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                else
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                        -- store output of traceback unit
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                        if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
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                                if s_axis_input_tlast = '1' then
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                                        last_window <= true;
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                                        buffer_end <= ENCODER_MEMORY_DEPTH;
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                                end if;
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                                if s_axis_input_last_tuser = '1' then
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                                        send_output <= true;
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                                        buffer_sreg <= buffer_sreg(MAX_WINDOW_LENGTH - 2 downto 0) & s_axis_input_tdata;
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                                else
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                                        buffer_sreg <= buffer_sreg(MAX_WINDOW_LENGTH - 2 downto 0) & s_axis_input_tdata;
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                                        buffer_cnt  <= buffer_cnt + 1;
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                                end if;
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                        end if;
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                        -- send reordered data to the output
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                        if m_axis_output_tready = '1' and send_output then
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                                buffer_sreg <= '0' & buffer_sreg(MAX_WINDOW_LENGTH - 1 downto 1);
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                                -- Next transfer will be the last one of this window.
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                                if buffer_cnt = 1 then
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                                        m_axis_output_last_tuser <= '1';
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                                end if;
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                                -- This was the last data transfer. Tailbits are cut off
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                                if buffer_cnt = buffer_end then
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                                        send_output              <= false;
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                                        last_window              <= false;
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                                        buffer_end               <= 0;
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                                        buffer_cnt               <= (others => '0');
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                                        m_axis_output_last_tuser <= '0';
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                                else
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                                        buffer_cnt <= buffer_cnt - 1;
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                                end if;
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                        end if;
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                end if;
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        end if;
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        end process pr_reorder;
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end architecture rtl;

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