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# WB2AXIP: A Pipelind Wishbone B4 to AXI4 bridge
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Built out of necessity, [this core](rtl/wbm2axisp.v) is designed to provide
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a conversion from a [wishbone
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bus](http://zipcpu.com/zipcpu/2017/11/07/wb-formal.html) to an AXI bus.
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Primarily, the core is designed to connect a
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[wishbone bus](http://zipcpu.com/zipcpu/2017/11/07/wb-formal.html),
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either 32- or 128-bits wide, to a 128-bit wide AXI bus, which is the natural
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width of a DDR3 transaction (with 16-bit lanes).  Hence, if the
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Memory Interface Generator DDR3 controller is running at a 4:1 clock rate,
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memory clocks to AXI system clocks, then it should be possible to accomplish
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one transaction clock at a sustained or pipelined rate.  This
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[bus translator](rtl/wbm2axisp.v) is designed to be able to handle one
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transaction per clock (pipelined), although [(due to Xilinx's MIG design)
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the delay may be up to 27 clocks](http://opencores.org/project,wbddr3).  (Ouch!)
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# AXI to Wishbone conversion
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Since the project began, a full-fledged [AXI4 to Wishbone bridge](rtl/axim2wbsp.v) has been added to the project.
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This converter handles synchronizing the write channels, turning AXI read/write
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requests into pipeline wishbone requests, maintaining the AXI ID fields, etc.
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It ignores the AXI xSIZE, xLOCK, xCACHE, xPROT, and xQOS fields.  It supports
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xBURST types of FIXED (2'b00) and INCR (2'b01), but not WRAP (2'b10) or
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reserved (2'b11).  It does not (yet) support bridging between busses of
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different widths, so both the AXI and the WB bus must have the same width.
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AXI4 is a complicated protocol, however, especially when
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[compared to WB](http://zipcpu.com/zipcpu/2017/11/07/wb-formal.html).
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_Finally, whereas the [bridge](rtl/axim2wbsp.v) has been written, it has yet
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to be significantly tested or formally proven.  If you are interested in
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helping to test it, please contact me at (zipcpu (at) gmail.com).  Until
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that time, it must be said that the result is subject to change._
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# Formal Verification
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This particular version of the tools includes an initial attempt at
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formally proving that the core(s) work.
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Currently, the project contains formal specifications for
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[Avalon](bench/formal/fav_slave.v), [Wishbone](bench/formal/fwb_slave.v), and
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[AXI](bench/formal/faxi_slave.v) busses.  Components with working proofs
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include the [WB to AXI](rtl/wbm2axisp.v) bridge as well as the
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[WB arbiter](rtl/wbarbiter.v) needed for the [AXI to WB](rtl/axim2wbsp.v).
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I also have a working proof for an Avalon to WB bridge that isn't posted
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here.
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The [AXI4 to Wishbone bridge](rtl/axim2wbsp.v) remains a work in progress
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that isn't getting a lot of attention.
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# Commercial Applications
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Should you find the GPLv3 license insufficient for your needs, other licenses
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can be purchased from Gisselquist Technology, LLc.
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# Thanks
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I'd like to thank @wallento for his initial work on a
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[Wishbone to AXI converter](https://github.com/wallento/wb2axi), and his
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encouragement to improve upon it.  While this isn't a fork of his work, it
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takes its motivation from his work.

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