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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: axim2wbsp.v
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//
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// Project: Pipelined Wishbone to AXI converter
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//
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// Purpose: So ... this converter works in the other direction. This
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// converter takes AXI commands, and organizes them into pipelined
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// wishbone commands.
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//
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//
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// We'll treat AXI as two separate busses: one for writes, another for
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// reads, further, we'll insist that the two channels AXI uses for writes
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// combine into one channel for our purposes.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module axim2wbsp( i_clk, i_axi_reset_n,
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//
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o_axi_awready, // Slave is ready to accept
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i_axi_awid, i_axi_awaddr, i_axi_awlen, i_axi_awsize, i_axi_awburst,
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i_axi_awlock, i_axi_awcache, i_axi_awprot, i_axi_awqos, i_axi_awvalid,
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//
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o_axi_wready, i_axi_wdata, i_axi_wstrb, i_axi_wlast, i_axi_wvalid,
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//
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o_axi_bid, o_axi_bresp, o_axi_bvalid, i_axi_bready,
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//
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o_axi_arready, // Read address ready
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i_axi_arid, // Read ID
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i_axi_araddr, // Read address
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i_axi_arlen, // Read Burst Length
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i_axi_arsize, // Read Burst size
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i_axi_arburst, // Read Burst type
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i_axi_arlock, // Read lock type
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i_axi_arcache, // Read Cache type
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i_axi_arprot, // Read Protection type
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i_axi_arqos, // Read Protection type
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i_axi_arvalid, // Read address valid
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//
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o_axi_rid, // Response ID
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o_axi_rresp, // Read response
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o_axi_rvalid, // Read reponse valid
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o_axi_rdata, // Read data
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o_axi_rlast, // Read last
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i_axi_rready, // Read Response ready
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// Wishbone interface
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o_reset, o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
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//
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parameter C_AXI_ID_WIDTH = 6; // The AXI id width used for R&W
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// This is an int between 1-16
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parameter C_AXI_DATA_WIDTH = 32;// Width of the AXI R&W data
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parameter C_AXI_ADDR_WIDTH = 28; // AXI Address width
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localparam DW = C_AXI_DATA_WIDTH;
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localparam AW = (C_AXI_DATA_WIDTH== 8) ? (C_AXI_ADDR_WIDTH)
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:((C_AXI_DATA_WIDTH== 16) ? (C_AXI_ADDR_WIDTH-1)
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:((C_AXI_DATA_WIDTH== 32) ? (C_AXI_ADDR_WIDTH-2)
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:((C_AXI_DATA_WIDTH== 64) ? (C_AXI_ADDR_WIDTH-3)
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:((C_AXI_DATA_WIDTH==128) ? (C_AXI_ADDR_WIDTH-4)
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:(C_AXI_ADDR_WIDTH-5)))));
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//
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input wire i_clk; // System clock
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input wire i_axi_reset_n;
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// AXI write address channel signals
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output wire o_axi_awready; // Slave is ready to accept
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input wire [C_AXI_ID_WIDTH-1:0] i_axi_awid; // Write ID
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input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_awaddr; // Write address
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input wire [7:0] i_axi_awlen; // Write Burst Length
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input wire [2:0] i_axi_awsize; // Write Burst size
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input wire [1:0] i_axi_awburst; // Write Burst type
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input wire [0:0] i_axi_awlock; // Write lock type
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input wire [3:0] i_axi_awcache; // Write Cache type
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input wire [2:0] i_axi_awprot; // Write Protection type
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input wire [3:0] i_axi_awqos; // Write Quality of Svc
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input wire i_axi_awvalid; // Write address valid
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// AXI write data channel signals
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output wire o_axi_wready; // Write data ready
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input wire [C_AXI_DATA_WIDTH-1:0] i_axi_wdata; // Write data
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input wire [C_AXI_DATA_WIDTH/8-1:0] i_axi_wstrb; // Write strobes
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input wire i_axi_wlast; // Last write transaction
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input wire i_axi_wvalid; // Write valid
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// AXI write response channel signals
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_bid; // Response ID
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output wire [1:0] o_axi_bresp; // Write response
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output wire o_axi_bvalid; // Write reponse valid
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input wire i_axi_bready; // Response ready
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// AXI read address channel signals
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output wire o_axi_arready; // Read address ready
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input wire [C_AXI_ID_WIDTH-1:0] i_axi_arid; // Read ID
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input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_araddr; // Read address
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input wire [7:0] i_axi_arlen; // Read Burst Length
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input wire [2:0] i_axi_arsize; // Read Burst size
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input wire [1:0] i_axi_arburst; // Read Burst type
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input wire [0:0] i_axi_arlock; // Read lock type
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input wire [3:0] i_axi_arcache; // Read Cache type
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input wire [2:0] i_axi_arprot; // Read Protection type
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input wire [3:0] i_axi_arqos; // Read Protection type
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input wire i_axi_arvalid; // Read address valid
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// AXI read data channel signals
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid; // Response ID
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output wire [1:0] o_axi_rresp; // Read response
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output wire o_axi_rvalid; // Read reponse valid
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output wire [C_AXI_DATA_WIDTH-1:0] o_axi_rdata; // Read data
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output wire o_axi_rlast; // Read last
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input wire i_axi_rready; // Read Response ready
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// We'll share the clock and the reset
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output wire o_reset;
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output wire o_wb_cyc;
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output wire o_wb_stb;
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output wire o_wb_we;
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output wire [(AW-1):0] o_wb_addr;
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output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data;
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output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel;
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input wire i_wb_ack;
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input wire i_wb_stall;
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input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data;
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input wire i_wb_err;
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//
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//
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//
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wire [(AW-1):0] w_wb_addr, r_wb_addr;
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wire [(C_AXI_DATA_WIDTH-1):0] w_wb_data;
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wire [(C_AXI_DATA_WIDTH/8-1):0] w_wb_sel;
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wire r_wb_err, r_wb_cyc, r_wb_stb, r_wb_stall, r_wb_ack;
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wire w_wb_err, w_wb_cyc, w_wb_stb, w_wb_stall, w_wb_ack;
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// verilator lint_off UNUSED
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wire r_wb_we, w_wb_we;
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assign r_wb_we = 1'b0;
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assign w_wb_we = 1'b1;
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// verilator lint_on UNUSED
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aximwr2wbsp #(
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.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
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.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
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.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .AW(AW))
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axi_write_decoder(
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.i_axi_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
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//
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.o_axi_awready(o_axi_awready),
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.i_axi_awid( i_axi_awid),
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.i_axi_awaddr( i_axi_awaddr),
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.i_axi_awlen( i_axi_awlen),
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.i_axi_awsize( i_axi_awsize),
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.i_axi_awburst(i_axi_awburst),
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.i_axi_awlock( i_axi_awlock),
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.i_axi_awcache(i_axi_awcache),
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.i_axi_awprot( i_axi_awprot),
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.i_axi_awqos( i_axi_awqos),
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.i_axi_awvalid(i_axi_awvalid),
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//
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.o_axi_wready( o_axi_wready),
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.i_axi_wdata( i_axi_wdata),
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.i_axi_wstrb( i_axi_wstrb),
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.i_axi_wlast( i_axi_wlast),
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.i_axi_wvalid( i_axi_wvalid),
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//
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.o_axi_bid(o_axi_bid),
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.o_axi_bresp(o_axi_bresp),
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.o_axi_bvalid(o_axi_bvalid),
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.i_axi_bready(i_axi_bready),
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//
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.o_wb_cyc( w_wb_cyc),
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.o_wb_stb( w_wb_stb),
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.o_wb_addr( w_wb_addr),
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.o_wb_data( w_wb_data),
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.o_wb_sel( w_wb_sel),
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.i_wb_ack( w_wb_ack),
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.i_wb_stall(w_wb_stall),
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.i_wb_err( w_wb_err));
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assign w_wb_we = 1'b1;
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aximrd2wbsp #(
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.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
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.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
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.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .AW(AW))
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axi_read_decoder(
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.i_axi_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
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//
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.o_axi_arready(o_axi_arready),
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.i_axi_arid( i_axi_arid),
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.i_axi_araddr( i_axi_araddr),
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.i_axi_arlen( i_axi_arlen),
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.i_axi_arsize( i_axi_arsize),
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.i_axi_arburst(i_axi_arburst),
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.i_axi_arlock( i_axi_arlock),
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.i_axi_arcache(i_axi_arcache),
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.i_axi_arprot( i_axi_arprot),
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.i_axi_arqos( i_axi_arqos),
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.i_axi_arvalid(i_axi_arvalid),
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//
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.o_axi_rid( o_axi_rid),
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.o_axi_rresp( o_axi_rresp),
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.o_axi_rvalid(o_axi_rvalid),
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.o_axi_rdata( o_axi_rdata),
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.o_axi_rlast( o_axi_rlast),
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.i_axi_rready(i_axi_rready),
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//
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.o_wb_cyc( r_wb_cyc),
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.o_wb_stb( r_wb_stb),
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.o_wb_addr( r_wb_addr),
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.i_wb_ack( r_wb_ack),
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.i_wb_stall(r_wb_stall),
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.i_wb_data( i_wb_data),
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.i_wb_err( r_wb_err));
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wbarbiter #(
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`ifdef FORMAL
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.F_LGDEPTH(C_AXI_DATA_WIDTH),
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`endif
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.DW(C_AXI_DATA_WIDTH),
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.AW(AW))
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readorwrite(i_clk, !i_axi_reset_n,
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r_wb_cyc, r_wb_stb, 1'b0, r_wb_addr, w_wb_data, w_wb_sel,
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r_wb_ack, r_wb_stall, r_wb_err,
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w_wb_cyc, w_wb_stb, 1'b1, w_wb_addr, w_wb_data, w_wb_sel,
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w_wb_ack, w_wb_stall, w_wb_err,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_err);
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assign o_reset = (i_axi_reset_n == 1'b0);
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`ifdef FORMAL
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`ifdef AXIM2WBSP
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reg f_last_clk;
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initial f_last_clk = 0;
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always @($global_clock)
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begin
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assume(i_clk == f_last_clk);
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f_last_clk <= !f_last_clk;
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end
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`else
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`endif
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid = 1'b1;
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wire [(C_AXI_ID_WIDTH-1):0] f_axi_rd_outstanding,
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f_axi_wr_outstanding,
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f_axi_awr_outstanding;
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wire [((1<<C_AXI_ID_WIDTH)-1):0] f_axi_rd_id_outstanding,
|
| 286 |
|
|
f_axi_awr_id_outstanding,
|
| 287 |
|
|
f_axi_wr_id_outstanding;
|
| 288 |
|
|
wire [(C_AXI_ID_WIDTH-1):0] f_wb_nreqs,
|
| 289 |
|
|
f_wb_nacks, f_wb_outstanding;
|
| 290 |
|
|
wire [(C_AXI_ID_WIDTH-1):0] f_wb_wr_nreqs,
|
| 291 |
|
|
f_wb_wr_nacks, f_wb_wr_outstanding;
|
| 292 |
|
|
wire [(C_AXI_ID_WIDTH-1):0] f_wb_rd_nreqs,
|
| 293 |
|
|
f_wb_rd_nacks, f_wb_rd_outstanding;
|
| 294 |
|
|
|
| 295 |
|
|
fwb_slave #(.DW(DW), .AW(AW),
|
| 296 |
|
|
.F_MAX_STALL(0),
|
| 297 |
|
|
.F_MAX_ACK_DELAY(0),
|
| 298 |
|
|
.F_LGDEPTH(C_AXI_ID_WIDTH),
|
| 299 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 300 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 301 |
|
|
f_wb_wr(i_clk, !i_axi_reset_n,
|
| 302 |
|
|
w_wb_cyc, w_wb_stb, w_wb_we, w_wb_addr, w_wb_data,
|
| 303 |
|
|
w_wb_sel,
|
| 304 |
|
|
w_wb_ack, w_wb_stall, i_wb_data, w_wb_err,
|
| 305 |
|
|
f_wb_wr_nreqs, f_wb_wr_nacks, f_wb_wr_outstanding);
|
| 306 |
|
|
|
| 307 |
|
|
fwb_slave #(.DW(DW), .AW(AW),
|
| 308 |
|
|
.F_MAX_STALL(0),
|
| 309 |
|
|
.F_MAX_ACK_DELAY(0),
|
| 310 |
|
|
.F_LGDEPTH(C_AXI_ID_WIDTH),
|
| 311 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 312 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 313 |
|
|
f_wb_rd(i_clk, !i_axi_reset_n,
|
| 314 |
|
|
r_wb_cyc, r_wb_stb, r_wb_we, r_wb_addr, w_wb_data, w_wb_sel,
|
| 315 |
|
|
r_wb_ack, r_wb_stall, i_wb_data, r_wb_err,
|
| 316 |
|
|
f_wb_rd_nreqs, f_wb_rd_nacks, f_wb_rd_outstanding);
|
| 317 |
|
|
|
| 318 |
|
|
fwb_master #(.DW(DW), .AW(AW),
|
| 319 |
|
|
.F_MAX_STALL(3),
|
| 320 |
|
|
.F_MAX_ACK_DELAY(3),
|
| 321 |
|
|
.F_LGDEPTH(C_AXI_ID_WIDTH))
|
| 322 |
|
|
f_wb(i_clk, !i_axi_reset_n,
|
| 323 |
|
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
| 324 |
|
|
o_wb_sel,
|
| 325 |
|
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
|
| 326 |
|
|
f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
|
| 327 |
|
|
|
| 328 |
|
|
always @(*)
|
| 329 |
|
|
assume(i_axi_awlen < 8'h4);
|
| 330 |
|
|
|
| 331 |
|
|
always @(*)
|
| 332 |
|
|
assume(i_axi_arlen < 8'h4);
|
| 333 |
|
|
|
| 334 |
|
|
always @(*)
|
| 335 |
|
|
assume(i_axi_arvalid == 0);
|
| 336 |
|
|
|
| 337 |
|
|
faxi_slave #(
|
| 338 |
|
|
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
|
| 339 |
|
|
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
|
| 340 |
|
|
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
|
| 341 |
|
|
.F_AXI_MAXSTALL(0),
|
| 342 |
|
|
.F_AXI_MAXDELAY(0))
|
| 343 |
|
|
f_axi(.i_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
|
| 344 |
|
|
// AXI write address channnel
|
| 345 |
|
|
.i_axi_awready(o_axi_awready),
|
| 346 |
|
|
.i_axi_awid( i_axi_awid),
|
| 347 |
|
|
.i_axi_awaddr( i_axi_awaddr),
|
| 348 |
|
|
.i_axi_awlen( i_axi_awlen),
|
| 349 |
|
|
.i_axi_awsize( i_axi_awsize),
|
| 350 |
|
|
.i_axi_awburst(i_axi_awburst),
|
| 351 |
|
|
.i_axi_awlock( i_axi_awlock),
|
| 352 |
|
|
.i_axi_awcache(i_axi_awcache),
|
| 353 |
|
|
.i_axi_awprot( i_axi_awprot),
|
| 354 |
|
|
.i_axi_awqos( i_axi_awqos),
|
| 355 |
|
|
.i_axi_awvalid(i_axi_awvalid),
|
| 356 |
|
|
// AXI write data channel
|
| 357 |
|
|
.i_axi_wready( o_axi_wready),
|
| 358 |
|
|
.i_axi_wdata( i_axi_wdata),
|
| 359 |
|
|
.i_axi_wstrb( i_axi_wstrb),
|
| 360 |
|
|
.i_axi_wlast( i_axi_wlast),
|
| 361 |
|
|
.i_axi_wvalid( i_axi_wvalid),
|
| 362 |
|
|
// AXI write acknowledgement channel
|
| 363 |
|
|
.i_axi_bid( o_axi_bid), // Response ID
|
| 364 |
|
|
.i_axi_bresp( o_axi_bresp), // Write response
|
| 365 |
|
|
.i_axi_bvalid(o_axi_bvalid), // Write reponse valid
|
| 366 |
|
|
.i_axi_bready(i_axi_bready), // Response ready
|
| 367 |
|
|
// AXI read address channel
|
| 368 |
|
|
.i_axi_arready(o_axi_arready), // Read address ready
|
| 369 |
|
|
.i_axi_arid( i_axi_arid), // Read ID
|
| 370 |
|
|
.i_axi_araddr( i_axi_araddr), // Read address
|
| 371 |
|
|
.i_axi_arlen( i_axi_arlen), // Read Burst Length
|
| 372 |
|
|
.i_axi_arsize( i_axi_arsize), // Read Burst size
|
| 373 |
|
|
.i_axi_arburst(i_axi_arburst), // Read Burst type
|
| 374 |
|
|
.i_axi_arlock( i_axi_arlock), // Read lock type
|
| 375 |
|
|
.i_axi_arcache(i_axi_arcache), // Read Cache type
|
| 376 |
|
|
.i_axi_arprot( i_axi_arprot), // Read Protection type
|
| 377 |
|
|
.i_axi_arqos( i_axi_arqos), // Read Protection type
|
| 378 |
|
|
.i_axi_arvalid(i_axi_arvalid), // Read address valid
|
| 379 |
|
|
// AXI read data return
|
| 380 |
|
|
.i_axi_rid( o_axi_rid), // Response ID
|
| 381 |
|
|
.i_axi_rresp( o_axi_rresp), // Read response
|
| 382 |
|
|
.i_axi_rvalid( o_axi_rvalid), // Read reponse valid
|
| 383 |
|
|
.i_axi_rdata( o_axi_rdata), // Read data
|
| 384 |
|
|
.i_axi_rlast( o_axi_rlast), // Read last
|
| 385 |
|
|
.i_axi_rready( i_axi_rready), // Read Response ready
|
| 386 |
|
|
// Quantify where we are within a transaction
|
| 387 |
|
|
.f_axi_rd_outstanding( f_axi_rd_outstanding),
|
| 388 |
|
|
.f_axi_wr_outstanding( f_axi_wr_outstanding),
|
| 389 |
|
|
.f_axi_awr_outstanding(f_axi_awr_outstanding),
|
| 390 |
|
|
.f_axi_rd_id_outstanding(f_axi_rd_id_outstanding),
|
| 391 |
|
|
.f_axi_awr_id_outstanding(f_axi_awr_id_outstanding),
|
| 392 |
|
|
.f_axi_wr_id_outstanding(f_axi_wr_id_outstanding));
|
| 393 |
|
|
|
| 394 |
|
|
`endif
|
| 395 |
|
|
endmodule
|
| 396 |
|
|
|
