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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbarbiter.v
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//
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// Project: Pipelined Wishbone to AXI converter
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//
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// Purpose: This is a priority bus arbiter. It allows two separate wishbone
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// masters to connect to the same bus, while also guaranteeing
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// that one master can have the bus with no delay any time the other
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// master is not using the bus. The goal is to eliminate as much
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// combinatorial logic as possible, while still guarateeing minimum access
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// time for the priority (last, or alternate) channel.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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`define WBA_ALTERNATING
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//
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module wbarbiter(i_clk, i_reset,
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// Bus A -- the priority bus
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i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel,
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o_a_ack, o_a_stall, o_a_err,
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// Bus B
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i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel,
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o_b_ack, o_b_stall, o_b_err,
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// Combined/arbitrated bus
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o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
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parameter DW=32, AW=32;
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parameter SCHEME="ALTERNATING";
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parameter [0:0] OPT_ZERO_ON_IDLE = 1'b0;
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`ifdef FORMAL
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parameter F_LGDEPTH=3;
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`endif
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//
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input wire i_clk, i_reset;
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// Bus A
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input wire i_a_cyc, i_a_stb, i_a_we;
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input wire [(AW-1):0] i_a_adr;
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input wire [(DW-1):0] i_a_dat;
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input wire [(DW/8-1):0] i_a_sel;
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output wire o_a_ack, o_a_stall, o_a_err;
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// Bus B
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input wire i_b_cyc, i_b_stb, i_b_we;
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input wire [(AW-1):0] i_b_adr;
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input wire [(DW-1):0] i_b_dat;
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input wire [(DW/8-1):0] i_b_sel;
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output wire o_b_ack, o_b_stall, o_b_err;
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//
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output wire o_cyc, o_stb, o_we;
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output wire [(AW-1):0] o_adr;
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output wire [(DW-1):0] o_dat;
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output wire [(DW/8-1):0] o_sel;
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input wire i_ack, i_stall, i_err;
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// Go high immediately (new cycle) if ...
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// Previous cycle was low and *someone* is requesting a bus cycle
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// Go low immadiately if ...
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// We were just high and the owner no longer wants the bus
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// WISHBONE Spec recommends no logic between a FF and the o_cyc
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// This violates that spec. (Rec 3.15, p35)
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reg r_a_owner;
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assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc;
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initial r_a_owner = 1'b1;
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generate if (SCHEME == "PRIORITY")
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begin : PRI
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always @(posedge i_clk)
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if (!i_b_cyc)
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r_a_owner <= 1'b1;
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// Allow B to set its CYC line w/o activating this
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// interface
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else if ((i_b_stb)&&(!i_a_cyc))
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r_a_owner <= 1'b0;
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end else if (SCHEME == "ALTERNATING")
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begin : ALT
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reg last_owner;
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initial last_owner = 1'b0;
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always @(posedge i_clk)
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if ((i_a_cyc)&&(r_a_owner))
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last_owner <= 1'b1;
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else if ((i_b_cyc)&&(!r_a_owner))
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last_owner <= 1'b0;
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always @(posedge i_clk)
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if ((!i_a_cyc)&&(!i_b_cyc))
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r_a_owner <= !last_owner;
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else if ((r_a_owner)&&(!i_a_cyc))
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begin
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if (i_b_stb)
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r_a_owner <= 1'b0;
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end else if ((!r_a_owner)&&(!i_b_cyc))
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begin
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if (i_a_stb)
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r_a_owner <= 1'b1;
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end
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end else // if (SCHEME == "LAST")
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begin : LST
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always @(posedge i_clk)
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if ((!i_a_cyc)&&(i_b_stb))
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r_a_owner <= 1'b0;
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else if ((!i_b_cyc)&&(i_a_stb))
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r_a_owner <= 1'b1;
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end endgenerate
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// Realistically, if neither master owns the bus, the output is a
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// don't care. Thus we trigger off whether or not 'A' owns the bus.
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// If 'B' owns it all we care is that 'A' does not. Likewise, if
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// neither owns the bus than the values on the various lines are
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// irrelevant.
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assign o_we = (r_a_owner) ? i_a_we : i_b_we;
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generate if (OPT_ZERO_ON_IDLE)
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begin
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//
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// OPT_ZERO_ON_IDLE will use up more logic and may even slow
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// down the master clock if set. However, it may also reduce
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// the power used by the FPGA by preventing things from toggling
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// when the bus isn't in use. The option is here because it
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// also makes it a lot easier to look for when things happen
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// on the bus via VERILATOR when timing and logic counts
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// don't matter.
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//
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assign o_stb = (o_cyc)? ((r_a_owner) ? i_a_stb : i_b_stb):0;
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assign o_adr = (o_stb)? ((r_a_owner) ? i_a_adr : i_b_adr):0;
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assign o_dat = (o_stb)? ((r_a_owner) ? i_a_dat : i_b_dat):0;
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assign o_sel = (o_stb)? ((r_a_owner) ? i_a_sel : i_b_sel):0;
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assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0;
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assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0;
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assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
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assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1;
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assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
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assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0;
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end else begin
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assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb;
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assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
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assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
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assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel;
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// We cannot allow the return acknowledgement to ever go high if
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// the master in question does not own the bus. Hence we force
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// it low if the particular master doesn't own the bus.
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assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0;
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assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0;
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// Stall must be asserted on the same cycle the input master
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// asserts the bus, if the bus isn't granted to him.
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assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
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assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1;
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//
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//
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assign o_a_err = ( r_a_owner) ? i_err : 1'b0;
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assign o_b_err = (!r_a_owner) ? i_err : 1'b0;
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end endgenerate
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// Make Verilator happy
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// verilator lint_off UNUSED
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wire unused;
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assign unused = i_reset;
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// verilator lint_on UNUSED
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`ifdef FORMAL
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`ifdef WBARBITER
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reg f_last_clk;
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initial assume(!i_clk);
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always @($global_clock)
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begin
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assume(i_clk != f_last_clk);
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f_last_clk <= i_clk;
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end
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`define ASSUME assume
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`else
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`define ASSUME assert
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`endif
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @($global_clock)
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f_past_valid <= 1'b1;
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initial `ASSUME(!i_a_cyc);
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initial `ASSUME(!i_a_stb);
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initial `ASSUME(!i_b_cyc);
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initial `ASSUME(!i_b_stb);
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initial `ASSUME(!i_ack);
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initial `ASSUME(!i_err);
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always @(posedge i_clk)
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begin
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if (o_cyc)
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assert((i_a_cyc)||(i_b_cyc));
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if ((f_past_valid)&&($past(o_cyc))&&(o_cyc))
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assert($past(r_a_owner) == r_a_owner);
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end
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wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding,
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f_a_nreqs, f_a_nacks, f_a_outstanding,
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f_b_nreqs, f_b_nacks, f_b_outstanding;
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fwb_master #(.DW(DW), .AW(AW),
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.F_MAX_STALL(0),
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.F_LGDEPTH(F_LGDEPTH),
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.F_MAX_ACK_DELAY(0),
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.F_OPT_RMW_BUS_OPTION(1),
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.F_OPT_DISCONTINUOUS(1))
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f_wbm(i_clk, i_reset,
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o_cyc, o_stb, o_we, o_adr, o_dat, o_sel,
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i_ack, i_stall, 32'h0, i_err,
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f_nreqs, f_nacks, f_outstanding);
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fwb_slave #(.DW(DW), .AW(AW),
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.F_MAX_STALL(0),
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.F_LGDEPTH(F_LGDEPTH),
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.F_MAX_ACK_DELAY(0),
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.F_OPT_RMW_BUS_OPTION(1),
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.F_OPT_DISCONTINUOUS(1))
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f_wba(i_clk, i_reset,
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i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel,
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o_a_ack, o_a_stall, 32'h0, o_a_err,
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f_a_nreqs, f_a_nacks, f_a_outstanding);
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fwb_slave #(.DW(DW), .AW(AW),
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.F_MAX_STALL(0),
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.F_LGDEPTH(F_LGDEPTH),
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.F_MAX_ACK_DELAY(0),
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.F_OPT_RMW_BUS_OPTION(1),
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.F_OPT_DISCONTINUOUS(1))
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f_wbb(i_clk, i_reset,
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i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel,
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o_b_ack, o_b_stall, 32'h0, o_b_err,
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f_b_nreqs, f_b_nacks, f_b_outstanding);
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always @(posedge i_clk)
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if (r_a_owner)
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begin
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assert(f_b_nreqs == 0);
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assert(f_b_nacks == 0);
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assert(f_a_outstanding == f_outstanding);
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end else begin
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assert(f_a_nreqs == 0);
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assert(f_a_nacks == 0);
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assert(f_b_outstanding == f_outstanding);
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end
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))
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&&($past(i_a_stb))&&(!$past(i_b_cyc)))
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assert(r_a_owner);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))
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&&(!$past(i_a_cyc))&&($past(i_b_stb)))
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assert(!r_a_owner);
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always @(posedge i_clk)
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if ((f_past_valid)&&(r_a_owner != $past(r_a_owner)))
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assert(!$past(o_cyc));
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`endif
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endmodule
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