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amulcock |
-------------------------------------------------------------------------------
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---- ----
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amulcock |
---- WISHBONE Wishbone_BFM IP Core ----
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amulcock |
---- ----
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amulcock |
---- This file is part of the Wishbone_BFM project ----
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---- http://www.opencores.org/cores/Wishbone_BFM/ ----
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amulcock |
---- ----
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---- Description ----
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amulcock |
---- Implementation of Wishbone_BFM IP core according to ----
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---- Wishbone_BFM IP core specification document. ----
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amulcock |
---- ----
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---- To Do: ----
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---- NA ----
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---- ----
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---- Author(s): ----
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---- Andrew Mulcock, amulcock@opencores.org ----
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---- ----
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-------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-------------------------------------------------------------------------------
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---- ----
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-- CVS Revision History ----
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---- ----
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-- $Log: not supported by cvs2svn $ ----
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---- ----
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use work.io_pack.all; -- contains the clock frequency integer
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library ieee;
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use ieee.std_logic_1164.all;
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-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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entity syscon is
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port(
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-- sys_con ports
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RST_sys : in std_logic;
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CLK_stop : in std_logic;
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RST_O : out std_logic;
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CLK_O : out std_logic
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);
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end syscon;
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architecture Behavioral of syscon is
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signal clk_internal : std_logic;
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signal rst_internal : std_logic := '0'; -- not reset
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begin
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-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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-- sys con siumulator
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clock_loop : process
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begin
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clk_internal <= '0';
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if CLK_stop = '1' then
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wait;
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end if;
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wait for clk_period/2;
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clk_internal <= '1';
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wait for clk_period/2;
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end process clock_loop;
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CLK_O <= clk_internal;
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rst_loop : process ( RST_sys, clk_internal )
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begin
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if ( RST_sys = '1' ) then
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rst_internal <= '1';
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elsif rising_edge( clk_internal ) then
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if RST_sys = '0' then
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rst_internal <= '0';
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end if;
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end if;
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end process rst_loop;
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RST_O <= rst_internal;
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end Behavioral;
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