URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [vhdl/] [clk_div.vhd] - Blame information for rev 42

Go to most recent revision | Details | Compare with Previous | View Log


library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;
 
ENTITY clk_div IS
 
        PORT
        (
                clock_25Mhz                             : IN    STD_LOGIC;
                clock_1MHz                              : OUT   STD_LOGIC;
                clock_100KHz                    : OUT   STD_LOGIC;
                clock_10KHz                             : OUT   STD_LOGIC;
                clock_1KHz                              : OUT   STD_LOGIC;
                clock_100Hz                             : OUT   STD_LOGIC;
                clock_10Hz                              : OUT   STD_LOGIC;
                clock_1Hz                               : OUT   STD_LOGIC);
 
END clk_div;
 
ARCHITECTURE a OF clk_div IS
 
        SIGNAL  count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL  count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
        SIGNAL  count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
        SIGNAL  clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
        SIGNAL  clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;
BEGIN
        PROCESS
        BEGIN
-- Divide by 25
                WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
                        IF count_1Mhz < 24 THEN
                                count_1Mhz <= count_1Mhz + 1;
                        ELSE
                                count_1Mhz <= "00000";
                        END IF;
                        IF count_1Mhz < 12 THEN
                                clock_1Mhz_int <= '0';
                        ELSE
                                clock_1Mhz_int <= '1';
                        END IF;
 
-- Ripple clocks are used in this code to save prescalar hardware
-- Sync all clock prescalar outputs back to master clock signal
                        clock_1Mhz <= clock_1Mhz_int;
                        clock_100Khz <= clock_100Khz_int;
                        clock_10Khz <= clock_10Khz_int;
                        clock_1Khz <= clock_1Khz_int;
                        clock_100hz <= clock_100hz_int;
                        clock_10hz <= clock_10hz_int;
                        clock_1hz <= clock_1hz_int;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
                        IF count_100Khz /= 4 THEN
                                count_100Khz <= count_100Khz + 1;
                        ELSE
                                count_100khz <= "000";
                                clock_100Khz_int <= NOT clock_100Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
                        IF count_10Khz /= 4 THEN
                                count_10Khz <= count_10Khz + 1;
                        ELSE
                                count_10khz <= "000";
                                clock_10Khz_int <= NOT clock_10Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
                        IF count_1Khz /= 4 THEN
                                count_1Khz <= count_1Khz + 1;
                        ELSE
                                count_1khz <= "000";
                                clock_1Khz_int <= NOT clock_1Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
                        IF count_100hz /= 4 THEN
                                count_100hz <= count_100hz + 1;
                        ELSE
                                count_100hz <= "000";
                                clock_100hz_int <= NOT clock_100hz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
                        IF count_10hz /= 4 THEN
                                count_10hz <= count_10hz + 1;
                        ELSE
                                count_10hz <= "000";
                                clock_10hz_int <= NOT clock_10hz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
                        IF count_1hz /= 4 THEN
                                count_1hz <= count_1hz + 1;
                        ELSE
                                count_1hz <= "000";
                                clock_1hz_int <= NOT clock_1hz_int;
                        END IF;
        END PROCESS;
 
END a;
 

Line No.	Rev	Author	Line
1	34	rrred	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.all;`
3			`use IEEE.STD_LOGIC_ARITH.all;`
4			`use IEEE.STD_LOGIC_UNSIGNED.all;`
5
6			`ENTITY clk_div IS`
7
8			`PORT`
9			`(`
10			`clock_25Mhz : IN STD_LOGIC;`
11			`clock_1MHz : OUT STD_LOGIC;`
12			`clock_100KHz : OUT STD_LOGIC;`
13			`clock_10KHz : OUT STD_LOGIC;`
14			`clock_1KHz : OUT STD_LOGIC;`
15			`clock_100Hz : OUT STD_LOGIC;`
16			`clock_10Hz : OUT STD_LOGIC;`
17			`clock_1Hz : OUT STD_LOGIC);`
18
19			`END clk_div;`
20
21			`ARCHITECTURE a OF clk_div IS`
22
23			`SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);`
24			`SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);`
25			`SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);`
26			`SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;`
27			`SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;`
28			`BEGIN`
29			`PROCESS`
30			`BEGIN`
31			`-- Divide by 25`
32			`WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';`
33			`IF count_1Mhz < 24 THEN`
34			`count_1Mhz <= count_1Mhz + 1;`
35			`ELSE`
36			`count_1Mhz <= "00000";`
37			`END IF;`
38			`IF count_1Mhz < 12 THEN`
39			`clock_1Mhz_int <= '0';`
40			`ELSE`
41			`clock_1Mhz_int <= '1';`
42			`END IF;`
43
44			`-- Ripple clocks are used in this code to save prescalar hardware`
45			`-- Sync all clock prescalar outputs back to master clock signal`
46			`clock_1Mhz <= clock_1Mhz_int;`
47			`clock_100Khz <= clock_100Khz_int;`
48			`clock_10Khz <= clock_10Khz_int;`
49			`clock_1Khz <= clock_1Khz_int;`
50			`clock_100hz <= clock_100hz_int;`
51			`clock_10hz <= clock_10hz_int;`
52			`clock_1hz <= clock_1hz_int;`
53			`END PROCESS;`
54
55			`-- Divide by 10`
56			`PROCESS`
57			`BEGIN`
58			`WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';`
59			`IF count_100Khz /= 4 THEN`
60			`count_100Khz <= count_100Khz + 1;`
61			`ELSE`
62			`count_100khz <= "000";`
63			`clock_100Khz_int <= NOT clock_100Khz_int;`
64			`END IF;`
65			`END PROCESS;`
66
67			`-- Divide by 10`
68			`PROCESS`
69			`BEGIN`
70			`WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';`
71			`IF count_10Khz /= 4 THEN`
72			`count_10Khz <= count_10Khz + 1;`
73			`ELSE`
74			`count_10khz <= "000";`
75			`clock_10Khz_int <= NOT clock_10Khz_int;`
76			`END IF;`
77			`END PROCESS;`
78
79			`-- Divide by 10`
80			`PROCESS`
81			`BEGIN`
82			`WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';`
83			`IF count_1Khz /= 4 THEN`
84			`count_1Khz <= count_1Khz + 1;`
85			`ELSE`
86			`count_1khz <= "000";`
87			`clock_1Khz_int <= NOT clock_1Khz_int;`
88			`END IF;`
89			`END PROCESS;`
90
91			`-- Divide by 10`
92			`PROCESS`
93			`BEGIN`
94			`WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';`
95			`IF count_100hz /= 4 THEN`
96			`count_100hz <= count_100hz + 1;`
97			`ELSE`
98			`count_100hz <= "000";`
99			`clock_100hz_int <= NOT clock_100hz_int;`
100			`END IF;`
101			`END PROCESS;`
102
103			`-- Divide by 10`
104			`PROCESS`
105			`BEGIN`
106			`WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';`
107			`IF count_10hz /= 4 THEN`
108			`count_10hz <= count_10hz + 1;`
109			`ELSE`
110			`count_10hz <= "000";`
111			`clock_10hz_int <= NOT clock_10hz_int;`
112			`END IF;`
113			`END PROCESS;`
114
115			`-- Divide by 10`
116			`PROCESS`
117			`BEGIN`
118			`WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';`
119			`IF count_1hz /= 4 THEN`
120			`count_1hz <= count_1hz + 1;`
121			`ELSE`
122			`count_1hz <= "000";`
123			`clock_1hz_int <= NOT clock_1hz_int;`
124			`END IF;`
125			`END PROCESS;`
126
127			`END a;`
128

Browse

Tools

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [vhdl/] [clk_div.vhd] - Blame information for rev 42