OpenCores
URL https://opencores.org/ocsvn/8b10b_encdec/8b10b_encdec/trunk

Subversion Repositories 8b10b_encdec

[/] [8b10b_encdec/] [web_uploads/] [8b10_enc.vhd] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 root
-------------------------------------------------------------------------------
2
--
3
-- Title        : 8b/10b Encoder
4
-- Design       : 8-bit to 10-bit Encoder
5
-- Project      : 8000 - 8b10b_encdec
6
-- Author       : Ken Boyette
7
-- Company      : Critia Computer, Inc.
8
--
9
-------------------------------------------------------------------------------
10
--
11
-- File                 : 8b10b_enc.vhd
12
-- Version              : 1.0
13
-- Generated    : 09.15.2006
14
-- By                   : Itf2Vhdl ver. 1.20
15
--
16
-------------------------------------------------------------------------------
17
--
18
-- Description :
19
--      This module provides 8-bit to 10-bit encoding.
20
--      It accepts 8-bit parallel data input and generates 10-bit encoded data
21
--      output in accordance with the 8b/10b standard.  This coding method was
22
--      described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
23
--      8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek and was granted
24
--      a U.S. Patent #4,486,739 in 1984 which has now expired.
25
--
26
--              The parallel 8-bit Binary input represent 256 possible values, called
27
--              characters.
28
--              The bits are identified as:
29
--                      HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
30
--              The     output is a 10-bit encoded character whose bits are identified as:
31
--                      AO, BO, CO, DO, EO, IO, FO, GO, HO, AJO (Least Significant to Most)
32
--              An additional 12 output characters, K, are defined for command and
33
--              synchronization use.
34
--              KI, is used to indicate that the input is for a special character.
35
--              All inputs and outputs are synchronous with an externally supplied
36
--              byte rate clock BYTECLK.
37
--              The encoded output is valid one clock after the input.
38
--              There is a reset input, RESET, to reset the logic.  The next rising 
39
--              BYTECLK after RESET is deasserted latches valid input data.
40
--
41
--              Note: This VHDL structure closely follows the discrete logic defined 
42
--              in the original article and the subsequent patent.
43
--              The Figures referenced are those in the patent.
44
-------------------------------------------------------------------------------
45
--              This program is licensed under the GPL.
46
-------------------------------------------------------------------------------
47
 
48
library IEEE;
49
use IEEE.STD_LOGIC_1164.all;
50
 
51
entity enc_8b10b is
52
    port(
53
                RESET : in std_logic ;          -- Global asynchronous reset (active high) 
54
                SBYTECLK : in std_logic ;       -- Master synchronous send byte clock
55
                KI : in std_logic ;                     -- Control (K) input(active high)
56
                AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
57
                JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic  -- Encoded out 
58
            );
59
end enc_8b10b;
60
 
61
architecture behavioral of enc_8b10b is
62
 
63
-- Signals to tie things together
64
        signal XLRESET, LRESET : std_logic ; -- Local synchronized RESET
65
        signal L40, L04, L13, L31, L22 : std_logic ;    -- Figure 3 Signals
66
        signal F4, G4, H4, K4, S, FNEG : std_logic ;    -- Figure 4 Signals 
67
        signal PD1S6, ND1S6, PD0S6, ND0S6 : std_logic ; -- Figure 5 Signals 
68
        signal ND1S4, ND0S4, PD1S4, PD0S4 : std_logic ; -- ...Figure 5
69
        signal COMPLS4, COMPLS6, NDL6 : std_logic ;     -- Figure 6 Signals 
70
        signal PDL6, LPDL6, PDL4, LPDL4 : std_logic ;   -- Figure 6
71
        signal NAO, NBO, NCO, NDO, NEO, NIO : std_logic ;       -- Figure 7 Signals
72
        signal NFO, NGO, NHO, NJO, SINT : std_logic ;   -- Figure 8
73
 
74
begin
75
 
76
        -- PROCESS: SYNCRST; Synchronize and delay RESET one clock for startup
77
 
78
        SYNCRST: process (RESET, XLRESET, SBYTECLK)
79
        begin
80
                if SBYTECLK'event and SBYTECLK = '1' then
81
                        XLRESET <= RESET ;
82
                elsif SBYTECLK'event and SBYTECLK = '0' then
83
                        LRESET <= XLRESET ;
84
                end if ;
85
        end process SYNCRST ;
86
 
87
        --
88
        -- 5b Input Function (Reference: Figure 3)
89
        --
90
 
91
        -- Four 1's
92
        L40 <=  AI and BI and CI and DI ;                                       -- 1,1,1,1
93
        -- Four 0's
94
        L04 <=  not AI and not BI and not CI and not DI ;       -- 0,0,0,0
95
        -- One 1 and three 0's
96
        L13 <=  (not AI and not BI and not CI and DI)           -- 0,0,0,1
97
                        or (not AI and not BI and CI and not DI)        -- 0,0,1,0              
98
                        or (not AI and BI and not CI and not DI)        -- 0,1,0,0
99
                        or (AI and not BI and not CI and not DI) ;      -- 1,0,0,0
100
        -- Three 1's and one 0          
101
        L31 <=  (AI and BI and CI and not DI)                   -- 1,1,1,0      
102
                        or (AI and BI and not CI and DI)                -- 1,1,0,1
103
                        or (AI and not BI and CI and DI)                -- 1,0,1,1
104
                        or (not AI and BI and CI and DI) ;              -- 0,1,1,1
105
        -- Two 1's and two 0's
106
        L22 <=  (not AI and not BI and CI and DI)               -- 0,0,1,1
107
                        or (not AI and BI and CI and not DI)    -- 0,1,1,0
108
                        or (AI and BI and not CI and not DI)    -- 1,1,0,0
109
                        or (AI and not BI and not CI and DI)    -- 1,0,0,1
110
                        or (not AI and BI and not CI and DI)    -- 0,1,0,1
111
                        or (AI and not BI and CI and not DI) ;  -- 1,0,1,0
112
 
113
        --
114
    -- 3b Input Function (Reference: Figure 4)
115
        --
116
 
117
        -- PROCESS: FN3B; Latch 3b and K inputs
118
    FN3B: process (SBYTECLK, FI, GI, HI, KI)
119
    begin       -- Falling edge of clock latches F,G,H,K inputs
120
        if SBYTECLK'event and SBYTECLK = '0' then
121
                F4 <= FI ;
122
                G4 <= GI ;
123
                        H4 <= HI ;
124
                        K4 <= KI ;
125
        end if;
126
    end process FN3B;
127
 
128
        -- PROCESS: FNS; Create and latch "S" function
129
        FNS: process (LRESET, SBYTECLK, PDL6, L31, DI, EI, NDL6, L13)
130
        begin
131
                if LRESET = '1' then
132
                        S <= '0' ;
133
                elsif SBYTECLK'event and SBYTECLK = '1' then
134
                        S <= (PDL6 and L31 and DI and not EI)
135
                        or (NDL6 and L13 and EI and not DI) ;
136
                end if;
137
        end process FNS ;
138
 
139
        -- Intermediate term for "F4 is Not Equal to G4"
140
        FNEG    <=  F4 xor      G4 ;
141
 
142
        --
143
        -- Disparity Control - Figure 5
144
        --
145
 
146
        PD1S6 <= (not L22 and not L31 and not EI)
147
                or (L13 and DI and EI) ;
148
 
149
        ND1S6 <= (L31 and not DI and not EI)
150
                or (EI and not L22 and not L13)
151
                or K4 ;
152
 
153
        PD0S6 <= (not L22 and not L13 and EI)
154
                or K4 ;
155
 
156
        ND0S6 <= (not L22 and not L31 and not EI)
157
                or (L13 and DI and EI) ;
158
 
159
        ND1S4 <= (F4 and G4);
160
 
161
        ND0S4 <= (not F4 and not G4);
162
 
163
        PD1S4 <= (not F4 and not G4)
164
                or (FNEG and K4) ;
165
 
166
        PD0S4 <= (F4 and G4 and H4) ;
167
 
168
        --
169
        -- Disparity Control - Figure 6
170
        --
171
 
172
        PDL6 <= (PD0S6 and not COMPLS6)
173
                        or (COMPLS6 and ND0S6)
174
                        or (not ND0S6 and not PD0S6 and LPDL4) ;
175
 
176
        NDL6 <= not PDL6 ;
177
 
178
        PDL4 <= (LPDL6 and not PD0S4 and not ND0S4)
179
                        or (ND0S4 and COMPLS4)
180
                        or (not COMPLS4 and PD0S4) ;
181
 
182
        -- PROCESS: CMPLS4; Disparity determines complimenting S4
183
        CMPLS4: process (LRESET, SBYTECLK, PDL6)
184
    begin
185
                if LRESET = '1' then
186
                        LPDL6 <= '0' ;
187
        elsif SBYTECLK'event and SBYTECLK = '1' then    -- Rising edge
188
                        LPDL6 <= PDL6 ;                                                         -- .. latches S4
189
        end if;
190
    end process CMPLS4 ;
191
 
192
        COMPLS4 <= (PD1S4 and not LPDL6)
193
                        xor (ND1S4 and LPDL6) ;
194
 
195
    -- PROCESS: CMPLS6; Disparity determines complimenting S6
196
        CMPLS6: process (LRESET, SBYTECLK, PDL4)
197
    begin
198
                if LRESET = '1' then
199
                        LPDL4 <= '0' ;
200
        elsif SBYTECLK'event and SBYTECLK = '0' then     -- Falling edge
201
                LPDL4 <= PDL4 ;                                                 -- .. latches S6
202
                end if;
203
    end process CMPLS6;
204
 
205
        COMPLS6 <= (ND1S6 and LPDL4)
206
                        xor (PD1S6 and not LPDL4) ;
207
 
208
        --
209
        -- 5b/6b Encoder - Figure 7
210
        --
211
 
212
        -- Logic for non-complimented (Normal) A,B,C,D,E,I outputs
213
        NAO <= AI ;
214
        NBO <= L04
215
                or (BI and not L40) ;
216
        NCO <= CI
217
                or L04
218
                or (L13 and DI and EI) ;
219
        NDO <= (DI and not L40) ;
220
        NEO <= (EI and not (L13 and DI and EI))
221
                or (L13 and not EI) ;
222
        NIO <= (L22 and not EI)
223
                or (L04 and EI)
224
                or (L13 and not DI and EI)
225
                or (L40 and EI)
226
                or (L22 and KI) ;
227
 
228
        -- PROCESS: ENC5B6B; Generate and latch LS 6 encoded bits
229
        ENC5B6B: process (LRESET, SBYTECLK, COMPLS6, NAO, NBO, NCO, NDO, NEO, NIO)
230
        begin
231
                if LRESET = '1' then
232
                        AO <= '0' ;
233
                        BO <= '0' ;
234
                        CO <= '0' ;
235
                        DO <= '0' ;
236
                        EO <= '0' ;
237
                        IO <= '0' ;
238
                elsif SBYTECLK'event and SBYTECLK = '1' then
239
                        AO <= COMPLS6 XOR NAO ; -- Least significant bit 0
240
                        BO <= COMPLS6 XOR NBO ;
241
                        CO <= COMPLS6 XOR NCO ;
242
                        DO <= COMPLS6 XOR NDO ;
243
                        EO <= COMPLS6 XOR NEO ;
244
                        IO <= COMPLS6 XOR NIO ; -- Most significant bit 6
245
                end if;
246
        end process ENC5B6B;
247
 
248
        --
249
        -- 3b/4b Encoder - Figure 8
250
        --
251
 
252
        -- Logic for the non-complimented F,G,H,J outputs
253
        SINT <= (S and F4 and G4 and H4)
254
                or (K4 and F4 and G4 and H4) ;
255
        NFO <= (F4 and not SINT) ;
256
        NGO <= G4
257
                or (not F4 and not G4 and not H4) ;
258
        NHO <= H4 ;
259
        NJO <= SINT
260
                or (FNEG and not H4) ;
261
 
262
        -- PROCESS: ENC3B4B; Generate and latch MS 4 encoded bits
263
        ENC3B4B: process (LRESET, SBYTECLK, COMPLS4, NFO, NGO, NHO, NJO)
264
        begin
265
                if LRESET = '1' then
266
                        FO <= '0' ;
267
                        GO <= '0' ;
268
                        HO <= '0' ;
269
                        JO <= '0' ;
270
                elsif SBYTECLK'event and SBYTECLK ='0' then
271
                        FO <= COMPLS4 XOR NFO ; -- Least significant bit 7
272
                        GO <= COMPLS4 XOR NGO ;
273
                        HO <= COMPLS4 XOR NHO ;
274
                        JO <= COMPLS4 XOR NJO ; -- Most significant bit 10
275
                end if;
276
        end process ENC3B4B ;
277
 
278
end behavioral;
279
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.