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[/] [8b10b_encdec/] [web_uploads/] [enc_8b10b_TB.vhd] - Blame information for rev 5

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-------------------------------------------------------------------------------
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--
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-- Title        : Test Bench for enc_8b10b
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-- Design       : 8b/10b Encoder Test Bench
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-- Project      : 8000 - 8b10b_encdec
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-- Author       : Ken Boyette
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-- Company      : Critia Computer, Inc.
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--
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-------------------------------------------------------------------------------
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--
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-- File                 : enc_8b10b_TB.vhd
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-- Version              : 1.0
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-- Generated    : 09.25.2006
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-- From                 : y:\Projects\8000\FPGA\VHDLSource\8b10b\8b10_enc.vhd
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-- By                   : Active-HDL Built-in Test Bench Generator ver. 1.2s
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Test Bench for enc_8b10b_tb
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--
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--      This testbench provides a sequence of data pattern stimuli for the
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--      enc_8b10b component.  It latches the encoded output and provides this
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--      for waveform display during simulation.  The test pattern generator
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--      alternately drives all data patterns and then the 12 defined K patterns.
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-------------------------------------------------------------------------------
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-- This program is licensed under the GPL
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity enc_8b10b_tb is
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end enc_8b10b_tb;
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architecture TB_ARCHITECTURE of enc_8b10b_tb is
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        component enc_8b10b
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        port(
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                RESET : in std_logic;
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                SBYTECLK : in std_logic;
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                KI : in std_logic;
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                AI : in std_logic;
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                BI : in std_logic;
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                CI : in std_logic;
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                DI : in std_logic;
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                EI : in std_logic;
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                FI : in std_logic;
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                GI : in std_logic;
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                HI : in std_logic;
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                AO : out std_logic;
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                BO : out std_logic;
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                CO : out std_logic;
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                DO : out std_logic;
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                EO : out std_logic;
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                FO : out std_logic;
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                IO : out std_logic;
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                GO : out std_logic;
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                HO : out std_logic;
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                JO : out std_logic
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                );
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        end component;
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        -- Special character code values
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        constant K28d0 : std_logic_vector := "00011100"; -- Balanced
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        constant K28d1 : std_logic_vector := "00111100"; -- Unbalanced comma
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        constant K28d2 : std_logic_vector := "01011100"; -- Unbalanced
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        constant K28d3 : std_logic_vector := "01111100"; -- Unbalanced
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        constant K28d4 : std_logic_vector := "10011100"; -- Balanced
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        constant K28d5 : std_logic_vector := "10111100"; -- Unbalanced comma
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        constant K28d6 : std_logic_vector := "11011100"; -- Unbalanced
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        constant K28d7 : std_logic_vector := "11111100"; -- Balanced comma
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        constant K23d7 : std_logic_vector := "11110111"; -- Balanced
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        constant K27d7 : std_logic_vector := "11111011"; -- Balanced
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        constant K29d7 : std_logic_vector := "11111101"; -- Balanced
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        constant K30d7 : std_logic_vector := "11111110"; -- Balanced
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        -- Stimulus signals - mapped to the input  of enc_8b10b
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        signal TRESET : std_logic;
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        signal TBYTECLK : std_logic;
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        signal TKO : std_logic;
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        signal TAO : std_logic;
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        signal TBO : std_logic;
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        signal TCO : std_logic;
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        signal TDO : std_logic;
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        signal TEO : std_logic;
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        signal TFO : std_logic;
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        signal TGO : std_logic;
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        signal THO : std_logic;
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        -- Observed signals - mapped from output of enc_8b10b
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        signal TA : std_logic;
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        signal TB : std_logic;
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        signal TC : std_logic;
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        signal TD : std_logic;
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        signal TE : std_logic;
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        signal TF : std_logic;
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        signal TI : std_logic;
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        signal TG : std_logic;
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        signal TH : std_logic;
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        signal TJ : std_logic;
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        -- Signals for TestBench control functions
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        signal tchar : std_logic_vector (7 downto 0) ;           -- All character vector
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        signal kcounter : std_logic_vector (3 downto 0) ;        -- K character counter
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        signal dcounter : std_logic_vector (7 downto 0) ;        -- D value counter
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        signal tcharout, tlcharout : std_logic_vector (9 downto 0) ;     -- Character output vector
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        signal tclken : std_logic ; -- Enables clock after short delay starting up
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        signal tcnten : std_logic ; -- Enables count after 1 cycle
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        signal tks : std_logic ; -- Use to select control function of encoder
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        signal dk : std_logic ; -- '0' if D, '1' if K
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begin
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        ---------------------------------------------------------------------------
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        -- Instantiate module
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        ---------------------------------------------------------------------------
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        encoder : enc_8b10b
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                port map (
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                        RESET => TRESET,
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                        SBYTECLK => TBYTECLK,
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                        KI => TKO,
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                        AI => TAO,
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                        BI => TBO,
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                        CI => TCO,
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                        DI => TDO,
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                        EI => TEO,
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                        FI => TFO,
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                        GI => TGO,
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                        HI => THO,
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                        AO => TA,
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                        BO => TB,
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                        CO => TC,
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                        DO => TD,
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                        EO => TE,
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                        IO => TI,
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                        FO => TF,
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                        GO => TG,
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                        HO => TH,
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                        JO => TJ
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                ) ;
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TRESET <= '1', '0' after 200 ns ; -- Start with a valid reset for 100ns
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tclken <= '0', '1' after 10 ns ; -- Start clock with valid state, then 10MHz
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process (TBYTECLK, tclken)
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begin
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        If (tclken = '0') then
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                TBYTECLK <= '0';
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        else TBYTECLK <= (not TBYTECLK) after 50 ns ;   -- Generate 10MHz byte clock
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        end if;
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end process ;
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process (TRESET, TBYTECLK)
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begin
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        if (TRESET = '1') then  -- Delay count 1 cycle 
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                tcnten <= '0' ;
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        elsif (TBYTECLK'event and TBYTECLK = '0') then
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                tcnten <= '1' ;
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        end if ;
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end process ;
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process (TRESET, TBYTECLK, tks, tcnten, kcounter, dcounter, tchar)
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begin
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        if (TRESET = '1') then
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                tchar <= "00000000" ;
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                tks <= '1' ; -- Set for K initially
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                dk <= '0' ;
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                kcounter <= "0000" ; -- Preset K counter
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                dcounter <= "00000000" ;        -- Preset D counter
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        elsif (TBYTECLK'event and TBYTECLK = '1') then
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                dk <= tks ;
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                if tks = '1' then       -- Output K characters
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                        kcounter <= kcounter + tcnten ; -- Increment counter
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                        dcounter <= "00000000" ;
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                        case kcounter is
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                                when "0000" => tchar <= K28d0 ;
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                                when "0001" => tchar <= K28d1 ;
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                                when "0010" => tchar <= K28d2 ;
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                                when "0011" => tchar <= K28d3 ;
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                                when "0100" => tchar <= K28d4 ;
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                                when "0101" => tchar <= K28d5 ;
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                                when "0110" => tchar <= K28d6 ;
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                                when "0111" => tchar <= K28d7 ;
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                                when "1000" => tchar <= K23d7 ;
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                                when "1001" => tchar <= K27d7 ;
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                                when "1010" => tchar <= K29d7 ;
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                                when "1011" => tchar <= K30d7 ;
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                                        tks <= '0' ;     -- Switch to D output
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                                when "1100" => tchar <= "00000000" ;
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                                when others => tchar(7 downto 0) <= K28d5 ;
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                        end case;
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                else dcounter <= dcounter + tcnten ;    -- Output D values
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                        tchar <= dcounter ;
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                        if dcounter = "11111111" then
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                                tks <= '1' ;    -- Repeat K portion
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                                kcounter <= "0000" ; -- Reset K counter
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                        end if;
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                end if ;
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        end if;
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end process ;
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-- Latch encoder output each rising edge for simulation display
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process (TBYTECLK)
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begin
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        if (TBYTECLK'event and TBYTECLK = '1') then
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                tlcharout(0) <= TA;
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                tlcharout(1) <= TB;
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                tlcharout(2) <= TC;
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                tlcharout(3) <= TD;
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                tlcharout(4) <= TE;
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                tlcharout(5) <= TI;
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                tlcharout(6) <= TF;
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                tlcharout(7) <= TG;
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                tlcharout(8) <= TH;
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                tlcharout(9) <= TJ;
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        end if;
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end process ;
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-- Connect our test values to the encoder inputs
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TAO <= tchar(0);
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TBO <= tchar(1);
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TCO <= tchar(2);
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TDO <= tchar(3);
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TEO <= tchar(4);
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TFO <= tchar(5);
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TGO <= tchar(6);
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THO <= tchar(7);
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TKO <= dk;
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-- Monitor encoder output
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tcharout(0) <= TA;
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tcharout(1) <= TB;
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tcharout(2) <= TC;
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tcharout(3) <= TD;
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tcharout(4) <= TE;
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tcharout(5) <= TI;
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tcharout(6) <= TF;
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tcharout(7) <= TG;
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tcharout(8) <= TH;
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tcharout(9) <= TJ;
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end TB_ARCHITECTURE;
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