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[/] [System09/] [trunk/] [rtl/] [Spartan3/] [ram16k_b16.vhd] - Blame information for rev 172

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1 172 davidgb 
-- $Id: ram16k_b16.vhd,v 1.2 2008/03/14 15:52:43 dilbert57 Exp $
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--===========================================================================--
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--                                                                           --
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--  ram16k_b16.vhd - 16KByte Block RAM Component for Spartan 3/3E            --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : ram16k_b16.vhd
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--
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--  Entity name    : ram_16k
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--
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--  Purpose        : Implements 16K of Synchronous Static RAM
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--                   using 16 x Spartan 3/3E RAMB16_S9 block rams
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--                   Used in the Digilent Spartan 3E500 System09 design
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--
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--  Dependencies   : ieee.Std_Logic_1164
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--                   ieee.std_logic_arith
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--                   unisim.vcomponents
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--
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--  Uses           : RAMB16_S9
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--
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--  Author         : John E. Kent
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--
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--  Email          : dilbert57@opencores.org
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--
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--  Web            : http://opencores.org/project,system09
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--
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--
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--  Copyright (C) 2005 - 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version Author      Date          Changes
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--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
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  use unisim.vcomponents.all;
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entity ram_16k is
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  port (
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    clk      : in  std_logic;
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    rst      : in  std_logic;
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    cs       : in  std_logic;
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    addr     : in  std_logic_vector (13 downto 0);
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    rw       : in  std_logic;
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    data_in  : in  std_logic_vector (7 downto 0);
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    data_out : out std_logic_vector (7 downto 0)
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  );
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end ram_16k;
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architecture rtl of ram_16k is
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  signal we         : std_logic;
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  signal dp         : std_logic_vector(15 downto 0);
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  signal ce         : std_logic_vector(15 downto 0);
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  signal data_out_0 : std_logic_vector(7 downto 0);
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  signal data_out_1 : std_logic_vector(7 downto 0);
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  signal data_out_2 : std_logic_vector(7 downto 0);
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  signal data_out_3 : std_logic_vector(7 downto 0);
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  signal data_out_4 : std_logic_vector(7 downto 0);
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  signal data_out_5 : std_logic_vector(7 downto 0);
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  signal data_out_6 : std_logic_vector(7 downto 0);
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  signal data_out_7 : std_logic_vector(7 downto 0);
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begin
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  RAM0 : RAMB16_S9
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    port map (
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      do   => data_out_0,
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      dop(0) => dp(0),
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      addr => addr(10 downto 0),
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      clk  => clk,
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      di   => data_in,
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      dip(0) => dp(0),
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      en   => ce(0),
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      ssr  => rst,
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      we   => we
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    );
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  RAM1 : RAMB16_S9
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    port map (
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      do   => data_out_1,
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      dop(0) => dp(1),
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      addr => addr(10 downto 0),
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      clk  => clk,
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      di   => data_in,
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      dip(0) => dp(1),
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      en   => ce(1),
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      ssr  => rst,
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      we   => we
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    );
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  RAM2 : RAMB16_S9
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    port map (
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      do   => data_out_2,
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      dop(0) => dp(2),
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      addr => addr(10 downto 0),
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      clk  => clk,
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      di   => data_in,
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      dip(0) => dp(2),
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      en   => ce(2),
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      ssr  => rst,
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      we   => we
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    );
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  RAM3 : RAMB16_S9
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    port map (
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      do   => data_out_3,
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      dop(0) => dp(3),
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      addr => addr(10 downto 0),
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      clk  => clk,
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      di   => data_in,
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      dip(0) => dp(3),
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      en   => ce(3),
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      ssr  => rst,
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      we   => we
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    );
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  RAM4 : RAMB16_S9
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    port map (
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      do   => data_out_4,
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      dop(0) => dp(4),
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      addr => addr(10 downto 0),
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      clk  => clk,
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      di   => data_in,
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      dip(0) => dp(4),
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      en   => ce(4),
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      ssr  => rst,
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      we   => we
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    );
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  RAM5 : RAMB16_S9
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    port map (
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      do   => data_out_5,
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      dop(0) => dp(5),
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      addr => addr(10 downto 0),
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      clk  => clk,
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      di   => data_in,
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      dip(0) => dp(5),
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      en   => ce(5),
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      ssr  => rst,
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      we   => we
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    );
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  RAM6 : RAMB16_S9
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    port map (
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      do   => data_out_6,
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      dop(0) => dp(6),
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      addr => addr(10 downto 0),
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      clk  => clk,
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      di   => data_in,
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      dip(0) => dp(6),
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      en   => ce(6),
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      ssr  => rst,
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      we   => we
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    );
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  RAM7 : RAMB16_S9
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    port map (
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      do   => data_out_7,
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      dop(0) => dp(7),
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      addr => addr(10 downto 0),
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      clk  => clk,
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      di   => data_in,
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      dip(0) => dp(7),
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      en   => ce(7),
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      ssr  => rst,
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      we   => we
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    );
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my_ram_32k : process ( cs, rw, addr,
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                       data_out_0, data_out_1, data_out_2, data_out_3,
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                       data_out_4, data_out_5, data_out_6, data_out_7)
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begin
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         we <= not rw;
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         case addr(13 downto 11) is
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         when "000" =>
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             data_out <= data_out_0;
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         when "001" =>
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             data_out <= data_out_1;
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         when "010" =>
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             data_out <= data_out_2;
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         when "011" =>
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             data_out <= data_out_3;
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         when "100" =>
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             data_out <= data_out_4;
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         when "101" =>
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             data_out <= data_out_5;
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         when "110" =>
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             data_out <= data_out_6;
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         when "111" =>
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             data_out <= data_out_7;
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         when others =>
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             null;
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    end case;
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    ce(0)  <= cs and not( addr(13) ) and not( addr(12) ) and not( addr(11) );
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    ce(1)  <= cs and not( addr(13) ) and not( addr(12) ) and      addr(11)  ;
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    ce(2)  <= cs and not( addr(13) ) and      addr(12)   and not( addr(11) );
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    ce(3)  <= cs and not( addr(13) ) and      addr(12)   and      addr(11)  ;
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    ce(4)  <= cs and      addr(13)   and not( addr(12) ) and not( addr(11) );
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    ce(5)  <= cs and      addr(13)   and not( addr(12) ) and      addr(11)  ;
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    ce(6)  <= cs and      addr(13)   and      addr(12)   and not( addr(11) );
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    ce(7)  <= cs and      addr(13)   and      addr(12)   and      addr(11)  ;
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end process;
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end architecture rtl;
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