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[/] [System09/] [trunk/] [rtl/] [System09_BurchED_B5-X300_2/] [System09_BurchED_B5-X300.vhd] - Blame information for rev 104

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1 104 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--===========================================================================----
6
--
7
--  This core adheres to the GNU public license  
8
--
9
-- File name      : System09_BurchED_B5-X300.vhd
10
--
11
-- Purpose        : Top level file for 6809 compatible system on a chip
12
--                  Designed with Xilinx XC2S300e Spartan 2E FPGA.
13
--                  Implemented With BurchED B5-X300 FPGA board,
14
--                  B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
15
--
16
-- Dependencies   : ieee.Std_Logic_1164
17
--                  ieee.std_logic_unsigned
18
--                  ieee.std_logic_arith
19
--                  ieee.numeric_std
20
--
21
-- Uses           : 
22
--                  cpu09      (cpu09.vhd)      CPU core
23
--                  mon_rom    (sys09bug_rom2k_b4.vhd) Monitor ROM
24
--                  dat_ram    (datram.vhd)     Dynamic Address Translation
25
--                  acia_6850  (ACIA_6850.vhd) ACIA / MiniUART
26
--                             (ACIA_RX.vhd)
27
--                             (ACIA_TX.vhd)
28
--                  ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
29
--                  keyboard   (keyboard.vhd)   PS/2 Keyboard Interface
30
--                  vdu8       (vdu8.vhd)       80 x 25 Video Display
31
--                  timer      (timer.vhd)      Timer module
32
--                  trap            (trap.vhd)       Bus Trap interrupt
33
--                  uart1     (uart1.vhd)     Parallel I/O port.
34
-- 
35
-- Author         : John E. Kent      
36
--                  dilbert57@opencores.org      
37
--      Memory Map     :
38
-- $E000 - ACIA (SWTPc)
39
-- $E010 - Reserved for FD1771 FDC (SWTPc)
40
-- $E020 - Keyboard
41
-- $E030 - VDU
42
-- $E040 - Compact Flash
43
-- $E050 - Timer
44
-- $E060 - Bus trap
45
-- $E070 - Parallel I/O
46
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
47
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
48
--
49
--===========================================================================----
50
--
51
-- Revision History:
52
--===========================================================================--
53
-- Version 0.1 - 20 March 2003
54
-- Version 0.2 - 30 March 2003
55
-- Version 0.3 - 29 April 2003
56
-- Version 0.4 - 29 June 2003
57
--
58
-- Version 0.5 - 19 July 2003
59
-- prints out "Hello World"
60
--
61
-- Version 0.6 - 5 September 2003
62
-- Runs SBUG
63
--
64
-- Version 1.0- 6 Sep 2003 - John Kent
65
-- Inverted SysClk
66
-- Initial release to Open Cores
67
--
68
-- Version 1.1 - 17 Jan 2004 - John Kent
69
-- Updated miniUart.
70
--
71
-- Version 1.2 - 25 Jan 2004 - John Kent
72
-- removed signals "test_alu" and "test_cc" 
73
-- Trap hardware re-instated.
74
--
75
-- Version 1.3 - 11 Feb 2004 - John Kent
76
-- Designed forked off to produce System09_VDU
77
-- Added VDU component
78
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
79
-- UART Runs at 57.6 Kbps
80
--
81
-- Version 1.4 - 21 Nov 2004 - John Kent
82
-- Changes to make compatible with Spartan3 starter kit version
83
-- Designed to run with a 50MHz clock input.
84
-- the VDU divides 50 MHz to generate a 
85
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
86
-- Changed Monitor ROM signals to make it look like
87
-- a standard 2K memory block
88
-- Re-assigned I/O port assignments so it is possible to run KBUG9
89
-- $E000 - ACIA
90
-- $E010 - Keyboard
91
-- $E020 - VDU
92
-- $E030 - Compact Flash
93
-- $E040 - Timer
94
-- $E050 - Bus trap
95
-- $E060 - Parallel I/O
96
--
97
-- Version 1.5 - 3rd February 2007 - John Kent
98
-- Changed VDU8 to use external clock divider
99
-- renamed miniUART to ACIA_6850
100
-- Memory decoding of ROM & IO now uses DAT
101
--
102
-- Version 1.6 - 7th Februaury 2007 - John Kent
103
-- Made ACIA Clock generator an external component
104
-- Added Generics to VDU and Keyboard
105
-- Changed decoding
106
--
107
-- Version 1.7 - 20th May 2007 - John Kent
108
-- Added 4 wait states to CF access
109
-- Removed DAT memory map control of ROM & IO
110
-- to allow for full use of RAM as a RAM disk.
111
-- Mapped in all 16 bits of the CF data bus.
112
-- 
113
--===========================================================================
114
--
115
library ieee;
116
   use ieee.std_logic_1164.all;
117
   use IEEE.STD_LOGIC_ARITH.ALL;
118
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
119
   use ieee.numeric_std.all;
120
library unisim;
121
        use unisim.vcomponents.all;
122
 
123
entity System09 is
124
  port(
125
    SysClk      : in  Std_Logic;  -- System Clock input
126
         Reset_n     : in  Std_logic;  -- Master Reset input (active low)
127
    LED         : out std_logic;  -- Diagnostic LED Flasher
128
 
129
    -- Memory Interface signals
130
         -- B5-SRAM
131
    ram0_csn     : out Std_Logic;
132
    ram0_wrln    : out Std_Logic;
133
    ram0_wrun    : out Std_Logic;
134
    ram0_addr    : out Std_Logic_Vector(16 downto 0);
135
    ram0_data    : inout Std_Logic_Vector(15 downto 0);
136
 
137
    -- Memory Interface signals
138
         -- B3-SRAM
139
    ram1_csn     : out Std_Logic;
140
    ram1_wrln    : out Std_Logic;
141
    ram1_wrun    : out Std_Logic;
142
    ram1_addr    : out Std_Logic_Vector(16 downto 0);
143
    ram1_data    : inout Std_Logic_Vector(15 downto 0);
144
 
145
         -- B5 Peripheral IO Board
146
 
147
         -- PS/2 Keyboard
148
         kb0_clock    : inout Std_logic;
149
         kb0_data     : inout Std_Logic;
150
 
151
         -- PS/2 Mouse interface
152
--       mouse0_clock : in  Std_Logic;
153
--       mouse0_data  : in  Std_Logic;
154
 
155
         -- Uart Interface
156
    uart0_rxd   : in  Std_Logic;
157
         uart0_txd   : out Std_Logic;
158
    uart0_rts_n : out Std_Logic;
159
    uart0_cts_n : in  Std_Logic;
160
 
161
         -- CRTC output signals
162
         vga0_vs     : out Std_Logic;
163
    vga0_hs     : out Std_Logic;
164
    vga0_blue   : out std_logic_vector(1 downto 0);
165
    vga0_green  : out std_logic_vector(1 downto 0);
166
    vga0_red    : out std_logic_vector(1 downto 0);
167
 
168
    -- Buzzer
169
--         buzzer0      : out std_logic;
170
 
171
         -- B3 Peripheral Connect Board
172
 
173
         -- PS/2 Keyboard
174
--  kb1_clock    : inout Std_logic;
175
--  kb1_data     : inout Std_Logic;
176
 
177
         -- PS/2 Mouse interface
178
--       mouse0_clock : in  Std_Logic;
179
--       mouse0_data  : in  Std_Logic;
180
 
181
         -- Uart Interface
182
    uart1_rxd   : in  Std_Logic;
183
         uart1_txd   : out Std_Logic;
184
    uart1_rts_n : out Std_Logic;
185
    uart1_cts_n : in  Std_Logic;
186
 
187
         -- CRTC output signals
188
--  vga1_vs     : out Std_Logic;
189
--  vga1_hs     : out Std_Logic;
190
--  vga1_blue   : out std_logic_vector(1 downto 0);
191
--  vga1_green  : out std_logic_vector(1 downto 0);
192
--  vga1_red    : out std_logic_vector(1 downto 0);
193
 
194
    -- Buzzer
195
--         buzzer1      : out std_logic;
196
 
197
    -- Compact Flash
198
    cf_rst_n     : out std_logic;
199
    cf_cs0_n     : out std_logic;
200
    cf_cs1_n     : out std_logic;
201
    cf_rd_n      : out std_logic;
202
    cf_wr_n      : out std_logic;
203
    cf_a         : out std_logic_vector(2 downto 0);
204
    cf_d         : inout std_logic_vector(15 downto 0)
205
         );
206
end System09;
207
 
208
-------------------------------------------------------------------------------
209
-- Architecture for System09
210
-------------------------------------------------------------------------------
211
architecture rtl of System09 is
212
  -----------------------------------------------------------------------------
213
  -- constants
214
  -----------------------------------------------------------------------------
215
  constant SYS_CLK_FREQ   : integer := 50000000;  -- FPGA System Clock
216
  constant VGA_CLK_FREQ   : integer := 25000000;  -- VGA Pixel Clock
217
  constant CPU_CLK_FREQ   : integer := 12500000;  -- CPU Clock
218
  constant BAUD0_RATE     : integer := 57600;     -- Baud Rate
219
  constant BAUD1_RATE     : integer := 57600;     -- Baud Rate
220
  constant ACIA0_CLK_FREQ : integer := BAUD0_RATE * 16;
221
  constant ACIA1_CLK_FREQ : integer := BAUD1_RATE * 16;
222
 
223
  type hold_state_type is ( hold_release_state, hold_request_state );
224
 
225
  -----------------------------------------------------------------------------
226
  -- Signals
227
  -----------------------------------------------------------------------------
228
  -- Monitor ROM
229
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
230
  signal rom_cs        : std_logic;
231
 
232
  -- UART Interface signals
233
  signal uart0_data_out : Std_Logic_Vector(7 downto 0);
234
  signal uart0_cs       : Std_Logic;
235
  signal uart0_irq      : Std_Logic;
236
  signal uart0_clk      : Std_Logic;
237
  signal uart0_dcd_n    : Std_Logic;
238
 
239
  -- UART Interface signals
240
  signal uart1_data_out : Std_Logic_Vector(7 downto 0);
241
  signal uart1_cs       : Std_Logic;
242
  signal uart1_irq      : Std_Logic;
243
  signal uart1_clk      : Std_Logic;
244
  signal uart1_dcd_n    : Std_Logic;
245
 
246
  -- timer
247
  signal timer_data_out : std_logic_vector(7 downto 0);
248
  signal timer_cs    : std_logic;
249
  signal timer_irq   : std_logic;
250
 
251
  -- trap
252
  signal trap_cs         : std_logic;
253
  signal trap_data_out   : std_logic_vector(7 downto 0);
254
  signal trap_irq        : std_logic;
255
 
256
  -- compact flash port
257
  signal cf_data_out : std_logic_vector(7 downto 0);
258
  signal cf_cs       : std_logic;
259
  signal cf_rd       : std_logic;
260
  signal cf_wr       : std_logic;
261
  signal cf_hold     : std_logic;
262
  signal cf_release  : std_logic;
263
  signal cf_count    : std_logic_vector(3 downto 0);
264
  signal cf_hold_state : hold_state_type;
265
 
266
  -- keyboard port
267
  signal keyboard_data_out : std_logic_vector(7 downto 0);
268
  signal keyboard_cs       : std_logic;
269
  signal keyboard_irq      : std_logic;
270
 
271
  -- B5 RAM
272
  signal ram0_cs       : std_logic; -- memory chip select
273
  signal ram0_wrl      : std_logic; -- memory write lower
274
  signal ram0_wru      : std_logic; -- memory write upper
275
  signal ram0_data_out : std_logic_vector(7 downto 0);
276
 
277
  -- B3 RAM
278
  signal ram1_cs       : std_logic; -- memory chip select
279
  signal ram1_wrl      : std_logic; -- memory write lower
280
  signal ram1_wru      : std_logic; -- memory write upper
281
  signal ram1_data_out : std_logic_vector(7 downto 0);
282
 
283
  -- CPU Interface signals
284
  signal cpu_reset    : Std_Logic;
285
  signal cpu_clk      : Std_Logic;
286
  signal cpu_rw       : std_logic;
287
  signal cpu_vma      : std_logic;
288
  signal cpu_halt     : std_logic;
289
  signal cpu_hold     : std_logic;
290
  signal cpu_firq     : std_logic;
291
  signal cpu_irq      : std_logic;
292
  signal cpu_nmi      : std_logic;
293
  signal cpu_addr     : std_logic_vector(15 downto 0);
294
  signal cpu_data_in  : std_logic_vector(7 downto 0);
295
  signal cpu_data_out : std_logic_vector(7 downto 0);
296
 
297
  -- Dynamic address translation
298
  signal dat_cs       : std_logic;
299
  signal dat_addr     : std_logic_vector(7 downto 0);
300
 
301
  -- Video Display Unit
302
  signal vga_clk      : std_logic;
303
  signal vdu_cs       : std_logic;
304
  signal vdu_data_out : std_logic_vector(7 downto 0);
305
  signal vga_red      : std_logic;
306
  signal vga_green    : std_logic;
307
  signal vga_blue     : std_logic;
308
 
309
  -- Flashing Led test signals
310
  signal countL      : std_logic_vector(23 downto 0);
311
  signal clock_div   : std_logic_vector(1 downto 0);
312
 
313
-----------------------------------------------------------------
314
--
315
-- CPU09 CPU core
316
--
317
-----------------------------------------------------------------
318
 
319
component cpu09
320
  port (
321
         clk:        in std_logic;
322
    rst:      in        std_logic;
323
    rw:      out        std_logic;              -- Asynchronous memory interface
324
    vma:             out        std_logic;
325
    address:  out       std_logic_vector(15 downto 0);
326
    data_in:  in        std_logic_vector(7 downto 0);
327
         data_out: out std_logic_vector(7 downto 0);
328
         halt:     in  std_logic;
329
         hold:     in  std_logic;
330
         irq:      in  std_logic;
331
         nmi:      in  std_logic;
332
         firq:     in  std_logic
333
  );
334
end component;
335
 
336
 
337
----------------------------------------
338
--
339
-- SBUG Block RAM Monitor ROM
340
--
341
----------------------------------------
342
component mon_rom
343
    port (
344
       clk   : in  std_logic;
345
       rst   : in  std_logic;
346
       cs    : in  std_logic;
347
       rw    : in  std_logic;
348
       addr  : in  std_logic_vector (10 downto 0);
349
       wdata : in  std_logic_vector (7 downto 0);
350
       rdata : out std_logic_vector (7 downto 0)
351
    );
352
end component;
353
 
354
 
355
----------------------------------------
356
--
357
-- Dynamic Address Translation Registers
358
--
359
----------------------------------------
360
component dat_ram
361
  port (
362
    clk:      in  std_logic;
363
         rst:      in  std_logic;
364
         cs:       in  std_logic;
365
         rw:       in  std_logic;
366
         addr_lo:  in  std_logic_vector(3 downto 0);
367
         addr_hi:  in  std_logic_vector(3 downto 0);
368
    data_in:  in  std_logic_vector(7 downto 0);
369
         data_out: out std_logic_vector(7 downto 0)
370
         );
371
end component;
372
 
373
-----------------------------------------------------------------
374
--
375
-- 6850 ACIA/UART
376
--
377
-----------------------------------------------------------------
378
 
379
component ACIA_6850
380
  port (
381
     clk      : in  Std_Logic;  -- System Clock
382
     rst      : in  Std_Logic;  -- Reset input (active high)
383
     cs       : in  Std_Logic;  -- miniUART Chip Select
384
     rw       : in  Std_Logic;  -- Read / Not Write
385
     irq      : out Std_Logic;  -- Interrupt
386
     Addr     : in  Std_Logic;  -- Register Select
387
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
388
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
389
     RxC      : in  Std_Logic;  -- Receive Baud Clock
390
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
391
     RxD      : in  Std_Logic;  -- Receive Data
392
     TxD      : out Std_Logic;  -- Transmit Data
393
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
394
     CTS_n    : in  Std_Logic;  -- Clear To Send
395
     RTS_n    : out Std_Logic );  -- Request To send
396
end component;
397
 
398
-----------------------------------------------------------------
399
--
400
-- ACIA Clock divider
401
--
402
-----------------------------------------------------------------
403
 
404
component ACIA_Clock
405
  generic (
406
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
407
          ACIA_CLK_FREQ : integer
408
  );
409
  port (
410
     clk      : in  Std_Logic;  -- System Clock Input
411
          ACIA_clk : out Std_logic   -- ACIA Clock output
412
  );
413
end component;
414
 
415
----------------------------------------
416
--
417
-- Timer module
418
--
419
----------------------------------------
420
 
421
component timer
422
  port (
423
     clk       : in std_logic;
424
     rst       : in std_logic;
425
     cs        : in std_logic;
426
     rw        : in std_logic;
427
     addr      : in std_logic;
428
     data_in   : in std_logic_vector(7 downto 0);
429
          data_out  : out std_logic_vector(7 downto 0);
430
          irq       : out std_logic
431
          );
432
end component;
433
 
434
------------------------------------------------------------
435
--
436
-- Bus Trap logic
437
--
438
------------------------------------------------------------
439
 
440
component trap
441
        port (
442
         clk        : in  std_logic;
443
    rst        : in  std_logic;
444
    cs         : in  std_logic;
445
    rw         : in  std_logic;
446
    vma        : in  std_logic;
447
    addr       : in  std_logic_vector(15 downto 0);
448
    data_in    : in  std_logic_vector(7 downto 0);
449
         data_out   : out std_logic_vector(7 downto 0);
450
         irq        : out std_logic
451
  );
452
end component;
453
 
454
----------------------------------------
455
--
456
-- PS/2 Keyboard
457
--
458
----------------------------------------
459
 
460
component keyboard
461
  generic(
462
  KBD_CLK_FREQ : integer := CPU_CLK_FREQ
463
  );
464
  port(
465
  clk             : in    std_logic;
466
  rst             : in    std_logic;
467
  cs              : in    std_logic;
468
  rw              : in    std_logic;
469
  addr            : in    std_logic;
470
  data_in         : in    std_logic_vector(7 downto 0);
471
  data_out        : out   std_logic_vector(7 downto 0);
472
  irq             : out   std_logic;
473
  kbd_clk         : inout std_logic;
474
  kbd_data        : inout std_logic
475
  );
476
end component;
477
 
478
----------------------------------------
479
--
480
-- Video Display Unit.
481
--
482
----------------------------------------
483
component vdu8
484
      generic(
485
        VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- 25MHz
486
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
487
             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
488
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
489
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
490
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
491
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
492
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
493
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
494
             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
495
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
496
      );
497
      port(
498
                -- control register interface
499
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
500
      vdu_rst      : in  std_logic;
501
                vdu_cs       : in  std_logic;
502
                vdu_rw       : in  std_logic;
503
                vdu_addr     : in  std_logic_vector(2 downto 0);
504
      vdu_data_in  : in  std_logic_vector(7 downto 0);
505
      vdu_data_out : out std_logic_vector(7 downto 0);
506
 
507
      -- vga port connections
508
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
509
      vga_red_o    : out std_logic;
510
      vga_green_o  : out std_logic;
511
      vga_blue_o   : out std_logic;
512
      vga_hsync_o  : out std_logic;
513
      vga_vsync_o  : out std_logic
514
   );
515
end component;
516
 
517
 
518
component BUFG
519
  port (
520
                i: in  std_logic;
521
                o: out std_logic
522
  );
523
end component;
524
 
525
begin
526
  -----------------------------------------------------------------------------
527
  -- Instantiation of internal components
528
  -----------------------------------------------------------------------------
529
 
530
----------------------------------------
531
--
532
-- CPU09 CPU Core
533
--
534
----------------------------------------
535
my_cpu : cpu09  port map (
536
         clk         => cpu_clk,
537
    rst       => cpu_reset,
538
    rw       => cpu_rw,
539
    vma       => cpu_vma,
540
    address   => cpu_addr(15 downto 0),
541
    data_in   => cpu_data_in,
542
         data_out  => cpu_data_out,
543
         halt      => cpu_halt,
544
         hold      => cpu_hold,
545
         irq       => cpu_irq,
546
         nmi       => cpu_nmi,
547
         firq      => cpu_firq
548
  );
549
 
550
----------------------------------------
551
--
552
-- SBUG / KBUG / SYS09BUG Monitor ROM
553
--
554
----------------------------------------
555
my_rom : mon_rom port map (
556
       clk   => cpu_clk,
557
                 rst   => cpu_reset,
558
                 cs    => rom_cs,
559
                 rw    => '1',
560
       addr  => cpu_addr(10 downto 0),
561
                 wdata => cpu_data_out,
562
       rdata => rom_data_out
563
    );
564
 
565
----------------------------------------
566
--
567
-- Dynamic Address Translation Registers
568
--
569
----------------------------------------
570
my_dat : dat_ram port map (
571
    clk        => cpu_clk,
572
         rst        => cpu_reset,
573
         cs         => dat_cs,
574
         rw         => cpu_rw,
575
         addr_hi    => cpu_addr(15 downto 12),
576
         addr_lo    => cpu_addr(3 downto 0),
577
    data_in    => cpu_data_out,
578
         data_out   => dat_addr(7 downto 0)
579
         );
580
 
581
----------------------------------------
582
--
583
-- ACIA/UART Serial interface
584
--
585
----------------------------------------
586
my_ACIA0  : ACIA_6850 port map (
587
         clk         => cpu_clk,
588
         rst       => cpu_reset,
589
    cs        => uart0_cs,
590
         rw        => cpu_rw,
591
    irq       => uart0_irq,
592
    Addr      => cpu_addr(0),
593
         Datain    => cpu_data_out,
594
         DataOut   => uart0_data_out,
595
         RxC       => uart0_clk,
596
         TxC       => uart0_clk,
597
         RxD       => uart0_rxd,
598
         TxD       => uart0_txd,
599
         DCD_n     => uart0_dcd_n,
600
         CTS_n     => uart0_cts_n,
601
         RTS_n     => uart0_rts_n
602
         );
603
 
604
my_ACIA1  : ACIA_6850 port map (
605
         clk         => cpu_clk,
606
         rst       => cpu_reset,
607
    cs        => uart1_cs,
608
         rw        => cpu_rw,
609
    irq       => uart1_irq,
610
    Addr      => cpu_addr(0),
611
         Datain    => cpu_data_out,
612
         DataOut   => uart1_data_out,
613
         RxC       => uart1_clk,
614
         TxC       => uart1_clk,
615
         RxD       => uart1_rxd,
616
         TxD       => uart1_txd,
617
         DCD_n     => uart1_dcd_n,
618
         CTS_n     => uart1_cts_n,
619
         RTS_n     => uart1_rts_n
620
         );
621
 
622
----------------------------------------
623
--
624
-- ACIA Clock
625
--
626
----------------------------------------
627
my_ACIA0_Clock : ACIA_Clock
628
  generic map(
629
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
630
         ACIA_CLK_FREQ => ACIA0_CLK_FREQ
631
  )
632
  port map(
633
    clk        => SysClk,
634
    acia_clk   => uart0_clk
635
  );
636
 
637
my_ACIA1_Clock : ACIA_Clock
638
  generic map(
639
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
640
         ACIA_CLK_FREQ => ACIA1_CLK_FREQ
641
  )
642
  port map(
643
    clk        => SysClk,
644
    acia_clk   => uart1_clk
645
  );
646
 
647
 
648
----------------------------------------
649
--
650
-- PS/2 Keyboard Interface
651
--
652
----------------------------------------
653
my_keyboard : keyboard
654
   generic map (
655
        KBD_CLK_FREQ => CPU_CLK_FREQ
656
        )
657
   port map(
658
        clk          => cpu_clk,
659
        rst          => cpu_reset,
660
        cs           => keyboard_cs,
661
        rw           => cpu_rw,
662
        addr         => cpu_addr(0),
663
        data_in      => cpu_data_out(7 downto 0),
664
        data_out     => keyboard_data_out(7 downto 0),
665
        irq          => keyboard_irq,
666
        kbd_clk      => kb0_clock,
667
        kbd_data     => kb0_data
668
        );
669
 
670
----------------------------------------
671
--
672
-- Video Display Unit instantiation
673
--
674
----------------------------------------
675
my_vdu : vdu8
676
  generic map(
677
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
678
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
679
           VGA_HOR_CHARS          => 80, -- CHARACTERS
680
           VGA_VER_CHARS          => 25, -- CHARACTERS
681
           VGA_PIX_PER_CHAR       => 8,  -- PIXELS
682
           VGA_LIN_PER_CHAR       => 16, -- LINES
683
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
684
           VGA_HOR_SYNC           => 96, -- PIXELS
685
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
686
           VGA_VER_BACK_PORCH     => 13, -- LINES
687
           VGA_VER_SYNC           => 1,  -- LINES
688
           VGA_VER_FRONT_PORCH    => 36  -- LINES
689
  )
690
  port map(
691
 
692
                -- Control Registers
693
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
694
      vdu_rst       => cpu_reset,
695
                vdu_cs        => vdu_cs,
696
                vdu_rw        => cpu_rw,
697
                vdu_addr      => cpu_addr(2 downto 0),
698
                vdu_data_in   => cpu_data_out,
699
                vdu_data_out  => vdu_data_out,
700
 
701
      -- vga port connections
702
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
703
      vga_red_o     => vga_red,
704
      vga_green_o   => vga_green,
705
      vga_blue_o    => vga_blue,
706
      vga_hsync_o   => vga0_hs,
707
      vga_vsync_o   => vga0_vs
708
   );
709
 
710
----------------------------------------
711
--
712
-- Timer Module
713
--
714
----------------------------------------
715
my_timer  : timer port map (
716
    clk       => cpu_clk,
717
         rst       => cpu_reset,
718
    cs        => timer_cs,
719
         rw        => cpu_rw,
720
    addr      => cpu_addr(0),
721
         data_in   => cpu_data_out,
722
         data_out  => timer_data_out,
723
    irq       => timer_irq
724
    );
725
 
726
----------------------------------------
727
--
728
-- Bus Trap Interrupt logic
729
--
730
----------------------------------------
731
my_trap : trap port map (
732
         clk        => cpu_clk,
733
    rst        => cpu_reset,
734
    cs         => trap_cs,
735
    rw         => cpu_rw,
736
         vma        => cpu_vma,
737
    addr       => cpu_addr,
738
    data_in    => cpu_data_out,
739
         data_out   => trap_data_out,
740
         irq        => trap_irq
741
    );
742
 
743
 
744
--
745
-- 12.5 MHz CPU clock
746
--
747
cpu_clk_buffer : BUFG port map(
748
    i => clock_div(1),
749
         o => cpu_clk
750
    );
751
 
752
--
753
-- 25 MHz VGA Pixel clock
754
--
755
vga_clk_buffer : BUFG port map(
756
    i => clock_div(0),
757
         o => vga_clk
758
    );
759
 
760
----------------------------------------------------------------------
761
--
762
-- Process to decode memory map
763
--
764
----------------------------------------------------------------------
765
 
766
mem_decode: process( cpu_clk, Reset_n, dat_addr,
767
                     cpu_addr, cpu_rw, cpu_vma,
768
                                              rom_data_out,
769
                                                        ram0_data_out, ram1_data_out,
770
                                                        uart0_data_out, uart1_data_out,
771
                                                        keyboard_data_out,
772
                                                        vdu_data_out,
773
                                              cf_data_out,
774
                                                   timer_data_out,
775
                                                        trap_data_out )
776
variable decode_addr : std_logic_vector(4 downto 0);
777
begin
778
  decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
779
--    decode_addr := cpu_addr(15 downto 11);
780
 
781
  cpu_data_in <= (others=>'0');
782
  rom_cs      <= '0';
783
  dat_cs      <= '0';
784
  ram0_cs     <= '0';
785
  ram1_cs     <= '0';
786
  uart0_cs    <= '0';
787
  uart1_cs    <= '0';
788
  keyboard_cs <= '0';
789
  vdu_cs      <= '0';
790
  cf_cs       <= '0';
791
  timer_cs    <= '0';
792
  trap_cs     <= '0';
793
 
794
    if cpu_addr( 15 downto 8 ) = "11111111" then
795
                        cpu_data_in <= rom_data_out;
796
                        rom_cs      <= cpu_vma;              -- read ROM
797
                        dat_cs      <= cpu_vma;              -- write DAT
798
         else
799
      case decode_addr is
800
           --
801
                -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
802
                --
803
                when "11111" => -- $F800 - $FFFF
804
                   cpu_data_in <= rom_data_out;
805
                        rom_cs      <= cpu_vma;              -- read ROM
806
 
807
      --
808
                -- IO Devices $E000 - $E7FF
809
                --
810
                when "11100" => -- $E000 - $E7FF
811
                   case cpu_addr(7 downto 4) is
812
                        --
813
                        -- UART / ACIA $E000
814
                        --
815
                        when "0000" => -- $E000
816
                     cpu_data_in <= uart0_data_out;
817
                          uart0_cs    <= cpu_vma;
818
 
819
                        --
820
                        -- WD1771 FDC sites at $E010-$E01F
821
                        --
822
 
823
         --
824
         -- Keyboard port $E020 - $E02F
825
                        --
826
                        when "0010" => -- $E020
827
           cpu_data_in <= keyboard_data_out;
828
                          keyboard_cs <= cpu_vma;
829
 
830
         --
831
         -- VDU port $E030 - $E03F
832
                        --
833
                        when "0011" => -- $E030
834
           cpu_data_in <= vdu_data_out;
835
                          vdu_cs      <= cpu_vma;
836
 
837
         --
838
                        -- Compact Flash $E040 - $E04F
839
                        --
840
                        when "0100" => -- $E040
841
           cpu_data_in <= cf_data_out;
842
           cf_cs       <= cpu_vma;
843
 
844
         --
845
         -- Timer $E050 - $E05F
846
                        --
847
                        when "0101" => -- $E050
848
           cpu_data_in <= timer_data_out;
849
           timer_cs    <= cpu_vma;
850
 
851
         --
852
         -- Bus Trap Logic $E060 - $E06F
853
                        --
854
                        when "0110" => -- $E060
855
           cpu_data_in <= trap_data_out;
856
                          trap_cs     <= cpu_vma;
857
 
858
         --
859
         -- UART1 port $E070 - $E07F
860
                        --
861
                        when "0111" => -- $E070
862
           cpu_data_in <= uart1_data_out;
863
                          uart1_cs    <= cpu_vma;
864
 
865
                        when others => -- $E080 to $E7FF
866
                          null;
867
 
868
                   end case;
869
                --
870
                -- Everything else is RAM
871
                --
872
                when others =>
873
                  case dat_addr(7 downto 6) is
874
                  when "00" =>
875
                    cpu_data_in <= ram0_data_out;
876
                    ram0_cs     <= cpu_vma;
877
        when "01" =>
878
                    cpu_data_in <= ram1_data_out;
879
                    ram1_cs     <= cpu_vma;
880
        when others =>
881
                    null;
882
        end case;
883
 
884
                end case;
885
        end if;
886
end process;
887
 
888
 
889
--
890
-- B5-SRAM Control
891
-- Processes to read and write memory based on bus signals
892
--
893
ram0_process: process( cpu_clk, Reset_n,
894
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
895
                                               dat_addr,
896
                      ram0_cs, ram0_wrl, ram0_wru, ram0_data_out )
897
begin
898
    ram0_csn <= not( ram0_cs and Reset_n );
899
         ram0_wrl  <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
900
         ram0_wrln <= not (ram0_wrl);
901
    ram0_wru  <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
902
         ram0_wrun <= not (ram0_wru);
903
         ram0_addr(16 downto 11) <= dat_addr(5 downto 0);
904
         ram0_addr(10 downto 0) <= cpu_addr(11 downto 1);
905
 
906
    if ram0_wrl = '1' then
907
                ram0_data(7 downto 0) <= cpu_data_out;
908
         else
909
      ram0_data(7 downto 0) <= (others=>'Z');
910
         end if;
911
 
912
         if ram0_wru = '1' then
913
                ram0_data(15 downto 8) <= cpu_data_out;
914
         else
915
      ram0_data(15 downto 8)  <= (others=>'Z');
916
    end if;
917
 
918
         if cpu_addr(0) = '1' then
919
      ram0_data_out <= ram0_data(15 downto 8);
920
         else
921
      ram0_data_out <= ram0_data(7 downto 0);
922
    end if;
923
end process;
924
 
925
--
926
-- B3-SRAM Control
927
-- Processes to read and write memory based on bus signals
928
--
929
ram1_process: process( cpu_clk, Reset_n,
930
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
931
                                               dat_addr,
932
                      ram1_cs, ram1_wrl, ram1_wru, ram1_data_out )
933
begin
934
    ram1_csn <= not( ram1_cs and Reset_n );
935
         ram1_wrl  <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
936
         ram1_wrln <= not (ram1_wrl);
937
    ram1_wru  <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
938
         ram1_wrun <= not (ram1_wru);
939
         ram1_addr(16 downto 11) <= dat_addr(5 downto 0);
940
         ram1_addr(10 downto 0) <= cpu_addr(11 downto 1);
941
 
942
    if ram1_wrl = '1' then
943
                ram1_data(7 downto 0) <= cpu_data_out;
944
         else
945
      ram1_data(7 downto 0) <= (others=>'Z');
946
         end if;
947
 
948
         if ram1_wru = '1' then
949
                ram1_data(15 downto 8) <= cpu_data_out;
950
         else
951
      ram1_data(15 downto 8)  <= (others=>'Z');
952
    end if;
953
 
954
         if cpu_addr(0) = '1' then
955
      ram1_data_out <= ram1_data(15 downto 8);
956
         else
957
      ram1_data_out <= ram1_data(7 downto 0);
958
    end if;
959
end process;
960
 
961
--
962
-- Compact Flash Control
963
--
964
compact_flash: process( Reset_n,
965
                 cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
966
                                          cf_cs, cf_rd, cf_wr, cf_d )
967
begin
968
         cf_rst_n  <= Reset_n;
969
         cf_cs0_n  <= not( cf_cs ) or cpu_addr(3);
970
         cf_cs1_n  <= not( cf_cs and cpu_addr(3));
971
         cf_wr     <= cf_cs and (not cpu_rw);
972
         cf_rd     <= cf_cs and cpu_rw;
973
         cf_wr_n   <= not cf_wr;
974
         cf_rd_n   <= not cf_rd;
975
         cf_a      <= cpu_addr(2 downto 0);
976
         if cf_wr = '1' then
977
           cf_d(7 downto 0)  <= cpu_data_out;
978
         cf_d(15 downto 8) <= (others => '0');
979
         else
980
           cf_d(7 downto 0)  <= (others => 'Z');
981
         cf_d(15 downto 8) <= (others => 'Z');
982
         end if;
983
         cf_data_out <= cf_d(7 downto 0);
984
end process;
985
 
986
--
987
-- Hold CF access       for a few cycles
988
--
989
cf_hold_proc: process( cpu_clk, Reset_n )
990
begin
991
    if Reset_n = '0' then
992
                 cf_release    <= '0';
993
                 cf_count      <= "0000";
994
            cf_hold_state <= hold_release_state;
995
         elsif cpu_clk'event and cpu_clk='0' then
996
            case cf_hold_state is
997
                 when hold_release_state =>
998
          cf_release <= '0';
999
                    if cf_cs = '1' then
1000
                            cf_count      <= "0011";
1001
                                 cf_hold_state <= hold_request_state;
1002
                         end if;
1003
 
1004
                 when hold_request_state =>
1005
                    cf_count <= cf_count - "0001";
1006
                         if cf_count = "0000" then
1007
             cf_release    <= '1';
1008
                                 cf_hold_state <= hold_release_state;
1009
                         end if;
1010
       when others =>
1011
                    null;
1012
       end case;
1013
         end if;
1014
end process;
1015
 
1016
--
1017
-- Interrupts and other bus control signals
1018
--
1019
interrupts : process( Reset_n,
1020
                                                         cf_cs, cf_hold, cf_release,
1021
                      uart0_irq, uart1_irq,
1022
                      trap_irq, timer_irq, keyboard_irq
1023
                                                         )
1024
begin
1025
    cf_hold   <= cf_cs and (not cf_release);
1026
         cpu_reset <= not Reset_n; -- CPU reset is active high
1027
    cpu_irq   <= uart0_irq or uart1_irq or keyboard_irq;
1028
         cpu_nmi   <= trap_irq;
1029
         cpu_firq  <= timer_irq;
1030
         cpu_halt  <= '0';
1031
         cpu_hold  <= cf_hold;
1032
end process;
1033
 
1034
 
1035
--
1036
-- flash led to indicate code is working
1037
--
1038
my_LED_Flasher: process (cpu_clk, CountL )
1039
begin
1040
    if(cpu_clk'event and cpu_clk = '0') then
1041
      countL <= countL + 1;
1042
    end if;
1043
         LED <= countL(23);
1044
end process;
1045
 
1046
--
1047
-- Clock divider
1048
--
1049
my_clock_divider: process( SysClk )
1050
begin
1051
        if SysClk'event and SysClk='0' then
1052
                clock_div <= clock_div + "01";
1053
        end if;
1054
end process;
1055
--
1056
-- Assign VDU VGA colour output
1057
-- only 8 colours are handled.
1058
--
1059
my_vga_out: process( vga_red, vga_green, vga_blue )
1060
begin
1061
  vga0_red    <= vga_red   & vga_red;
1062
  vga0_green  <= vga_green & vga_green;
1063
  vga0_blue   <= vga_blue  & vga_blue;
1064
  uart0_dcd_n <= '0';
1065
  uart1_dcd_n <= '0';
1066
end process;
1067
 
1068
end rtl; --===================== End of architecture =======================--
1069
 

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