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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 162

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132
    SW2_N        : in  Std_logic;  -- Master Reset input (active low)
133
    SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
134
 
135
    -- RS232 Port
136
    RS232_RXD    : in  Std_Logic;
137
    RS232_TXD    : out Std_Logic;
138
 
139
    -- Status 7 segment LED
140 148 davidgb
    S            : out std_logic_vector(7 downto 0)
141 141 davidgb
 
142
-- CPU Debug Interface signals
143
--    cpu_reset_o     : out Std_Logic;
144
--    cpu_clk_o       : out Std_Logic;
145
--    cpu_rw_o        : out std_logic;
146
--    cpu_vma_o       : out std_logic;
147
--    cpu_halt_o      : out std_logic;
148
--    cpu_hold_o      : out std_logic;
149
--    cpu_firq_o      : out std_logic;
150
--    cpu_irq_o       : out std_logic;
151
--    cpu_nmi_o       : out std_logic;
152
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
153
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
154
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
155
 
156 148 davidgb
  );
157 141 davidgb
end system09;
158
 
159
-------------------------------------------------------------------------------
160
-- Architecture for System09
161
-------------------------------------------------------------------------------
162
architecture rtl of system09 is
163
 
164
  -----------------------------------------------------------------------------
165
  -- constants
166
  -----------------------------------------------------------------------------
167
 
168
  -- SDRAM
169
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
170
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
171
  constant PIPE_EN              : boolean := false;  -- if true, enable pipelined read operations
172
  constant MAX_NOP              : natural := 10000;  -- number of NOPs before entering self-refresh
173
  constant MULTIPLE_ACTIVE_ROWS : boolean := false;  -- if true, allow an active row in each bank
174
  constant DATA_WIDTH           : natural := 16;     -- host & SDRAM data width
175
  constant NROWS                : natural := 8192;   -- number of rows in SDRAM array
176
  constant NCOLS                : natural := 512;    -- number of columns in SDRAM array
177
  constant HADDR_WIDTH          : natural := 24;     -- host-side address width
178
  constant SADDR_WIDTH          : natural := 13;     -- SDRAM-side address width
179
 
180
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock
181
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
182
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
183
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
184
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
185
 
186
  constant TRESET               : natural := 300;      -- min initialization interval (us)
187
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
188
 
189
  type hold_state_type is ( hold_release_state, hold_request_state );
190
 
191
  -----------------------------------------------------------------------------
192
  -- Signals
193
  -----------------------------------------------------------------------------
194
  -- BOOT ROM
195
  signal rom_cs         : Std_logic;
196
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
197
 
198
  -- Flex Memory & Monitor Stack
199
  signal flex_cs        : Std_logic;
200
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
201
 
202
  -- ACIA/UART Interface signals
203
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
204
  signal acia_cs        : Std_Logic;
205
  signal acia_irq       : Std_Logic;
206
  signal acia_clk       : Std_Logic;
207
  signal rxd            : Std_Logic;
208
  signal txd            : Std_Logic;
209
  signal DCD_n          : Std_Logic;
210
  signal RTS_n          : Std_Logic;
211
  signal CTS_n          : Std_Logic;
212
 
213
  -- RAM
214
  signal ram_cs         : std_logic; -- memory chip select
215
  signal ram_data_out   : std_logic_vector(7 downto 0);
216
  signal ram_rd_req     : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
217
  signal ram_wr_req     : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge) 
218
  signal ram_hold       : std_logic; -- hold off slow accesses
219
  signal ram_release    : std_logic; -- Release ram hold
220
 
221
  -- CPU Interface signals
222
  signal cpu_reset      : Std_Logic;
223
  signal cpu_clk        : Std_Logic;
224
  signal cpu_rw         : std_logic;
225
  signal cpu_vma        : std_logic;
226
  signal cpu_halt       : std_logic;
227
  signal cpu_hold       : std_logic;
228
  signal cpu_firq       : std_logic;
229
  signal cpu_irq        : std_logic;
230
  signal cpu_nmi        : std_logic;
231
  signal cpu_addr       : std_logic_vector(15 downto 0);
232
  signal cpu_data_in    : std_logic_vector(7 downto 0);
233
  signal cpu_data_out   : std_logic_vector(7 downto 0);
234
 
235
  -- Dynamic Address Translation
236
  signal dat_cs       : std_logic;
237
  signal dat_addr     : std_logic_vector(7 downto 0);
238
 
239
  -- timer
240
  signal timer_data_out : std_logic_vector(7 downto 0);
241
  signal timer_cs       : std_logic;
242
  signal timer_irq      : std_logic;
243
 
244
  -- trap
245
  signal trap_cs        : std_logic;
246
  signal trap_data_out  : std_logic_vector(7 downto 0);
247
  signal trap_irq       : std_logic;
248
 
249
  -- Peripheral Bus port
250
  signal pb_data_out   : std_logic_vector(7 downto 0);
251 148 davidgb
  signal pb_cs         : std_logic;       -- peripheral bus chip select
252
  signal pb_wru        : std_logic;       -- upper byte write strobe
253
  signal pb_wrl        : std_logic;       -- lower byte write strobe
254
  signal pb_rdu        : std_logic;       -- upper byte read strobe
255
  signal pb_rdl        : std_logic;       -- lower byte read strobe
256
  signal pb_hold       : std_logic;       -- hold peripheral bus access
257
  signal pb_release    : std_logic;       -- release hold of peripheral bus
258 141 davidgb
  signal pb_count      : std_logic_vector(3 downto 0); -- hold counter
259
  signal pb_hold_state : hold_state_type;
260
  signal pb_wreg       : std_logic_vector(7 downto 0); -- lower byte write register
261
  signal pb_rreg       : std_logic_vector(7 downto 0); -- lower byte read register
262
 
263
  signal rst_i         : std_logic;     -- internal reset signal
264
  signal clk_i         : std_logic;     -- internal master clock signal
265
 
266
  -- signals that go through the SDRAM host-side interface
267
  signal opBegun       : std_logic;        -- SDRAM operation started indicator
268
  signal earlyBegun    : std_logic;        -- SDRAM operation started indicator
269
  signal ramDone       : std_logic;        -- SDRAM operation complete indicator
270
  signal rdDone        : std_logic;        -- SDRAM read operation complete indicator
271
  signal wrDone        : std_logic;        -- SDRAM write operation complete indicator
272
  signal hAddr         : std_logic_vector(HADDR_WIDTH-1 downto 0);  -- host address bus
273
  signal hDIn          : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
274
  signal hDOut         : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
275
  signal hRd           : std_logic;        -- host-side read control signal
276
  signal hWr           : std_logic;        -- host-side write control signal
277
  signal hUds          : std_logic;        -- host-side upper data strobe
278
  signal hLds          : std_logic;        -- host-side lower data strobe
279
  signal rdPending     : std_logic;        -- read operation pending in SDRAM pipeline
280
  type ram_type is (ram_state_0,
281
                    ram_state_rd1, ram_state_rd2,
282
                    ram_state_wr1,
283 148 davidgb
                                                  ram_state_3 );
284 141 davidgb
  signal ram_state     : ram_type;
285
 
286 148 davidgb
         signal flash_ce_n   :  std_logic;
287
    signal rs232_cts    :   Std_Logic;
288
    signal rs232_rts    :  Std_Logic;
289
 
290
--  signal BaudCount   : std_logic_vector(5 downto 0);
291 141 davidgb
 
292
  signal CountL        : std_logic_vector(23 downto 0);
293
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
294
  signal Clk25         : std_logic;
295
 
296
-----------------------------------------------------------------
297
--
298
-- CPU09 CPU core
299
--
300
-----------------------------------------------------------------
301
 
302
component cpu09
303
  port (
304
    clk:      in  std_logic;
305
    rst:      in  std_logic;
306
    vma:      out std_logic;
307
    addr:     out std_logic_vector(15 downto 0);
308
    rw:       out std_logic;     -- Asynchronous memory interface
309
    data_out: out std_logic_vector(7 downto 0);
310
    data_in:  in  std_logic_vector(7 downto 0);
311
    irq:      in  std_logic;
312
    firq:     in  std_logic;
313
    nmi:      in  std_logic;
314
    halt:     in  std_logic;
315
    hold:     in  std_logic
316
  );
317
end component;
318
 
319
----------------------------------------
320
--
321
-- 4K Block RAM Monitor ROM
322 148 davidgb
-- $F000 - $FFFF
323 141 davidgb
--
324
----------------------------------------
325 148 davidgb
 
326 141 davidgb
component mon_rom
327 148 davidgb
  Port (
328
    clk   : in  std_logic;
329
    rst   : in  std_logic;
330
    cs    : in  std_logic;
331
    rw    : in  std_logic;
332
    addr  : in  std_logic_vector (11 downto 0);
333
    data_out : out std_logic_vector (7 downto 0);
334
    data_in : in  std_logic_vector (7 downto 0)
335
  );
336 141 davidgb
end component;
337
 
338
----------------------------------------
339
--
340
-- 8KBytes Block RAM for FLEX9
341
-- $C000 - $DFFF
342
--
343
----------------------------------------
344 148 davidgb
 
345 141 davidgb
component flex_ram
346
  Port (
347
    clk      : in  std_logic;
348
    rst      : in  std_logic;
349
    cs       : in  std_logic;
350
    rw       : in  std_logic;
351
    addr     : in  std_logic_vector (12 downto 0);
352
    data_out    : out std_logic_vector (7 downto 0);
353
    data_in    : in  std_logic_vector (7 downto 0)
354 148 davidgb
  );
355 141 davidgb
end component;
356
 
357
-----------------------------------------------------------------
358
--
359
-- 6850 Compatible ACIA / UART
360
--
361
-----------------------------------------------------------------
362
 
363
component acia6850
364
  port (
365 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
366
    rst      : in  Std_Logic;  -- Reset input (active high)
367
    cs       : in  Std_Logic;  -- miniUART Chip Select
368
    rw       : in  Std_Logic;  -- Read / Not Write
369
    addr     : in  Std_Logic;  -- Register Select
370
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
371
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
372
    irq      : out Std_Logic;  -- Interrupt
373
    RxC      : in  Std_Logic;  -- Receive Baud Clock
374
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
375
    RxD      : in  Std_Logic;  -- Receive Data
376
    TxD      : out Std_Logic;  -- Transmit Data
377
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
378
    CTS_n    : in  Std_Logic;  -- Clear To Send
379
    RTS_n    : out Std_Logic   -- Request To send
380
  );
381 141 davidgb
end component;
382
 
383
-----------------------------------------------------------------
384
--
385
-- ACIA Clock divider
386
--
387
-----------------------------------------------------------------
388
 
389
component ACIA_Clock
390
  generic (
391 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
392
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
393 141 davidgb
  );
394
  port (
395 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
396
    ACIA_clk : out Std_logic   -- ACIA Clock output
397 141 davidgb
  );
398
end component;
399
 
400
----------------------------------------
401
--
402
-- Timer module
403
--
404
----------------------------------------
405
 
406
component timer
407
  port (
408 148 davidgb
    clk       : in std_logic;
409
    rst       : in std_logic;
410
    cs        : in std_logic;
411
    rw        : in std_logic;
412
    addr      : in std_logic;
413
    data_in   : in std_logic_vector(7 downto 0);
414
    data_out  : out std_logic_vector(7 downto 0);
415
    irq       : out std_logic
416
  );
417 141 davidgb
end component;
418
 
419
------------------------------------------------------------
420
--
421
-- Bus Trap logic
422
--
423
------------------------------------------------------------
424
 
425
component trap
426 148 davidgb
  port (
427 141 davidgb
    clk        : in  std_logic;
428
    rst        : in  std_logic;
429
    cs         : in  std_logic;
430
    rw         : in  std_logic;
431
    vma        : in  std_logic;
432
    addr       : in  std_logic_vector(15 downto 0);
433
    data_in    : in  std_logic_vector(7 downto 0);
434
    data_out   : out std_logic_vector(7 downto 0);
435
    irq        : out std_logic
436
  );
437
end component;
438
 
439
----------------------------------------
440
--
441
-- Dynamic Address Translation Registers
442
--
443
----------------------------------------
444 148 davidgb
 
445 141 davidgb
component dat_ram
446
  port (
447
    clk      : in  std_logic;
448
    rst      : in  std_logic;
449
    cs       : in  std_logic;
450
    rw       : in  std_logic;
451
    addr_lo  : in  std_logic_vector(3 downto 0);
452
    addr_hi  : in  std_logic_vector(3 downto 0);
453
    data_in  : in  std_logic_vector(7 downto 0);
454
    data_out : out std_logic_vector(7 downto 0)
455
  );
456
end component;
457
 
458
 
459
--
460
-- Clock buffer
461
--
462 148 davidgb
 
463 141 davidgb
component BUFG
464
   Port (
465
     i: in std_logic;
466
     o: out std_logic
467
  );
468
end component;
469
 
470
begin
471 148 davidgb
 
472 141 davidgb
  -----------------------------------------------------------------------------
473
  -- Instantiation of internal components
474
  -----------------------------------------------------------------------------
475
 
476 148 davidgb
  my_cpu : cpu09
477
    port map (
478
      clk       => cpu_clk,
479
      rst       => cpu_reset,
480
      vma       => cpu_vma,
481
      addr      => cpu_addr(15 downto 0),
482
      rw        => cpu_rw,
483
      data_out  => cpu_data_out,
484
      data_in   => cpu_data_in,
485
      irq       => cpu_irq,
486
      firq      => cpu_firq,
487
      nmi       => cpu_nmi,
488
      halt      => cpu_halt,
489
      hold      => cpu_hold
490
    );
491 141 davidgb
 
492 148 davidgb
  my_rom : mon_rom
493
    port map (
494
      clk   => cpu_clk,
495
      rst   => cpu_reset,
496
      cs    => rom_cs,
497
      rw    => '1',
498
      addr  => cpu_addr(11 downto 0),
499
      data_in => cpu_data_out,
500
      data_out => rom_data_out
501 141 davidgb
    );
502
 
503 148 davidgb
  my_flex : flex_ram
504
    port map (
505
      clk       => cpu_clk,
506
      rst       => cpu_reset,
507
      cs        => flex_cs,
508
      rw        => cpu_rw,
509
      addr      => cpu_addr(12 downto 0),
510
      data_out     => flex_data_out,
511
      data_in     => cpu_data_out
512 141 davidgb
    );
513
 
514 148 davidgb
  my_acia  : acia6850
515
    port map (
516
      clk       => cpu_clk,
517
      rst       => cpu_reset,
518
      cs        => acia_cs,
519
      rw        => cpu_rw,
520
      addr      => cpu_addr(0),
521
      data_in   => cpu_data_out,
522
      data_out  => acia_data_out,
523
      irq       => acia_irq,
524
      RxC       => acia_clk,
525
      TxC       => acia_clk,
526
      RxD       => rxd,
527
      TxD       => txd,
528
      DCD_n     => dcd_n,
529
      CTS_n     => cts_n,
530
      RTS_n     => rts_n
531 141 davidgb
    );
532
 
533 148 davidgb
  my_ACIA_Clock : ACIA_Clock
534
    generic map(
535
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
536
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
537
    )
538
    port map(
539
      clk        => Clk_i,
540
      acia_clk   => acia_clk
541
    );
542 141 davidgb
 
543 148 davidgb
  ----------------------------------------
544
  --
545
  -- Timer Module
546
  --
547
  ----------------------------------------
548
  my_timer  : timer
549
    port map (
550
      clk       => cpu_clk,
551
      rst       => cpu_reset,
552
      cs        => timer_cs,
553
      rw        => cpu_rw,
554
      addr      => cpu_addr(0),
555
      data_in   => cpu_data_out,
556
      data_out  => timer_data_out,
557
      irq       => timer_irq
558
    );
559 141 davidgb
 
560 148 davidgb
  ----------------------------------------
561
  --
562
  -- Bus Trap Interrupt logic
563
  --
564
  ----------------------------------------
565
  my_trap : trap
566
    port map (
567
      clk        => cpu_clk,
568
      rst        => cpu_reset,
569
      cs         => trap_cs,
570
      rw         => cpu_rw,
571
      vma        => cpu_vma,
572
      addr       => cpu_addr,
573
      data_in    => cpu_data_out,
574
      data_out   => trap_data_out,
575
      irq        => trap_irq
576 141 davidgb
    );
577
 
578 148 davidgb
  my_dat : dat_ram
579
    port map (
580
      clk       => cpu_clk,
581
      rst       => cpu_reset,
582
      cs        => dat_cs,
583
      rw        => cpu_rw,
584
      addr_hi   => cpu_addr(15 downto 12),
585
      addr_lo   => cpu_addr(3 downto 0),
586
      data_in   => cpu_data_out,
587
      data_out  => dat_addr(7 downto 0)
588 141 davidgb
    );
589
 
590 148 davidgb
  cpu_clk_buffer : BUFG
591 141 davidgb
    port map(
592 148 davidgb
      i => Clk25,
593
      o => cpu_clk
594 141 davidgb
    );
595 162 davidgb
 
596 148 davidgb
  ----------------------------------------------------------------------
597
  --
598
  -- Process to decode memory map
599
  --
600
  ----------------------------------------------------------------------
601 141 davidgb
 
602 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
603 141 davidgb
                     dat_addr,
604
                     rom_data_out,
605
                     flex_data_out,
606
                     acia_data_out,
607
                     pb_data_out,
608
                     timer_data_out,
609
                     trap_data_out,
610
                     ram_data_out
611
                     )
612 148 davidgb
  begin
613
    cpu_data_in <= (others=>'0');
614
    dat_cs      <= '0';
615
    rom_cs      <= '0';
616
    flex_cs     <= '0';
617
    acia_cs     <= '0';
618
    timer_cs    <= '0';
619
    trap_cs     <= '0';
620
    pb_cs       <= '0';
621
    ram_cs      <= '0';
622 141 davidgb
 
623 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
624
      cpu_data_in <= rom_data_out;
625
      dat_cs      <= cpu_vma;              -- write DAT
626
      rom_cs      <= cpu_vma;              -- read  ROM
627 141 davidgb
 
628 148 davidgb
    --
629
    -- Sys09Bug Monitor ROM $F000 - $FFFF
630
    --
631
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
632
      cpu_data_in <= rom_data_out;
633
      rom_cs      <= cpu_vma;
634 141 davidgb
 
635 148 davidgb
    --
636
    -- IO Devices $E000 - $E7FF
637
    --
638
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
639
      case cpu_addr(11 downto 8) is
640
        --
641
        -- SWTPC peripherals from $E000 to $E0FF
642
        --
643
        when "0000" =>
644
          case cpu_addr(7 downto 4) is
645
          --
646
          -- Console Port ACIA $E000 - $E00F
647
          --
648
            when "0000" => -- $E000
649
              cpu_data_in <= acia_data_out;
650
              acia_cs     <= cpu_vma;
651 141 davidgb
 
652 148 davidgb
            --
653
            -- Reserved
654
            -- Floppy Disk Controller port $E010 - $E01F
655
            --
656 141 davidgb
 
657 148 davidgb
            --
658
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
659
            --
660
            when "0100" => -- $E040
661
              cpu_data_in <= (others=> '0');
662 141 davidgb
 
663 148 davidgb
            --
664
            -- Timer $E050 - $E05F
665
            --
666
            when "0101" => -- $E050
667
              cpu_data_in <= timer_data_out;
668
              timer_cs    <= cpu_vma;
669 141 davidgb
 
670 148 davidgb
            --
671
            -- Bus Trap Logic $E060 - $E06F
672
            --
673
            when "0110" => -- $E060
674
              cpu_data_in <= trap_data_out;
675
              trap_cs     <= cpu_vma;
676 141 davidgb
 
677 148 davidgb
            --
678
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
679
            --
680
 
681
            --
682
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
683
            --
684
 
685
            --
686
            -- Remaining 6 slots reserved for non SWTPc Peripherals
687
            --
688
            when others => -- $E0A0 to $E0FF
689
              null;
690
          end case;
691
 
692
        --
693
        -- $E200 to $EFFF reserved for future use
694
        --
695
        when others =>
696 141 davidgb
           null;
697 148 davidgb
      end case;
698 141 davidgb
 
699 148 davidgb
    --
700
    -- Flex RAM $0C000 - $0DFFF
701
    --
702
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
703
      cpu_data_in <= flex_data_out;
704
      flex_cs     <= cpu_vma;
705 141 davidgb
 
706 148 davidgb
    --
707
    -- Everything else is RAM
708
    --
709 141 davidgb
    else
710 148 davidgb
      cpu_data_in <= ram_data_out;
711
      ram_cs      <= cpu_vma;
712 141 davidgb
    end if;
713
 
714 148 davidgb
  end process;
715 141 davidgb
 
716 148 davidgb
  --
717
  -- Interrupts and other bus control signals
718
  --
719
  interrupts : process( SW3_N,
720 141 davidgb
                      pb_cs, pb_hold, pb_release, ram_hold,
721
                      acia_irq,
722
                      trap_irq,
723
                      timer_irq
724
                      )
725 148 davidgb
  begin
726 141 davidgb
    pb_hold    <= pb_cs and (not pb_release);
727 162 davidgb
    cpu_irq    <= acia_irq;
728 141 davidgb
    cpu_nmi    <= trap_irq or not( SW3_N );
729
    cpu_firq   <= timer_irq;
730
    cpu_halt   <= '0';
731
    cpu_hold   <= pb_hold or ram_hold;
732
    FLASH_CE_N <= '1';
733 148 davidgb
  end process;
734 141 davidgb
 
735 148 davidgb
  --
736
  -- Flash 7 segment LEDS
737
  --
738
  my_led_flasher: process( clk_i, rst_i, CountL )
739
  begin
740 141 davidgb
    if rst_i = '1' then
741
         CountL <= "000000000000000000000000";
742
    elsif rising_edge(clk_i) then
743
         CountL <= CountL + 1;
744
    end if;
745 162 davidgb
    --S(7 downto 0) <= CountL(23 downto 16);
746 148 davidgb
  end process;
747 141 davidgb
 
748 148 davidgb
  --
749
  -- Generate CPU & Pixel Clock from Memory Clock
750
  --
751
  my_prescaler : process( clk_i, clk_count )
752
  begin
753
    if rising_edge( clk_i ) then
754
      if clk_count = 0 then
755
        clk_count <= CPU_CLK_DIV-1;
756
      else
757
        clk_count <= clk_count - 1;
758
      end if;
759
      if clk_count = 0 then
760
         clk25 <= '0';
761
      elsif clk_count = (CPU_CLK_DIV/2) then
762
         clk25 <= '1';
763
      end if;
764 141 davidgb
    end if;
765 148 davidgb
  end process;
766 141 davidgb
 
767 148 davidgb
  --
768
  -- Reset button and reset timer
769
  --
770 162 davidgb
  my_switch_assignments : process( rst_i, SW2_N)
771 148 davidgb
  begin
772
    rst_i <= not SW2_N;
773 162 davidgb
    cpu_reset <= rst_i;
774 148 davidgb
  end process;
775 141 davidgb
 
776 148 davidgb
  --
777
  -- RS232 signals:
778
  --
779
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
780
  begin
781
    rxd       <= RS232_RXD;
782
    cts_n     <= RS232_CTS;
783
    dcd_n     <= '0';
784
    RS232_TXD <= txd;
785
    RS232_RTS <= rts_n;
786
  end process;
787 141 davidgb
 
788 148 davidgb
  --
789
  -- CPU read data request on rising CPU clock edge
790
  --
791
  ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
792
  begin
793 141 davidgb
    if hRd = '1' then
794
      ram_rd_req   <= '0';
795
    elsif rising_edge(cpu_clk) then
796
      if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
797
        ram_rd_req   <= '1';
798
      end if;
799
    end if;
800 148 davidgb
  end process;
801 141 davidgb
 
802 148 davidgb
  --
803
  -- CPU write data to RAM valid on rising CPU clock edge
804
  --
805
  ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
806
  begin
807 141 davidgb
    if hWr = '1' then
808
       ram_wr_req   <= '0';
809
    elsif rising_edge(cpu_clk) then
810
      if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
811
        ram_wr_req   <= '1';
812
      end if;
813
    end if;
814 148 davidgb
  end process;
815 141 davidgb
 
816 162 davidgb
  status_leds : process( rst_i, cpu_reset)
817 148 davidgb
  begin
818 162 davidgb
    S(7) <= rst_i;
819
    S(6) <= cpu_reset;
820
    S(2) <= countL(23);
821
    S(3) <= countL(22);
822
         S(4) <= countL(21);
823
         S(5) <= countL(20);
824
         S(1) <= '1'; -- countL(19);
825
         S(0) <= '0'; -- countL(18);
826
    --S(7 downto 4) <= "0000";
827 148 davidgb
  end process;
828 141 davidgb
 
829 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
830 141 davidgb
--                      cpu_halt, cpu_hold,
831
--                      cpu_firq, cpu_irq, cpu_nmi,
832
--                      cpu_addr, cpu_data_out, cpu_data_in )
833 148 davidgb
--  begin
834
--    cpu_reset_o    <= cpu_reset;
835
--    cpu_clk_o      <= cpu_clk;
836
--    cpu_rw_o       <= cpu_rw;
837
--    cpu_vma_o      <= cpu_vma;
838
--    cpu_halt_o     <= cpu_halt;
839
--    cpu_hold_o     <= cpu_hold;
840
--    cpu_firq_o     <= cpu_firq;
841
--    cpu_irq_o      <= cpu_irq;
842
--    cpu_nmi_o      <= cpu_nmi;
843
--    cpu_addr_o     <= cpu_addr;
844
--    cpu_data_out_o <= cpu_data_out;
845
--    cpu_data_in_o  <= cpu_data_in;
846
--  end process;
847 141 davidgb
 
848
end rtl; --===================== End of architecture =======================--
849
 

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