Subversion Repositories System09

--===========================================================================----

--

--  S Y N T H E Z I A B L E    System09 - SOC.

--

--  www.OpenCores.Org - February 2007

--  This core adheres to the GNU public license  

--

-- File name      : System09_Xess_XSA-3S1000.vhd

--

-- Purpose        : Top level file for 6809 compatible system on a chip

--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.

--                  Implemented With XESS XSA-3S1000 FPGA board.

--                  *** Note ***

--                  This configuration can run Flex9 however it only has

--                  32k bytes of user memory and the VDU is monochrome

--                  The design needs to be updated to use the SDRAM on 

--                  the XSA-3S1000 board.

--                  This configuration also lacks a DAT so cannot use

--                  the RAM Disk features of SYS09BUG.

--

-- Dependencies   : ieee.Std_Logic_1164

--                  ieee.std_logic_unsigned

--                  ieee.std_logic_arith

--                  ieee.numeric_std

--                  unisim.vcomponents

--

-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM

--                  cpu09      (cpu09.vhd)          CPU core

--                  ACIA_6850  (acia6850.vhd)      ACIA / UART

--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.

--                  timer      (timer.vhd)            Interrupt timer

--                  trap       (trap.vhd)             Bus condition trap logic

--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system

--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM

--                  

-- 

-- Author         : John E. Kent      

--                  dilbert57@opencores.org      

--

-- Memory Map     :

--

-- $0000 - User program RAM (32K Bytes)

-- $C000 - Flex Operating System memory (8K Bytes)

-- $E000 - ACIA (SWTPc)

-- $E010 - Reserved for FD1771 FDC (SWTPc)

-- $E050 - Timer

-- $E060 - Bus trap

-- $E070 - Reserced for Parallel I/O (B5-X300)

-- $E080 - Reserved for 6821 PIA (?) (SWTPc)

-- $E090 - Reserved for 6840 PTM (?) (SWTPc)

-- $F000 - Sys09Bug monitor Program (4K Bytes)

--

--===========================================================================----

--

-- Revision History:

--===========================================================================--

-- Version 0.1 - 20 March 2003

-- Version 0.2 - 30 March 2003

-- Version 0.3 - 29 April 2003

-- Version 0.4 - 29 June 2003

--

-- Version 0.5 - 19 July 2003

-- prints out "Hello World"

--

-- Version 0.6 - 5 September 2003

-- Runs SBUG

--

-- Version 1.0- 6 Sep 2003 - John Kent

-- Inverted SysClk

-- Initial release to Open Cores

--

-- Version 1.1 - 17 Jan 2004 - John Kent

-- Updated miniUart.

--

-- Version 1.2 - 25 Jan 2004 - John Kent

-- removed signals "test_alu" and "test_cc" 

-- Trap hardware re-instated.

--

-- Version 1.3 - 11 Feb 2004 - John Kent

-- Designed forked off to produce System09_VDU

-- Added VDU component

-- VDU runs at 25MHz and divides the clock by 2 for the CPU

-- UART Runs at 57.6 Kbps

--

-- Version 2.0 - 2 September 2004 - John Kent

-- ported to Digilent Xilinx Spartan3 starter board

-- removed Compact Flash and Trap Logic.

-- Replaced SBUG with KBug9s

--

-- Version 3.0 - 29th August 2006 - John Kent

-- Adapted to XSA-3S1000 board.

-- Removed DAT and miniUART.

-- Used 32KBytes of Block RAM.

--

-- Version 3.1 - 15th January 2007 - John Kent

-- Modified vdu8 interface

-- Added a clock divider

--

-- Version 3.2 - 25th February 2007 - John Kent

-- reinstated ACIA_6850 and ACIA_Clock

-- Updated VDU8 & Keyboard with generic parameters

-- Defined Constants for clock speed calculations

--

-- Version 3.3 - 1st July 2007 - John Kent

-- Made VDU mono to save on one RAMB16

-- Used distributed memory for Key Map ROM to save one RAMB16

-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s

-- Added timer and trap logic

-- Added IDE Interface for Compact Flash

-- Replaced KBug9s and stack with Sys09Bug.

--

-- Version 4.0 - 1st February 2008 - John kent

-- Replaced Block RAM with SDRAM Interface

-- Modified Hold timing for SDRAM

-- Added CF and Ethernet interface 

-- via the 16 bit peripheral bus at $E100

--

--===========================================================================--

library ieee;

   use ieee.std_logic_1164.all;

   use IEEE.STD_LOGIC_ARITH.ALL;

   use IEEE.STD_LOGIC_UNSIGNED.ALL;

   use ieee.numeric_std.all;

library work;

   use work.common.all;

library unisim;

   use unisim.vcomponents.all;

entity system09 is

  port(

    CLKA         : in  Std_Logic;  -- 100MHz Clock input

    --RESET_N        : in  Std_logic;  -- Master Reset input (active low)

    --NMI_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)

    -- RS232 Port

    RS232_RTS    : out std_logic;

         RS232_CTS    : in  std_logic;

    RS232_RXD    : in  Std_Logic;

    RS232_TXD    : out Std_Logic;

    -- slide switches

         sw           : in std_logic_vector(7 downto 0);

         -- push buttons (Right=SS, Center=NMI, Left=RESET)

         btn          : in std_logic_vector(4 downto 0);

    -- Status 7 segment LED

    S            : out std_logic_vector(7 downto 0)

-- CPU Debug Interface signals

--    cpu_reset_o     : out Std_Logic;

--    cpu_clk_o       : out Std_Logic;

--    cpu_rw_o        : out std_logic;

--    cpu_vma_o       : out std_logic;

--    cpu_halt_o      : out std_logic;

--    cpu_hold_o      : out std_logic;

--    cpu_firq_o      : out std_logic;

--    cpu_irq_o       : out std_logic;

--    cpu_nmi_o       : out std_logic;

--    cpu_addr_o      : out std_logic_vector(15 downto 0);

--    cpu_data_in_o   : out std_logic_vector(7 downto 0);

--    cpu_data_out_o  : out std_logic_vector(7 downto 0);

  );

end system09;

-------------------------------------------------------------------------------

-- Architecture for System09

-------------------------------------------------------------------------------

architecture rtl of system09 is

  -----------------------------------------------------------------------------

  -- constants

  -----------------------------------------------------------------------------

  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step

  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz

  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)

  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)

  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)

  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);

  constant BAUD_RATE            : integer := 57600;     -- Baud Rate

  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;

  constant TRESET               : natural := 300;      -- min initialization interval (us)

  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval

  -----------------------------------------------------------------------------

  -- Signals

  -----------------------------------------------------------------------------

  signal pbtn           : std_logic_vector(4 downto 0);

  signal NMI_N          : std_logic;

  signal RESET_N        : std_logic;

  signal SINGLE_STEP    : std_logic;

  -- BOOT ROM

  signal rom_cs         : Std_logic;

  signal rom_data_out   : Std_Logic_Vector(7 downto 0);

  -- Flex Memory & Monitor Stack

  signal flex_cs        : Std_logic;

  signal flex_data_out  : Std_Logic_Vector(7 downto 0);

  -- ACIA/UART Interface signals

  signal acia_data_out  : Std_Logic_Vector(7 downto 0);

  signal acia_cs        : Std_Logic;

  signal acia_irq       : Std_Logic;

  signal acia_clk       : Std_Logic;

  signal rxd            : Std_Logic;

  signal txd            : Std_Logic;

  signal DCD_n          : Std_Logic;

  signal RTS_n          : Std_Logic;

  signal CTS_n          : Std_Logic;

  -- RAM

  signal ram1_cs         : std_logic;

  signal ram1_data_out   : std_logic_vector(7 downto 0);

  signal ram2_cs         : std_logic;

  signal ram2_data_out   : std_logic_vector(7 downto 0);

  signal ram3_cs         : std_logic;

  -- CPU Interface signals

  signal cpu_reset      : Std_Logic;

  signal cpu_clk        : Std_Logic;

  signal cpu_rw         : std_logic;

  signal cpu_vma        : std_logic;

  signal cpu_halt       : std_logic;

  signal cpu_hold       : std_logic;

  signal cpu_firq       : std_logic;

  signal cpu_irq        : std_logic;

  signal cpu_nmi        : std_logic;

  signal cpu_addr       : std_logic_vector(15 downto 0);

  signal cpu_data_in    : std_logic_vector(7 downto 0);

  signal cpu_data_out   : std_logic_vector(7 downto 0);

  -- Dynamic Address Translation

  signal dat_cs       : std_logic;

  signal dat_addr     : std_logic_vector(7 downto 0);

  -- timer

  signal timer_data_out : std_logic_vector(7 downto 0);

  signal timer_cs       : std_logic;

  signal timer_irq      : std_logic;

  -- trap

  signal trap_cs        : std_logic;

  signal trap_data_out  : std_logic_vector(7 downto 0);

  signal trap_irq       : std_logic;

  signal rst_i         : std_logic;     -- internal reset signal

  signal clk_i         : std_logic;     -- internal master clock signal

  signal CountL        : std_logic_vector(23 downto 0);

  signal clk_count     : natural range 0 to CPU_CLK_DIV;

  signal Clk25         : std_logic;

component btn_debounce

    Port ( BTN_I : in  STD_LOGIC_VECTOR (4 downto 0);

           CLK : in  STD_LOGIC;

           BTN_O : out  STD_LOGIC_VECTOR (4 downto 0));

end component;

-----------------------------------------------------------------

--

-- CPU09 CPU core

--

-----------------------------------------------------------------

component cpu09

  port (

    clk:      in  std_logic;

    rst:      in  std_logic;

    vma:      out std_logic;

    addr:     out std_logic_vector(15 downto 0);

    rw:       out std_logic;     -- Asynchronous memory interface

    data_out: out std_logic_vector(7 downto 0);

    data_in:  in  std_logic_vector(7 downto 0);

    irq:      in  std_logic;

    firq:     in  std_logic;

    nmi:      in  std_logic;

    halt:     in  std_logic;

    hold:     in  std_logic

  );

end component;

----------------------------------------

--

-- 4K Block RAM Monitor ROM

-- $F000 - $FFFF

--

----------------------------------------

component mon_rom

  Port (

    clk   : in  std_logic;

    rst   : in  std_logic;

    cs    : in  std_logic;

    rw    : in  std_logic;

    addr  : in  std_logic_vector (11 downto 0);

    data_out : out std_logic_vector (7 downto 0);

    data_in : in  std_logic_vector (7 downto 0)

  );

end component;

----------------------------------------

--

-- 8KBytes Block RAM for FLEX9

-- $C000 - $DFFF

--

----------------------------------------

component flex_ram

  Port (

    clk      : in  std_logic;

    rst      : in  std_logic;

    cs       : in  std_logic;

    rw       : in  std_logic;

    addr     : in  std_logic_vector (12 downto 0);

    data_out    : out std_logic_vector (7 downto 0);

    data_in    : in  std_logic_vector (7 downto 0)

  );

end component;

----------------------------------------

--

-- 32KBytes Block RAM 0000

-- $0000 - $7FFF

--

----------------------------------------

component ram_32k

  Port (

    clk      : in  std_logic;

    rst      : in  std_logic;

    cs       : in  std_logic;

    rw       : in  std_logic;

    addr     : in  std_logic_vector (14 downto 0);

    data_out    : out std_logic_vector (7 downto 0);

    data_in    : in  std_logic_vector (7 downto 0)

  );

end component;

----------------------------------------

--

-- 16KBytes Block RAM 8000

-- $8000 - $BFFF

--

----------------------------------------

component ram_16k

  Port (

    clk      : in  std_logic;

    rst      : in  std_logic;

    cs       : in  std_logic;

    rw       : in  std_logic;

    addr     : in  std_logic_vector (13 downto 0);

    data_out    : out std_logic_vector (7 downto 0);

    data_in    : in  std_logic_vector (7 downto 0)

  );

end component;

-----------------------------------------------------------------

--

-- 6850 Compatible ACIA / UART

--

-----------------------------------------------------------------

component acia6850

  port (

    clk      : in  Std_Logic;  -- System Clock

    rst      : in  Std_Logic;  -- Reset input (active high)

    cs       : in  Std_Logic;  -- miniUART Chip Select

    rw       : in  Std_Logic;  -- Read / Not Write

    addr     : in  Std_Logic;  -- Register Select

    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 

    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out

    irq      : out Std_Logic;  -- Interrupt

    RxC      : in  Std_Logic;  -- Receive Baud Clock

    TxC      : in  Std_Logic;  -- Transmit Baud Clock

    RxD      : in  Std_Logic;  -- Receive Data

    TxD      : out Std_Logic;  -- Transmit Data

    DCD_n    : in  Std_Logic;  -- Data Carrier Detect

    CTS_n    : in  Std_Logic;  -- Clear To Send

    RTS_n    : out Std_Logic   -- Request To send

  );

end component;

-----------------------------------------------------------------

--

-- ACIA Clock divider

--

-----------------------------------------------------------------

component ACIA_Clock

  generic (

    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;

    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ

  );

  port (

    clk      : in  Std_Logic;  -- System Clock Input

    ACIA_clk : out Std_logic   -- ACIA Clock output

  );

end component;

----------------------------------------

--

-- Timer module

--

----------------------------------------

component timer

  port (

    clk       : in std_logic;

    rst       : in std_logic;

    cs        : in std_logic;

    rw        : in std_logic;

    addr      : in std_logic;

    data_in   : in std_logic_vector(7 downto 0);

    data_out  : out std_logic_vector(7 downto 0);

    irq       : out std_logic

  );

end component;

------------------------------------------------------------

--

-- Bus Trap logic

--

------------------------------------------------------------

component trap

  port (

    clk        : in  std_logic;

    rst        : in  std_logic;

    cs         : in  std_logic;

    rw         : in  std_logic;

    vma        : in  std_logic;

    addr       : in  std_logic_vector(15 downto 0);

    data_in    : in  std_logic_vector(7 downto 0);

    data_out   : out std_logic_vector(7 downto 0);

    irq        : out std_logic

  );

end component;

----------------------------------------

--

-- Dynamic Address Translation Registers

--

----------------------------------------

component dat_ram

  port (

    clk      : in  std_logic;

    rst      : in  std_logic;

    cs       : in  std_logic;

    rw       : in  std_logic;

    addr_lo  : in  std_logic_vector(3 downto 0);

    addr_hi  : in  std_logic_vector(3 downto 0);

    data_in  : in  std_logic_vector(7 downto 0);

    data_out : out std_logic_vector(7 downto 0)

  );

end component;

--

-- Clock buffer

--

component BUFG

   Port (

     i: in std_logic;

     o: out std_logic

  );

end component;

begin

  --

  -- pushbutton debounce

  --

  my_singlestep: btn_debounce

    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);

  RESET_N     <= pbtn(3); -- Right PB

  NMI_N       <= pbtn(4); -- Center PB

  SINGLE_STEP <= pbtn(1); -- Left PB

  --

  -- Generate CPU & Pixel Clock from Memory Clock

  --

  NORMAL: if CLOCK_MODE = 0 generate

    my_prescaler : process( clk_i, clk_count )

    begin

      if rising_edge( clk_i ) then

        if clk_count = 0 then

          clk_count <= CPU_CLK_DIV-1;

        else

          clk_count <= clk_count - 1;

        end if;

        if clk_count = 0 then

           clk25 <= '0';

        elsif clk_count = (CPU_CLK_DIV/2) then

           clk25 <= '1';

        end if;

      end if;

    end process;

  end generate;

  SS: if CLOCK_MODE = 1 generate

    clk25 <= SINGLE_STEP;

  end generate;

  --

  -- Reset button and reset timer

  --

  my_switch_assignments : process( rst_i, RESET_N)

  begin

    rst_i <= RESET_N;

    cpu_reset <= rst_i;

  end process;

  clk_i <= CLKA;

  -----------------------------------------------------------------------------

  -- Instantiation of internal components

  -----------------------------------------------------------------------------

  my_cpu : cpu09

    port map (

      clk       => cpu_clk,

      rst       => cpu_reset,

      vma       => cpu_vma,

      addr      => cpu_addr(15 downto 0),

      rw        => cpu_rw,

      data_out  => cpu_data_out,

      data_in   => cpu_data_in,

      irq       => cpu_irq,

      firq      => cpu_firq,

      nmi       => cpu_nmi,

      halt      => cpu_halt,

      hold      => cpu_hold

    );

  my_rom : mon_rom

    port map (

      clk   => cpu_clk,

      rst   => cpu_reset,

      cs    => rom_cs,

      rw    => '1',

      addr  => cpu_addr(11 downto 0),

      data_in => cpu_data_out,

      data_out => rom_data_out

    );

  my_flex : flex_ram

    port map (

      clk       => cpu_clk,

      rst       => cpu_reset,

      cs        => flex_cs,

      rw        => cpu_rw,

      addr      => cpu_addr(12 downto 0),

      data_out     => flex_data_out,

      data_in     => cpu_data_out

    );

  my_32k : ram_32k

    port map (

      clk       => cpu_clk,

      rst       => cpu_reset,

      cs        => ram1_cs,

      rw        => cpu_rw,

      addr      => cpu_addr(14 downto 0),

      data_out     => ram1_data_out,

      data_in     => cpu_data_out

    );

  my_16k : ram_16k

    port map (

      clk       => cpu_clk,

      rst       => cpu_reset,

      cs        => ram2_cs,

      rw        => cpu_rw,

      addr      => cpu_addr(13 downto 0),

      data_out     => ram2_data_out,

      data_in     => cpu_data_out

    );

  my_acia  : acia6850

    port map (

      clk       => cpu_clk,

      rst       => cpu_reset,

      cs        => acia_cs,

      rw        => cpu_rw,

      addr      => cpu_addr(0),

      data_in   => cpu_data_out,

      data_out  => acia_data_out,

      irq       => acia_irq,

      RxC       => acia_clk,

      TxC       => acia_clk,

      RxD       => RS232_RXD,

      TxD       => RS232_TXD,

      DCD_n     => dcd_n,

      CTS_n     => RS232_CTS,

      RTS_n     => RS232_RTS

    );

  dcd_n <= '0';

  my_ACIA_Clock : ACIA_Clock

    generic map(

      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,

      ACIA_CLK_FREQ => ACIA_CLK_FREQ

    )

    port map(

      clk        => Clk_i,

      acia_clk   => acia_clk

    );

  ----------------------------------------

  --

  -- Timer Module

  --

  ----------------------------------------

  my_timer  : timer

    port map (

      clk       => cpu_clk,

      rst       => cpu_reset,

      cs        => timer_cs,

      rw        => cpu_rw,

      addr      => cpu_addr(0),

      data_in   => cpu_data_out,

      data_out  => timer_data_out,

      irq       => timer_irq

    );

  ----------------------------------------

  --

  -- Bus Trap Interrupt logic

  --

  ----------------------------------------

  my_trap : trap

    port map (

      clk        => cpu_clk,

      rst        => cpu_reset,

      cs         => trap_cs,

      rw         => cpu_rw,

      vma        => cpu_vma,

      addr       => cpu_addr,

      data_in    => cpu_data_out,

      data_out   => trap_data_out,

      irq        => trap_irq

    );

  my_dat : dat_ram

    port map (

      clk       => cpu_clk,

      rst       => cpu_reset,

      cs        => dat_cs,

      rw        => cpu_rw,

      addr_hi   => cpu_addr(15 downto 12),

      addr_lo   => cpu_addr(3 downto 0),

      data_in   => cpu_data_out,

      data_out  => dat_addr(7 downto 0)

    );

  cpu_clk_buffer : BUFG

    port map(

      i => Clk25,

      o => cpu_clk

    );

  ----------------------------------------------------------------------

  --

  -- Process to decode memory map

  --

  ----------------------------------------------------------------------

  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,

                     dat_addr,

                     rom_data_out,

                     flex_data_out,

                     acia_data_out,

                     timer_data_out,

                     trap_data_out,

                     ram1_data_out, ram2_data_out

                     )

  begin

    cpu_data_in <= (others=>'0');

    dat_cs      <= '0';

    rom_cs      <= '0';

    flex_cs     <= '0';

    acia_cs     <= '0';

    timer_cs    <= '0';

    trap_cs     <= '0';