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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 186

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132 186 davidgb
    --RESET_N        : in  Std_logic;  -- Master Reset input (active low)
133
    --NMI_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
134 141 davidgb
 
135 186 davidgb
    -- RS232 Port
136
    RS232_RTS    : out std_logic;
137
         RS232_CTS    : in  std_logic;
138 185 davidgb
    RS232_RXD    : in  Std_Logic;
139
    RS232_TXD    : out Std_Logic;
140 141 davidgb
 
141 186 davidgb
    -- slide switches
142 185 davidgb
         sw           : in std_logic_vector(7 downto 0);
143 186 davidgb
         -- push buttons (Right=SS, Center=NMI, Left=RESET)
144
         btn          : in std_logic_vector(4 downto 0);
145
    -- Status 7 segment LED
146 185 davidgb
    S            : out std_logic_vector(7 downto 0)
147
 
148
 
149 141 davidgb
-- CPU Debug Interface signals
150
--    cpu_reset_o     : out Std_Logic;
151
--    cpu_clk_o       : out Std_Logic;
152
--    cpu_rw_o        : out std_logic;
153
--    cpu_vma_o       : out std_logic;
154
--    cpu_halt_o      : out std_logic;
155
--    cpu_hold_o      : out std_logic;
156
--    cpu_firq_o      : out std_logic;
157
--    cpu_irq_o       : out std_logic;
158
--    cpu_nmi_o       : out std_logic;
159
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
160
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
161
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
162
 
163 148 davidgb
  );
164 141 davidgb
end system09;
165
 
166
-------------------------------------------------------------------------------
167
-- Architecture for System09
168
-------------------------------------------------------------------------------
169
architecture rtl of system09 is
170
 
171
  -----------------------------------------------------------------------------
172
  -- constants
173
  -----------------------------------------------------------------------------
174 186 davidgb
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
175
 
176 185 davidgb
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
177
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
178
 
179
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)
180 186 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
181 141 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
182
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
183
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
184
 
185 185 davidgb
  constant TRESET               : natural := 300;      -- min initialization interval (us)
186
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
187
 
188 141 davidgb
  -----------------------------------------------------------------------------
189
  -- Signals
190 174 davidgb
  -----------------------------------------------------------------------------
191 185 davidgb
  signal pbtn           : std_logic_vector(4 downto 0);
192 186 davidgb
  signal NMI_N          : std_logic;
193
  signal RESET_N        : std_logic;
194
  signal SINGLE_STEP    : std_logic;
195
 
196 141 davidgb
  -- BOOT ROM
197
  signal rom_cs         : Std_logic;
198
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
199
 
200
  -- Flex Memory & Monitor Stack
201
  signal flex_cs        : Std_logic;
202
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
203
 
204
  -- ACIA/UART Interface signals
205
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
206
  signal acia_cs        : Std_Logic;
207
  signal acia_irq       : Std_Logic;
208
  signal acia_clk       : Std_Logic;
209
  signal rxd            : Std_Logic;
210
  signal txd            : Std_Logic;
211
  signal DCD_n          : Std_Logic;
212
  signal RTS_n          : Std_Logic;
213
  signal CTS_n          : Std_Logic;
214
 
215
  -- RAM
216 173 davidgb
  signal ram1_cs         : std_logic;
217
  signal ram1_data_out   : std_logic_vector(7 downto 0);
218
  signal ram2_cs         : std_logic;
219
  signal ram2_data_out   : std_logic_vector(7 downto 0);
220
  signal ram3_cs         : std_logic;
221 141 davidgb
 
222
  -- CPU Interface signals
223
  signal cpu_reset      : Std_Logic;
224
  signal cpu_clk        : Std_Logic;
225
  signal cpu_rw         : std_logic;
226
  signal cpu_vma        : std_logic;
227
  signal cpu_halt       : std_logic;
228
  signal cpu_hold       : std_logic;
229
  signal cpu_firq       : std_logic;
230
  signal cpu_irq        : std_logic;
231
  signal cpu_nmi        : std_logic;
232
  signal cpu_addr       : std_logic_vector(15 downto 0);
233
  signal cpu_data_in    : std_logic_vector(7 downto 0);
234
  signal cpu_data_out   : std_logic_vector(7 downto 0);
235
 
236
  -- Dynamic Address Translation
237
  signal dat_cs       : std_logic;
238
  signal dat_addr     : std_logic_vector(7 downto 0);
239
 
240
  -- timer
241
  signal timer_data_out : std_logic_vector(7 downto 0);
242
  signal timer_cs       : std_logic;
243
  signal timer_irq      : std_logic;
244
 
245
  -- trap
246
  signal trap_cs        : std_logic;
247
  signal trap_data_out  : std_logic_vector(7 downto 0);
248
  signal trap_irq       : std_logic;
249
 
250
  signal rst_i         : std_logic;     -- internal reset signal
251 186 davidgb
  signal clk_i         : std_logic;     -- internal master clock signal
252 148 davidgb
 
253 185 davidgb
  signal CountL        : std_logic_vector(23 downto 0);
254 141 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
255
  signal Clk25         : std_logic;
256 185 davidgb
 
257
 
258
component btn_debounce
259
    Port ( BTN_I : in  STD_LOGIC_VECTOR (4 downto 0);
260
           CLK : in  STD_LOGIC;
261
           BTN_O : out  STD_LOGIC_VECTOR (4 downto 0));
262
end component;
263
 
264 141 davidgb
 
265
-----------------------------------------------------------------
266
--
267
-- CPU09 CPU core
268
--
269
-----------------------------------------------------------------
270
 
271
component cpu09
272
  port (
273
    clk:      in  std_logic;
274
    rst:      in  std_logic;
275
    vma:      out std_logic;
276
    addr:     out std_logic_vector(15 downto 0);
277
    rw:       out std_logic;     -- Asynchronous memory interface
278
    data_out: out std_logic_vector(7 downto 0);
279
    data_in:  in  std_logic_vector(7 downto 0);
280
    irq:      in  std_logic;
281
    firq:     in  std_logic;
282
    nmi:      in  std_logic;
283
    halt:     in  std_logic;
284
    hold:     in  std_logic
285
  );
286
end component;
287
 
288
----------------------------------------
289
--
290
-- 4K Block RAM Monitor ROM
291 148 davidgb
-- $F000 - $FFFF
292 141 davidgb
--
293
----------------------------------------
294 148 davidgb
 
295 141 davidgb
component mon_rom
296 148 davidgb
  Port (
297
    clk   : in  std_logic;
298
    rst   : in  std_logic;
299
    cs    : in  std_logic;
300
    rw    : in  std_logic;
301
    addr  : in  std_logic_vector (11 downto 0);
302
    data_out : out std_logic_vector (7 downto 0);
303
    data_in : in  std_logic_vector (7 downto 0)
304
  );
305 141 davidgb
end component;
306
 
307
----------------------------------------
308
--
309
-- 8KBytes Block RAM for FLEX9
310
-- $C000 - $DFFF
311
--
312
----------------------------------------
313 148 davidgb
 
314 141 davidgb
component flex_ram
315
  Port (
316
    clk      : in  std_logic;
317
    rst      : in  std_logic;
318
    cs       : in  std_logic;
319
    rw       : in  std_logic;
320
    addr     : in  std_logic_vector (12 downto 0);
321
    data_out    : out std_logic_vector (7 downto 0);
322
    data_in    : in  std_logic_vector (7 downto 0)
323 148 davidgb
  );
324 141 davidgb
end component;
325 170 davidgb
 
326
----------------------------------------
327
--
328
-- 32KBytes Block RAM 0000
329
-- $0000 - $7FFF
330
--
331
----------------------------------------
332 141 davidgb
 
333 170 davidgb
component ram_32k
334
  Port (
335
    clk      : in  std_logic;
336
    rst      : in  std_logic;
337
    cs       : in  std_logic;
338
    rw       : in  std_logic;
339
    addr     : in  std_logic_vector (14 downto 0);
340
    data_out    : out std_logic_vector (7 downto 0);
341
    data_in    : in  std_logic_vector (7 downto 0)
342
  );
343
end component;
344
 
345 173 davidgb
 
346
----------------------------------------
347
--
348
-- 16KBytes Block RAM 8000
349
-- $8000 - $BFFF
350
--
351
----------------------------------------
352 170 davidgb
 
353 173 davidgb
component ram_16k
354
  Port (
355
    clk      : in  std_logic;
356
    rst      : in  std_logic;
357
    cs       : in  std_logic;
358
    rw       : in  std_logic;
359
    addr     : in  std_logic_vector (13 downto 0);
360
    data_out    : out std_logic_vector (7 downto 0);
361
    data_in    : in  std_logic_vector (7 downto 0)
362
  );
363
end component;
364
 
365 141 davidgb
-----------------------------------------------------------------
366
--
367
-- 6850 Compatible ACIA / UART
368
--
369
-----------------------------------------------------------------
370
 
371
component acia6850
372
  port (
373 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
374
    rst      : in  Std_Logic;  -- Reset input (active high)
375
    cs       : in  Std_Logic;  -- miniUART Chip Select
376
    rw       : in  Std_Logic;  -- Read / Not Write
377
    addr     : in  Std_Logic;  -- Register Select
378
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
379
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
380
    irq      : out Std_Logic;  -- Interrupt
381
    RxC      : in  Std_Logic;  -- Receive Baud Clock
382
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
383
    RxD      : in  Std_Logic;  -- Receive Data
384
    TxD      : out Std_Logic;  -- Transmit Data
385
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
386
    CTS_n    : in  Std_Logic;  -- Clear To Send
387
    RTS_n    : out Std_Logic   -- Request To send
388
  );
389 141 davidgb
end component;
390
 
391
-----------------------------------------------------------------
392
--
393
-- ACIA Clock divider
394
--
395
-----------------------------------------------------------------
396
 
397
component ACIA_Clock
398
  generic (
399 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
400
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
401 141 davidgb
  );
402
  port (
403 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
404
    ACIA_clk : out Std_logic   -- ACIA Clock output
405 141 davidgb
  );
406
end component;
407
 
408
----------------------------------------
409
--
410
-- Timer module
411
--
412
----------------------------------------
413
 
414
component timer
415
  port (
416 148 davidgb
    clk       : in std_logic;
417
    rst       : in std_logic;
418
    cs        : in std_logic;
419
    rw        : in std_logic;
420
    addr      : in std_logic;
421
    data_in   : in std_logic_vector(7 downto 0);
422
    data_out  : out std_logic_vector(7 downto 0);
423
    irq       : out std_logic
424
  );
425 141 davidgb
end component;
426
 
427
------------------------------------------------------------
428
--
429
-- Bus Trap logic
430
--
431
------------------------------------------------------------
432
 
433
component trap
434 148 davidgb
  port (
435 141 davidgb
    clk        : in  std_logic;
436
    rst        : in  std_logic;
437
    cs         : in  std_logic;
438
    rw         : in  std_logic;
439
    vma        : in  std_logic;
440
    addr       : in  std_logic_vector(15 downto 0);
441
    data_in    : in  std_logic_vector(7 downto 0);
442
    data_out   : out std_logic_vector(7 downto 0);
443
    irq        : out std_logic
444
  );
445
end component;
446
 
447
----------------------------------------
448
--
449
-- Dynamic Address Translation Registers
450
--
451
----------------------------------------
452 148 davidgb
 
453 141 davidgb
component dat_ram
454
  port (
455
    clk      : in  std_logic;
456
    rst      : in  std_logic;
457
    cs       : in  std_logic;
458
    rw       : in  std_logic;
459
    addr_lo  : in  std_logic_vector(3 downto 0);
460
    addr_hi  : in  std_logic_vector(3 downto 0);
461
    data_in  : in  std_logic_vector(7 downto 0);
462
    data_out : out std_logic_vector(7 downto 0)
463
  );
464
end component;
465 185 davidgb
 
466 141 davidgb
--
467
-- Clock buffer
468
--
469 148 davidgb
 
470 141 davidgb
component BUFG
471
   Port (
472
     i: in std_logic;
473
     o: out std_logic
474
  );
475
end component;
476
 
477 185 davidgb
begin
478 169 davidgb
 
479 186 davidgb
  --
480
  -- pushbutton debounce
481
  --
482
  my_singlestep: btn_debounce
483
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
484 185 davidgb
 
485 186 davidgb
  RESET_N     <= pbtn(3); -- Right PB
486
  NMI_N       <= pbtn(4); -- Center PB
487
  SINGLE_STEP <= pbtn(1); -- Left PB
488
 
489
  --
490
  -- Generate CPU & Pixel Clock from Memory Clock
491
  --
492
  NORMAL: if CLOCK_MODE = 0 generate
493
    my_prescaler : process( clk_i, clk_count )
494
    begin
495
      if rising_edge( clk_i ) then
496
        if clk_count = 0 then
497
          clk_count <= CPU_CLK_DIV-1;
498
        else
499
          clk_count <= clk_count - 1;
500
        end if;
501
        if clk_count = 0 then
502
           clk25 <= '0';
503
        elsif clk_count = (CPU_CLK_DIV/2) then
504
           clk25 <= '1';
505
        end if;
506
      end if;
507
    end process;
508
  end generate;
509
  SS: if CLOCK_MODE = 1 generate
510
    clk25 <= SINGLE_STEP;
511
  end generate;
512
 
513
  --
514
  -- Reset button and reset timer
515
  --
516
  my_switch_assignments : process( rst_i, RESET_N)
517
  begin
518
    rst_i <= RESET_N;
519
    cpu_reset <= rst_i;
520
  end process;
521 185 davidgb
 
522 186 davidgb
  clk_i <= CLKA;
523
 
524 141 davidgb
  -----------------------------------------------------------------------------
525
  -- Instantiation of internal components
526
  -----------------------------------------------------------------------------
527
 
528 148 davidgb
  my_cpu : cpu09
529
    port map (
530
      clk       => cpu_clk,
531
      rst       => cpu_reset,
532
      vma       => cpu_vma,
533
      addr      => cpu_addr(15 downto 0),
534
      rw        => cpu_rw,
535
      data_out  => cpu_data_out,
536
      data_in   => cpu_data_in,
537
      irq       => cpu_irq,
538
      firq      => cpu_firq,
539
      nmi       => cpu_nmi,
540
      halt      => cpu_halt,
541
      hold      => cpu_hold
542
    );
543 141 davidgb
 
544 148 davidgb
  my_rom : mon_rom
545
    port map (
546
      clk   => cpu_clk,
547
      rst   => cpu_reset,
548
      cs    => rom_cs,
549
      rw    => '1',
550
      addr  => cpu_addr(11 downto 0),
551
      data_in => cpu_data_out,
552
      data_out => rom_data_out
553 141 davidgb
    );
554
 
555 148 davidgb
  my_flex : flex_ram
556
    port map (
557
      clk       => cpu_clk,
558
      rst       => cpu_reset,
559
      cs        => flex_cs,
560
      rw        => cpu_rw,
561
      addr      => cpu_addr(12 downto 0),
562
      data_out     => flex_data_out,
563
      data_in     => cpu_data_out
564 170 davidgb
    );
565
 
566
  my_32k : ram_32k
567
    port map (
568
      clk       => cpu_clk,
569
      rst       => cpu_reset,
570 173 davidgb
      cs        => ram1_cs,
571 170 davidgb
      rw        => cpu_rw,
572
      addr      => cpu_addr(14 downto 0),
573 173 davidgb
      data_out     => ram1_data_out,
574 170 davidgb
      data_in     => cpu_data_out
575
    );
576 173 davidgb
 
577
  my_16k : ram_16k
578
    port map (
579
      clk       => cpu_clk,
580
      rst       => cpu_reset,
581
      cs        => ram2_cs,
582
      rw        => cpu_rw,
583
      addr      => cpu_addr(13 downto 0),
584
      data_out     => ram2_data_out,
585
      data_in     => cpu_data_out
586
    );
587
 
588 148 davidgb
  my_acia  : acia6850
589
    port map (
590
      clk       => cpu_clk,
591
      rst       => cpu_reset,
592
      cs        => acia_cs,
593
      rw        => cpu_rw,
594
      addr      => cpu_addr(0),
595
      data_in   => cpu_data_out,
596
      data_out  => acia_data_out,
597
      irq       => acia_irq,
598
      RxC       => acia_clk,
599
      TxC       => acia_clk,
600 186 davidgb
      RxD       => RS232_RXD,
601
      TxD       => RS232_TXD,
602 148 davidgb
      DCD_n     => dcd_n,
603 186 davidgb
      CTS_n     => RS232_CTS,
604
      RTS_n     => RS232_RTS
605 141 davidgb
    );
606 186 davidgb
  dcd_n <= '0';
607
 
608 148 davidgb
  my_ACIA_Clock : ACIA_Clock
609
    generic map(
610 185 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
611 148 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
612
    )
613
    port map(
614
      clk        => Clk_i,
615
      acia_clk   => acia_clk
616
    );
617 141 davidgb
 
618 148 davidgb
  ----------------------------------------
619
  --
620
  -- Timer Module
621
  --
622
  ----------------------------------------
623
  my_timer  : timer
624
    port map (
625
      clk       => cpu_clk,
626
      rst       => cpu_reset,
627
      cs        => timer_cs,
628
      rw        => cpu_rw,
629
      addr      => cpu_addr(0),
630
      data_in   => cpu_data_out,
631
      data_out  => timer_data_out,
632
      irq       => timer_irq
633
    );
634 141 davidgb
 
635 148 davidgb
  ----------------------------------------
636
  --
637
  -- Bus Trap Interrupt logic
638
  --
639
  ----------------------------------------
640
  my_trap : trap
641
    port map (
642
      clk        => cpu_clk,
643
      rst        => cpu_reset,
644
      cs         => trap_cs,
645
      rw         => cpu_rw,
646
      vma        => cpu_vma,
647
      addr       => cpu_addr,
648
      data_in    => cpu_data_out,
649
      data_out   => trap_data_out,
650
      irq        => trap_irq
651 141 davidgb
    );
652
 
653 148 davidgb
  my_dat : dat_ram
654
    port map (
655
      clk       => cpu_clk,
656
      rst       => cpu_reset,
657
      cs        => dat_cs,
658
      rw        => cpu_rw,
659
      addr_hi   => cpu_addr(15 downto 12),
660
      addr_lo   => cpu_addr(3 downto 0),
661
      data_in   => cpu_data_out,
662
      data_out  => dat_addr(7 downto 0)
663 141 davidgb
    );
664
 
665 148 davidgb
  cpu_clk_buffer : BUFG
666 141 davidgb
    port map(
667 148 davidgb
      i => Clk25,
668
      o => cpu_clk
669 141 davidgb
    );
670 162 davidgb
 
671 148 davidgb
  ----------------------------------------------------------------------
672
  --
673
  -- Process to decode memory map
674
  --
675
  ----------------------------------------------------------------------
676 141 davidgb
 
677 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
678 141 davidgb
                     dat_addr,
679
                     rom_data_out,
680
                     flex_data_out,
681
                     acia_data_out,
682
                     timer_data_out,
683
                     trap_data_out,
684 173 davidgb
                     ram1_data_out, ram2_data_out
685 141 davidgb
                     )
686 148 davidgb
  begin
687
    cpu_data_in <= (others=>'0');
688
    dat_cs      <= '0';
689
    rom_cs      <= '0';
690
    flex_cs     <= '0';
691
    acia_cs     <= '0';
692
    timer_cs    <= '0';
693
    trap_cs     <= '0';
694 173 davidgb
    ram1_cs      <= '0';
695
    ram2_cs      <= '0';
696
 
697 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
698
      cpu_data_in <= rom_data_out;
699
      dat_cs      <= cpu_vma;              -- write DAT
700
      rom_cs      <= cpu_vma;              -- read  ROM
701 141 davidgb
 
702 148 davidgb
    --
703
    -- Sys09Bug Monitor ROM $F000 - $FFFF
704
    --
705
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
706
      cpu_data_in <= rom_data_out;
707
      rom_cs      <= cpu_vma;
708 141 davidgb
 
709 148 davidgb
    --
710
    -- IO Devices $E000 - $E7FF
711
    --
712
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
713
      case cpu_addr(11 downto 8) is
714
        --
715
        -- SWTPC peripherals from $E000 to $E0FF
716
        --
717
        when "0000" =>
718
          case cpu_addr(7 downto 4) is
719
          --
720
          -- Console Port ACIA $E000 - $E00F
721
          --
722
            when "0000" => -- $E000
723
              cpu_data_in <= acia_data_out;
724
              acia_cs     <= cpu_vma;
725 141 davidgb
 
726 148 davidgb
            --
727
            -- Reserved
728
            -- Floppy Disk Controller port $E010 - $E01F
729
            --
730 141 davidgb
 
731 148 davidgb
            --
732
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
733
            --
734
            when "0100" => -- $E040
735
              cpu_data_in <= (others=> '0');
736 141 davidgb
 
737 148 davidgb
            --
738
            -- Timer $E050 - $E05F
739
            --
740
            when "0101" => -- $E050
741
              cpu_data_in <= timer_data_out;
742
              timer_cs    <= cpu_vma;
743 141 davidgb
 
744 148 davidgb
            --
745
            -- Bus Trap Logic $E060 - $E06F
746
            --
747
            when "0110" => -- $E060
748
              cpu_data_in <= trap_data_out;
749
              trap_cs     <= cpu_vma;
750 141 davidgb
 
751 148 davidgb
            --
752
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
753
            --
754
 
755
            --
756
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
757
            --
758
 
759
            --
760
            -- Remaining 6 slots reserved for non SWTPc Peripherals
761
            --
762
            when others => -- $E0A0 to $E0FF
763
              null;
764
          end case;
765
 
766
        --
767
        -- $E200 to $EFFF reserved for future use
768
        --
769
        when others =>
770 141 davidgb
           null;
771 148 davidgb
      end case;
772 141 davidgb
 
773 148 davidgb
    --
774
    -- Flex RAM $0C000 - $0DFFF
775
    --
776
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
777
      cpu_data_in <= flex_data_out;
778
      flex_cs     <= cpu_vma;
779 170 davidgb
 
780
    --
781
    -- 32k RAM $00000 - $07FFF
782
    --
783
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
784 173 davidgb
      cpu_data_in <= ram1_data_out;
785
      ram1_cs     <= cpu_vma;
786
 
787
    --
788
    -- 16k RAM $08000 - $0BFFF
789
    --
790
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
791
      cpu_data_in <= ram2_data_out;
792
      ram2_cs     <= cpu_vma;
793 141 davidgb
 
794 148 davidgb
    --
795
    -- Everything else is RAM
796
    --
797 141 davidgb
    else
798 173 davidgb
      cpu_data_in <= (others => '0');
799
      ram3_cs      <= cpu_vma;
800 141 davidgb
    end if;
801
 
802 148 davidgb
  end process;
803 141 davidgb
 
804 148 davidgb
  --
805
  -- Interrupts and other bus control signals
806
  --
807 186 davidgb
  interrupts : process( NMI_N,
808 141 davidgb
                      acia_irq,
809
                      trap_irq,
810
                      timer_irq
811
                      )
812 148 davidgb
  begin
813 162 davidgb
    cpu_irq    <= acia_irq;
814 186 davidgb
    cpu_nmi    <= trap_irq or not( NMI_N );
815 141 davidgb
    cpu_firq   <= timer_irq;
816
    cpu_halt   <= '0';
817 170 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
818 148 davidgb
  end process;
819 141 davidgb
 
820 148 davidgb
  --
821 185 davidgb
  -- Flash 7 segment LEDS
822 148 davidgb
  --
823 185 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
824 148 davidgb
  begin
825 185 davidgb
    if rst_i = '1' then
826
         CountL <= "000000000000000000000000";
827
    elsif rising_edge(clk_i) then
828
         CountL <= CountL + 1;
829 141 davidgb
    end if;
830 185 davidgb
    --S(7 downto 0) <= CountL(23 downto 16);
831
  end process;
832 141 davidgb
 
833 185 davidgb
 
834 141 davidgb
 
835
 
836 185 davidgb
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
837
  begin
838
    S(7) <= '0';
839
    S(6) <= cpu_rw;
840
         S(5) <= cpu_vma;
841
         S(4) <= '0';
842
    case sw is
843
         when "00000000" =>
844
           S(3 downto 0) <= cpu_addr(3 downto 0);
845
    when "00000001" =>
846
           S(3 downto 0) <= cpu_addr(7 downto 4);
847
         when "00000010" =>
848
           S(3 downto 0) <= cpu_addr(11 downto 8);
849
    when "00000011" =>
850
           S(3 downto 0) <= cpu_addr(15 downto 12);
851
    when "00000100" =>
852
           S(3 downto 0) <= cpu_data_in(3 downto 0);
853
    when "00000101" =>
854
           S(3 downto 0) <= cpu_data_in(7 downto 4);
855
    when others => S(3 downto 0) <= (others => '0');
856
         end case;
857
  end process;
858
 
859 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
860 141 davidgb
--                      cpu_halt, cpu_hold,
861
--                      cpu_firq, cpu_irq, cpu_nmi,
862
--                      cpu_addr, cpu_data_out, cpu_data_in )
863 148 davidgb
--  begin
864
--    cpu_reset_o    <= cpu_reset;
865
--    cpu_clk_o      <= cpu_clk;
866
--    cpu_rw_o       <= cpu_rw;
867
--    cpu_vma_o      <= cpu_vma;
868
--    cpu_halt_o     <= cpu_halt;
869
--    cpu_hold_o     <= cpu_hold;
870
--    cpu_firq_o     <= cpu_firq;
871
--    cpu_irq_o      <= cpu_irq;
872
--    cpu_nmi_o      <= cpu_nmi;
873
--    cpu_addr_o     <= cpu_addr;
874
--    cpu_data_out_o <= cpu_data_out;
875
--    cpu_data_in_o  <= cpu_data_in;
876
--  end process;
877 141 davidgb
 
878
end rtl; --===================== End of architecture =======================--
879
 

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