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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Blame information for rev 187

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1 165 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8 187 davidgb
-- File name      : system09.vhd
9 165 davidgb
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11 187 davidgb
--                  Designed with Digilent Zybo Z20.
12
-- ==========================================================================
13
-- Setup/Buttons
14
--    RS232 - connect a RS-232 Pmod to JE (upper row)
15
--    Configure terminal for 57600 baud 8-N-1, hardware handshake
16
--
17
-- Slide Switches - selects the nibble to display on the 4 LEDs
18
--    0000 - CPU Address 3 to 0
19
--    0001 - CPU Address 7 to 4
20
--    0010 - CPU Address 11 to 8
21
--    0011 - CPU Address 15 to 12
22
--    0100 - CPU Data 3 to 0
23
--    0101 - CPU Data 7 to 4
24
--
25
-- Push buttons
26
--     BTN3     BTN2     BTN1     BTN0
27
--    (unused)  Single   NMI      RESET
28
--              Step
29
--
30
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
31
--
32
-- Memory Map     :
33 165 davidgb
--
34 187 davidgb
-- $0000 - User program RAM (32K Bytes)
35
-- $8000 - User program RAM (16K Bytes)
36
-- $C000 - Flex Operating System memory (8K Bytes)
37
-- $E000 - ACIA (SWTPc)
38
-- $E050 - Timer
39
-- $E060 - Bus trap
40
-- $F000 - Sys09Bug monitor Program (4K Bytes)
41
-- ==========================================================================
42
--
43 165 davidgb
-- Dependencies   : ieee.Std_Logic_1164
44
--                  ieee.std_logic_unsigned
45
--                  ieee.std_logic_arith
46
--                  ieee.numeric_std
47
--                  unisim.vcomponents
48
--
49 187 davidgb
-- Uses           : mon_rom    (sys09swt.vhd)         SWTPc S-Bug 1.7 Monitor ROM 
50
--                  cpu09      (cpu09.vhd)            CPU core
51
--                  ACIA_6850  (acia6850.vhd)         ACIA / UART
52
--                  ACIA_Clock (ACIA_Clock.vhd)       ACIA clock.
53 165 davidgb
--                  timer      (timer.vhd)            Interrupt timer
54
--                  trap       (trap.vhd)             Bus condition trap logic
55 187 davidgb
--                  flex_ram   (flex9ram.vhd)         Flex operating system
56
--                  ram_16K    (ram16k_b16.vhd)       32 KBytes of Block RAM
57 165 davidgb
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
58
--                  
59
--===========================================================================----
60
--
61
-- Revision History:
62
--===========================================================================--
63 187 davidgb
-- Version 0.1 - Jan 20, 2021
64
--    Copied from the System09_Xess-XSA3S1000 vhdl
65 165 davidgb
--===========================================================================--
66
library ieee;
67
   use ieee.std_logic_1164.all;
68
   use IEEE.STD_LOGIC_ARITH.ALL;
69
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
70
   use ieee.numeric_std.all;
71
library work;
72
   use work.common.all;
73
library unisim;
74
   use unisim.vcomponents.all;
75
 
76
entity system09 is
77
  port(
78 187 davidgb
    CLKA         : in  Std_Logic;  -- 125 MHz Clock input
79 165 davidgb
 
80 177 davidgb
    -- RS232 Port
81 187 davidgb
    RS232_RTS    : out std_logic;
82
         RS232_CTS    : in  std_logic;
83
    RS232_RXD    : in  Std_Logic;
84
    RS232_TXD    : out Std_Logic;
85 165 davidgb
 
86 187 davidgb
    -- slide switches
87
         sw           : in std_logic_vector(3 downto 0);
88
         -- push buttons [Unused, Single-Step, NMI, RESET]
89
         btn          : in std_logic_vector(3 downto 0);
90
    -- Status 4 LEDs
91
    led          : out std_logic_vector(3 downto 0)
92 165 davidgb
  );
93
end system09;
94
 
95
-------------------------------------------------------------------------------
96
-- Architecture for System09
97
-------------------------------------------------------------------------------
98
architecture rtl of system09 is
99
 
100
  -----------------------------------------------------------------------------
101
  -- constants
102
  -----------------------------------------------------------------------------
103 187 davidgb
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
104
 
105
  constant SYS_CLK_FREQ         : natural := 125_000_000;  -- FPGA System Clock (in Hz)
106 165 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
107
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
108
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
109
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
110
 
111
  -----------------------------------------------------------------------------
112
  -- Signals
113 177 davidgb
  -----------------------------------------------------------------------------
114 187 davidgb
  signal pbtn           : std_logic_vector(3 downto 0);
115
  signal NMI_N          : std_logic;
116
  signal RESET_N        : std_logic;
117
  signal SINGLE_STEP    : std_logic;
118
 
119 165 davidgb
  -- BOOT ROM
120
  signal rom_cs         : Std_logic;
121
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
122
 
123
  -- Flex Memory & Monitor Stack
124
  signal flex_cs        : Std_logic;
125
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
126
 
127
  -- ACIA/UART Interface signals
128
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
129
  signal acia_cs        : Std_Logic;
130
  signal acia_irq       : Std_Logic;
131
  signal acia_clk       : Std_Logic;
132
  signal rxd            : Std_Logic;
133
  signal txd            : Std_Logic;
134
  signal DCD_n          : Std_Logic;
135
  signal RTS_n          : Std_Logic;
136
  signal CTS_n          : Std_Logic;
137
 
138
  -- RAM
139 177 davidgb
  signal ram1_cs         : std_logic;
140
  signal ram1_data_out   : std_logic_vector(7 downto 0);
141
  signal ram2_cs         : std_logic;
142
  signal ram2_data_out   : std_logic_vector(7 downto 0);
143
  signal ram3_cs         : std_logic;
144 165 davidgb
 
145
  -- CPU Interface signals
146
  signal cpu_reset      : Std_Logic;
147
  signal cpu_clk        : Std_Logic;
148
  signal cpu_rw         : std_logic;
149
  signal cpu_vma        : std_logic;
150
  signal cpu_halt       : std_logic;
151
  signal cpu_hold       : std_logic;
152
  signal cpu_firq       : std_logic;
153
  signal cpu_irq        : std_logic;
154
  signal cpu_nmi        : std_logic;
155
  signal cpu_addr       : std_logic_vector(15 downto 0);
156
  signal cpu_data_in    : std_logic_vector(7 downto 0);
157
  signal cpu_data_out   : std_logic_vector(7 downto 0);
158
 
159
  -- Dynamic Address Translation
160
  signal dat_cs       : std_logic;
161
  signal dat_addr     : std_logic_vector(7 downto 0);
162
 
163
  -- timer
164
  signal timer_data_out : std_logic_vector(7 downto 0);
165
  signal timer_cs       : std_logic;
166
  signal timer_irq      : std_logic;
167
 
168
  -- trap
169
  signal trap_cs        : std_logic;
170
  signal trap_data_out  : std_logic_vector(7 downto 0);
171
  signal trap_irq       : std_logic;
172
 
173
  signal rst_i         : std_logic;     -- internal reset signal
174 187 davidgb
  signal clk_i         : std_logic;     -- internal master clock signal
175 165 davidgb
 
176 187 davidgb
  signal CountL        : std_logic_vector(23 downto 0);
177 165 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
178
  signal Clk25         : std_logic;
179 187 davidgb
 
180
 
181
component btn_debounce
182
    Port ( BTN_I : in  STD_LOGIC_VECTOR (3 downto 0);
183
           CLK : in  STD_LOGIC;
184
           BTN_O : out  STD_LOGIC_VECTOR (3 downto 0));
185
end component;
186
 
187 165 davidgb
 
188
-----------------------------------------------------------------
189
--
190
-- CPU09 CPU core
191
--
192
-----------------------------------------------------------------
193
 
194
component cpu09
195
  port (
196
    clk:      in  std_logic;
197
    rst:      in  std_logic;
198
    vma:      out std_logic;
199
    addr:     out std_logic_vector(15 downto 0);
200
    rw:       out std_logic;     -- Asynchronous memory interface
201
    data_out: out std_logic_vector(7 downto 0);
202
    data_in:  in  std_logic_vector(7 downto 0);
203
    irq:      in  std_logic;
204
    firq:     in  std_logic;
205
    nmi:      in  std_logic;
206
    halt:     in  std_logic;
207
    hold:     in  std_logic
208
  );
209
end component;
210
 
211
----------------------------------------
212
--
213
-- 4K Block RAM Monitor ROM
214
-- $F000 - $FFFF
215
--
216
----------------------------------------
217
 
218
component mon_rom
219
  Port (
220
    clk   : in  std_logic;
221
    rst   : in  std_logic;
222
    cs    : in  std_logic;
223
    rw    : in  std_logic;
224
    addr  : in  std_logic_vector (11 downto 0);
225
    data_out : out std_logic_vector (7 downto 0);
226
    data_in : in  std_logic_vector (7 downto 0)
227
  );
228
end component;
229
 
230
----------------------------------------
231
--
232
-- 8KBytes Block RAM for FLEX9
233
-- $C000 - $DFFF
234
--
235
----------------------------------------
236
 
237
component flex_ram
238
  Port (
239
    clk      : in  std_logic;
240
    rst      : in  std_logic;
241
    cs       : in  std_logic;
242
    rw       : in  std_logic;
243
    addr     : in  std_logic_vector (12 downto 0);
244
    data_out    : out std_logic_vector (7 downto 0);
245
    data_in    : in  std_logic_vector (7 downto 0)
246
  );
247
end component;
248 177 davidgb
 
249
----------------------------------------
250
--
251
-- 32KBytes Block RAM 0000
252
-- $0000 - $7FFF
253
--
254
----------------------------------------
255 165 davidgb
 
256 177 davidgb
component ram_32k
257
  Port (
258
    clk      : in  std_logic;
259
    rst      : in  std_logic;
260
    cs       : in  std_logic;
261
    rw       : in  std_logic;
262
    addr     : in  std_logic_vector (14 downto 0);
263
    data_out    : out std_logic_vector (7 downto 0);
264
    data_in    : in  std_logic_vector (7 downto 0)
265
  );
266
end component;
267
 
268
 
269
----------------------------------------
270
--
271
-- 16KBytes Block RAM 8000
272
-- $8000 - $BFFF
273
--
274
----------------------------------------
275
 
276
component ram_16k
277
  Port (
278
    clk      : in  std_logic;
279
    rst      : in  std_logic;
280
    cs       : in  std_logic;
281
    rw       : in  std_logic;
282
    addr     : in  std_logic_vector (13 downto 0);
283
    data_out    : out std_logic_vector (7 downto 0);
284
    data_in    : in  std_logic_vector (7 downto 0)
285
  );
286
end component;
287
 
288 165 davidgb
-----------------------------------------------------------------
289
--
290
-- 6850 Compatible ACIA / UART
291
--
292
-----------------------------------------------------------------
293
 
294
component acia6850
295
  port (
296
    clk      : in  Std_Logic;  -- System Clock
297
    rst      : in  Std_Logic;  -- Reset input (active high)
298
    cs       : in  Std_Logic;  -- miniUART Chip Select
299
    rw       : in  Std_Logic;  -- Read / Not Write
300
    addr     : in  Std_Logic;  -- Register Select
301
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
302
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
303
    irq      : out Std_Logic;  -- Interrupt
304
    RxC      : in  Std_Logic;  -- Receive Baud Clock
305
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
306
    RxD      : in  Std_Logic;  -- Receive Data
307
    TxD      : out Std_Logic;  -- Transmit Data
308
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
309
    CTS_n    : in  Std_Logic;  -- Clear To Send
310
    RTS_n    : out Std_Logic   -- Request To send
311
  );
312
end component;
313
 
314
-----------------------------------------------------------------
315
--
316
-- ACIA Clock divider
317
--
318
-----------------------------------------------------------------
319
 
320
component ACIA_Clock
321
  generic (
322
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
323
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
324
  );
325
  port (
326
    clk      : in  Std_Logic;  -- System Clock Input
327
    ACIA_clk : out Std_logic   -- ACIA Clock output
328
  );
329
end component;
330
 
331
----------------------------------------
332
--
333
-- Timer module
334
--
335
----------------------------------------
336
 
337
component timer
338
  port (
339
    clk       : in std_logic;
340
    rst       : in std_logic;
341
    cs        : in std_logic;
342
    rw        : in std_logic;
343
    addr      : in std_logic;
344
    data_in   : in std_logic_vector(7 downto 0);
345
    data_out  : out std_logic_vector(7 downto 0);
346
    irq       : out std_logic
347
  );
348
end component;
349
 
350
------------------------------------------------------------
351
--
352
-- Bus Trap logic
353
--
354
------------------------------------------------------------
355
 
356
component trap
357
  port (
358
    clk        : in  std_logic;
359
    rst        : in  std_logic;
360
    cs         : in  std_logic;
361
    rw         : in  std_logic;
362
    vma        : in  std_logic;
363
    addr       : in  std_logic_vector(15 downto 0);
364
    data_in    : in  std_logic_vector(7 downto 0);
365
    data_out   : out std_logic_vector(7 downto 0);
366
    irq        : out std_logic
367
  );
368
end component;
369
 
370
----------------------------------------
371
--
372
-- Dynamic Address Translation Registers
373
--
374
----------------------------------------
375
 
376
component dat_ram
377
  port (
378
    clk      : in  std_logic;
379
    rst      : in  std_logic;
380
    cs       : in  std_logic;
381
    rw       : in  std_logic;
382
    addr_lo  : in  std_logic_vector(3 downto 0);
383
    addr_hi  : in  std_logic_vector(3 downto 0);
384
    data_in  : in  std_logic_vector(7 downto 0);
385
    data_out : out std_logic_vector(7 downto 0)
386
  );
387
end component;
388 187 davidgb
 
389 165 davidgb
--
390
-- Clock buffer
391
--
392
 
393
component BUFG
394
   Port (
395
     i: in std_logic;
396
     o: out std_logic
397
  );
398
end component;
399
 
400 187 davidgb
begin
401 177 davidgb
 
402 187 davidgb
  --
403
  -- pushbutton debounce
404
  --
405
  my_singlestep: btn_debounce
406
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
407
 
408
  RESET_N     <= pbtn(0); -- Right PB
409
  NMI_N       <= pbtn(1); -- Center PB
410
  SINGLE_STEP <= pbtn(2); -- Left PB
411
 
412
  --
413
  -- Generate CPU & Pixel Clock from Memory Clock
414
  --
415
  NORMAL: if CLOCK_MODE = 0 generate
416
    my_prescaler : process( clk_i, clk_count )
417
    begin
418
      if rising_edge( clk_i ) then
419
        if clk_count = 0 then
420
          clk_count <= CPU_CLK_DIV-1;
421
        else
422
          clk_count <= clk_count - 1;
423
        end if;
424
        if clk_count = 0 then
425
           clk25 <= '0';
426
        elsif clk_count = (CPU_CLK_DIV/2) then
427
           clk25 <= '1';
428
        end if;
429
      end if;
430
    end process;
431
  end generate;
432
  SS: if CLOCK_MODE = 1 generate
433
    clk25 <= SINGLE_STEP;
434
  end generate;
435
 
436
  --
437
  -- Reset button and reset timer
438
  --
439
  my_switch_assignments : process( rst_i, RESET_N)
440
  begin
441
    rst_i <= RESET_N;
442
    cpu_reset <= rst_i;
443
  end process;
444
 
445
  clk_i <= CLKA;
446
 
447 165 davidgb
  -----------------------------------------------------------------------------
448
  -- Instantiation of internal components
449
  -----------------------------------------------------------------------------
450
 
451
  my_cpu : cpu09
452
    port map (
453
      clk       => cpu_clk,
454
      rst       => cpu_reset,
455
      vma       => cpu_vma,
456
      addr      => cpu_addr(15 downto 0),
457
      rw        => cpu_rw,
458
      data_out  => cpu_data_out,
459
      data_in   => cpu_data_in,
460
      irq       => cpu_irq,
461
      firq      => cpu_firq,
462
      nmi       => cpu_nmi,
463
      halt      => cpu_halt,
464
      hold      => cpu_hold
465
    );
466
 
467
  my_rom : mon_rom
468
    port map (
469
      clk   => cpu_clk,
470
      rst   => cpu_reset,
471
      cs    => rom_cs,
472
      rw    => '1',
473
      addr  => cpu_addr(11 downto 0),
474
      data_in => cpu_data_out,
475
      data_out => rom_data_out
476
    );
477
 
478
  my_flex : flex_ram
479
    port map (
480
      clk       => cpu_clk,
481
      rst       => cpu_reset,
482
      cs        => flex_cs,
483
      rw        => cpu_rw,
484
      addr      => cpu_addr(12 downto 0),
485
      data_out     => flex_data_out,
486
      data_in     => cpu_data_out
487 177 davidgb
    );
488
 
489
  my_32k : ram_32k
490
    port map (
491
      clk       => cpu_clk,
492
      rst       => cpu_reset,
493
      cs        => ram1_cs,
494
      rw        => cpu_rw,
495
      addr      => cpu_addr(14 downto 0),
496
      data_out     => ram1_data_out,
497
      data_in     => cpu_data_out
498
    );
499
 
500
  my_16k : ram_16k
501
    port map (
502
      clk       => cpu_clk,
503
      rst       => cpu_reset,
504
      cs        => ram2_cs,
505
      rw        => cpu_rw,
506
      addr      => cpu_addr(13 downto 0),
507
      data_out     => ram2_data_out,
508
      data_in     => cpu_data_out
509
    );
510
 
511 165 davidgb
  my_acia  : acia6850
512
    port map (
513
      clk       => cpu_clk,
514
      rst       => cpu_reset,
515
      cs        => acia_cs,
516
      rw        => cpu_rw,
517
      addr      => cpu_addr(0),
518
      data_in   => cpu_data_out,
519
      data_out  => acia_data_out,
520
      irq       => acia_irq,
521
      RxC       => acia_clk,
522
      TxC       => acia_clk,
523 187 davidgb
      RxD       => RS232_RXD,
524
      TxD       => RS232_TXD,
525 165 davidgb
      DCD_n     => dcd_n,
526 187 davidgb
      CTS_n     => RS232_CTS,
527
      RTS_n     => RS232_RTS
528 165 davidgb
    );
529 187 davidgb
  dcd_n <= '0';
530
 
531 165 davidgb
  my_ACIA_Clock : ACIA_Clock
532
    generic map(
533 187 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
534 165 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
535
    )
536
    port map(
537
      clk        => Clk_i,
538
      acia_clk   => acia_clk
539
    );
540
 
541
  ----------------------------------------
542
  --
543
  -- Timer Module
544
  --
545
  ----------------------------------------
546
  my_timer  : timer
547
    port map (
548
      clk       => cpu_clk,
549
      rst       => cpu_reset,
550
      cs        => timer_cs,
551
      rw        => cpu_rw,
552
      addr      => cpu_addr(0),
553
      data_in   => cpu_data_out,
554
      data_out  => timer_data_out,
555
      irq       => timer_irq
556
    );
557
 
558
  ----------------------------------------
559
  --
560
  -- Bus Trap Interrupt logic
561
  --
562
  ----------------------------------------
563
  my_trap : trap
564
    port map (
565
      clk        => cpu_clk,
566
      rst        => cpu_reset,
567
      cs         => trap_cs,
568
      rw         => cpu_rw,
569
      vma        => cpu_vma,
570
      addr       => cpu_addr,
571
      data_in    => cpu_data_out,
572
      data_out   => trap_data_out,
573
      irq        => trap_irq
574
    );
575
 
576
  my_dat : dat_ram
577
    port map (
578
      clk       => cpu_clk,
579
      rst       => cpu_reset,
580
      cs        => dat_cs,
581
      rw        => cpu_rw,
582
      addr_hi   => cpu_addr(15 downto 12),
583
      addr_lo   => cpu_addr(3 downto 0),
584
      data_in   => cpu_data_out,
585
      data_out  => dat_addr(7 downto 0)
586
    );
587
 
588
  cpu_clk_buffer : BUFG
589
    port map(
590
      i => Clk25,
591
      o => cpu_clk
592
    );
593
 
594
  ----------------------------------------------------------------------
595
  --
596
  -- Process to decode memory map
597
  --
598
  ----------------------------------------------------------------------
599
 
600
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
601
                     dat_addr,
602
                     rom_data_out,
603
                     flex_data_out,
604
                     acia_data_out,
605
                     timer_data_out,
606
                     trap_data_out,
607 177 davidgb
                     ram1_data_out, ram2_data_out
608 165 davidgb
                     )
609
  begin
610
    cpu_data_in <= (others=>'0');
611
    dat_cs      <= '0';
612
    rom_cs      <= '0';
613
    flex_cs     <= '0';
614
    acia_cs     <= '0';
615
    timer_cs    <= '0';
616
    trap_cs     <= '0';
617 177 davidgb
    ram1_cs      <= '0';
618
    ram2_cs      <= '0';
619
 
620 165 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
621
      cpu_data_in <= rom_data_out;
622
      dat_cs      <= cpu_vma;              -- write DAT
623
      rom_cs      <= cpu_vma;              -- read  ROM
624
 
625
    --
626
    -- Sys09Bug Monitor ROM $F000 - $FFFF
627
    --
628
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
629
      cpu_data_in <= rom_data_out;
630
      rom_cs      <= cpu_vma;
631
 
632
    --
633
    -- IO Devices $E000 - $E7FF
634
    --
635
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
636
      case cpu_addr(11 downto 8) is
637
        --
638
        -- SWTPC peripherals from $E000 to $E0FF
639
        --
640
        when "0000" =>
641
          case cpu_addr(7 downto 4) is
642
          --
643
          -- Console Port ACIA $E000 - $E00F
644
          --
645
            when "0000" => -- $E000
646
              cpu_data_in <= acia_data_out;
647
              acia_cs     <= cpu_vma;
648
 
649
            --
650
            -- Reserved
651
            -- Floppy Disk Controller port $E010 - $E01F
652
            --
653
 
654
            --
655
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
656
            --
657
            when "0100" => -- $E040
658
              cpu_data_in <= (others=> '0');
659
 
660
            --
661
            -- Timer $E050 - $E05F
662
            --
663
            when "0101" => -- $E050
664
              cpu_data_in <= timer_data_out;
665
              timer_cs    <= cpu_vma;
666
 
667
            --
668
            -- Bus Trap Logic $E060 - $E06F
669
            --
670
            when "0110" => -- $E060
671
              cpu_data_in <= trap_data_out;
672
              trap_cs     <= cpu_vma;
673
 
674
            --
675
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
676
            --
677
 
678
            --
679
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
680
            --
681
 
682
            --
683
            -- Remaining 6 slots reserved for non SWTPc Peripherals
684
            --
685
            when others => -- $E0A0 to $E0FF
686
              null;
687
          end case;
688
 
689
        --
690
        -- $E200 to $EFFF reserved for future use
691
        --
692
        when others =>
693
           null;
694
      end case;
695
 
696
    --
697
    -- Flex RAM $0C000 - $0DFFF
698
    --
699
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
700
      cpu_data_in <= flex_data_out;
701
      flex_cs     <= cpu_vma;
702 177 davidgb
 
703
    --
704
    -- 32k RAM $00000 - $07FFF
705
    --
706
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
707
      cpu_data_in <= ram1_data_out;
708
      ram1_cs     <= cpu_vma;
709
 
710
    --
711
    -- 16k RAM $08000 - $0BFFF
712
    --
713
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
714
      cpu_data_in <= ram2_data_out;
715
      ram2_cs     <= cpu_vma;
716 165 davidgb
 
717
    --
718
    -- Everything else is RAM
719
    --
720
    else
721 177 davidgb
      cpu_data_in <= (others => '0');
722
      ram3_cs      <= cpu_vma;
723 165 davidgb
    end if;
724
 
725
  end process;
726
 
727
  --
728
  -- Interrupts and other bus control signals
729
  --
730 177 davidgb
  interrupts : process( NMI_N,
731 165 davidgb
                      acia_irq,
732
                      trap_irq,
733
                      timer_irq
734
                      )
735
  begin
736
    cpu_irq    <= acia_irq;
737 177 davidgb
    cpu_nmi    <= trap_irq or not( NMI_N );
738 165 davidgb
    cpu_firq   <= timer_irq;
739
    cpu_halt   <= '0';
740 177 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
741 165 davidgb
  end process;
742
 
743
  --
744 187 davidgb
  -- Flash 7 segment LEDS
745 165 davidgb
  --
746 187 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
747 165 davidgb
  begin
748 187 davidgb
    if rst_i = '1' then
749
         CountL <= "000000000000000000000000";
750
    elsif rising_edge(clk_i) then
751
         CountL <= CountL + 1;
752 165 davidgb
    end if;
753 187 davidgb
    --S(7 downto 0) <= CountL(23 downto 16);
754 165 davidgb
  end process;
755
 
756 187 davidgb
 
757
 
758
 
759
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
760
  begin
761
    case sw is
762
         when "0000" =>
763
           led(3 downto 0) <= cpu_addr(3 downto 0);
764
    when "0001" =>
765
           led(3 downto 0) <= cpu_addr(7 downto 4);
766
         when "0010" =>
767
           led(3 downto 0) <= cpu_addr(11 downto 8);
768
    when "0011" =>
769
           led(3 downto 0) <= cpu_addr(15 downto 12);
770
    when "0100" =>
771
           led(3 downto 0) <= cpu_data_in(3 downto 0);
772
    when "0101" =>
773
           led(3 downto 0) <= cpu_data_in(7 downto 4);
774
    when others => led(3 downto 0) <= (others => '0');
775
         end case;
776 165 davidgb
  end process;
777
 
778
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
779
--                      cpu_halt, cpu_hold,
780
--                      cpu_firq, cpu_irq, cpu_nmi,
781
--                      cpu_addr, cpu_data_out, cpu_data_in )
782
--  begin
783
--    cpu_reset_o    <= cpu_reset;
784
--    cpu_clk_o      <= cpu_clk;
785
--    cpu_rw_o       <= cpu_rw;
786
--    cpu_vma_o      <= cpu_vma;
787
--    cpu_halt_o     <= cpu_halt;
788
--    cpu_hold_o     <= cpu_hold;
789
--    cpu_firq_o     <= cpu_firq;
790
--    cpu_irq_o      <= cpu_irq;
791
--    cpu_nmi_o      <= cpu_nmi;
792
--    cpu_addr_o     <= cpu_addr;
793
--    cpu_data_out_o <= cpu_data_out;
794
--    cpu_data_in_o  <= cpu_data_in;
795
--  end process;
796
 
797
end rtl; --===================== End of architecture =======================--
798
 

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