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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Blame information for rev 199

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--===========================================================================----
--
--  S Y N T H E Z I A B L E    System09 - SOC.
--
--  www.OpenCores.Org - February 2007
--  This core adheres to the GNU public license  
--
-- File name      : system09.vhd
--
-- Purpose        : Top level file for 6809 compatible system on a chip
--                  Designed with Digilent Zybo Z20.
-- ==========================================================================
-- Setup/Buttons
--    RS232 - connect a RS-232 Pmod to JE (upper row)
--    Configure terminal for 57600 baud 8-N-1, hardware handshake
--
-- Slide Switches - selects the nibble to display on the 4 LEDs
--    0000 - CPU Address 3 to 0
--    0001 - CPU Address 7 to 4
--    0010 - CPU Address 11 to 8
--    0011 - CPU Address 15 to 12
--    0100 - CPU Data 3 to 0
--    0101 - CPU Data 7 to 4
--
-- Push buttons
--     BTN3     BTN2     BTN1     BTN0
--    (unused)  Single   NMI      RESET
--              Step
--
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
--
-- Memory Map     :
--
-- $0000 - User program RAM (32K Bytes)
-- $8000 - User program RAM (16K Bytes)
-- $C000 - Flex Operating System memory (8K Bytes)
-- $E000 - ACIA (SWTPc)
-- $E050 - Timer
-- $E060 - Bus trap
-- $F000 - Sys09Bug monitor Program (4K Bytes)
-- ==========================================================================
--
-- Dependencies   : ieee.Std_Logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_arith
--                  ieee.numeric_std
--                  unisim.vcomponents
--
-- Uses           : mon_rom    (sys09swt.vhd)         SWTPc S-Bug 1.7 Monitor ROM 
--                  cpu09      (cpu09.vhd)            CPU core
--                  ACIA_6850  (acia6850.vhd)         ACIA / UART
--                  ACIA_Clock (ACIA_Clock.vhd)       ACIA clock.
--                  timer      (timer.vhd)            Interrupt timer
--                  trap       (trap.vhd)             Bus condition trap logic
--                  flex_ram   (flex9ram.vhd)         Flex operating system
--                  ram_16K    (ram16k_b16.vhd)       32 KBytes of Block RAM
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
--                  
--===========================================================================----
--
-- Revision History:
--===========================================================================--
-- Version 0.1 - Jan 20, 2021
--    Copied from the System09_Xess-XSA3S1000 vhdl
--===========================================================================--
library ieee;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use ieee.numeric_std.all;
library work;
   use work.common.all;
library unisim;
   use unisim.vcomponents.all;
 
entity system09 is
  port(
    CLKA         : in  Std_Logic;  -- 125 MHz Clock input
 
    -- RS232 Port - via Pmod RS232
    RS232_CTS    : in  Std_Logic;
    RS232_RTS    : out Std_Logic;
    RS232_RXD    : in  Std_Logic;
    RS232_TXD    : out Std_Logic;
 
    -- slide switches
         sw           : in std_logic_vector(3 downto 0);
         -- push buttons [Unused, Single-Step, NMI, RESET]
         btn          : in std_logic_vector(3 downto 0);
    -- Status 4 LEDs
    led          : out std_logic_vector(3 downto 0)
  );
end system09;
 
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
architecture rtl of system09 is
 
  -----------------------------------------------------------------------------
  -- constants
  -----------------------------------------------------------------------------
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
 
  constant SYS_CLK_FREQ         : natural := 125_000_000;  -- FPGA System Clock (in Hz)
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
  signal pbtn           : std_logic_vector(3 downto 0);
  signal NMI            : std_logic;
  signal RESET          : std_logic;
  signal SINGLE_STEP    : std_logic;
 
  -- BOOT ROM
  signal rom_cs         : Std_logic;
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
 
  -- Flex Memory & Monitor Stack
  signal flex_cs        : Std_logic;
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
 
  -- ACIA/UART Interface signals
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
  signal acia_cs        : Std_Logic;
  signal acia_irq       : Std_Logic;
  signal acia_clk       : Std_Logic;
  signal RXD            : Std_Logic;
  signal TXD            : Std_Logic;
  signal DCD_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
 
  -- RAM
  signal ram1_cs         : std_logic;
  signal ram1_data_out   : std_logic_vector(7 downto 0);
  signal ram2_cs         : std_logic;
  signal ram2_data_out   : std_logic_vector(7 downto 0);
  signal ram3_cs         : std_logic;
 
  -- CPU Interface signals
  signal cpu_reset      : Std_Logic;
  signal cpu_clk        : Std_Logic;
  signal cpu_rw         : std_logic;
  signal cpu_vma        : std_logic;
  signal cpu_halt       : std_logic;
  signal cpu_hold       : std_logic;
  signal cpu_firq       : std_logic;
  signal cpu_irq        : std_logic;
  signal cpu_nmi        : std_logic;
  signal cpu_addr       : std_logic_vector(15 downto 0);
  signal cpu_data_in    : std_logic_vector(7 downto 0);
  signal cpu_data_out   : std_logic_vector(7 downto 0);
 
  -- Dynamic Address Translation
  signal dat_cs       : std_logic;
  signal dat_addr     : std_logic_vector(7 downto 0);
 
  -- timer
  signal timer_data_out : std_logic_vector(7 downto 0);
  signal timer_cs       : std_logic;
  signal timer_irq      : std_logic;
 
  -- trap
  signal trap_cs        : std_logic;
  signal trap_data_out  : std_logic_vector(7 downto 0);
  signal trap_irq       : std_logic;
 
  signal rst_i         : std_logic;     -- internal reset signal
  signal clk_i         : std_logic;     -- internal master clock signal
 
  signal CountL        : std_logic_vector(25 downto 0);
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal Clk25         : std_logic;
 
 
component btn_debounce
    Port ( BTN_I : in  STD_LOGIC_VECTOR (3 downto 0);
           CLK : in  STD_LOGIC;
           BTN_O : out  STD_LOGIC_VECTOR (3 downto 0));
end component;
 
 
-----------------------------------------------------------------
--
-- CPU09 CPU core
--
-----------------------------------------------------------------
 
component cpu09
  port (
    clk:      in  std_logic;
    rst:      in  std_logic;
    vma:      out std_logic;
    addr:     out std_logic_vector(15 downto 0);
    rw:       out std_logic;     -- Asynchronous memory interface
    data_out: out std_logic_vector(7 downto 0);
    data_in:  in  std_logic_vector(7 downto 0);
    irq:      in  std_logic;
    firq:     in  std_logic;
    nmi:      in  std_logic;
    halt:     in  std_logic;
    hold:     in  std_logic
  );
end component;
 
----------------------------------------
--
-- 4K Block RAM Monitor ROM
-- $F000 - $FFFF
--
----------------------------------------
 
component mon_rom
  Port (
    clk   : in  std_logic;
    rst   : in  std_logic;
    cs    : in  std_logic;
    rw    : in  std_logic;
    addr  : in  std_logic_vector (11 downto 0);
    data_out : out std_logic_vector (7 downto 0);
    data_in : in  std_logic_vector (7 downto 0)
  );
end component;
 
----------------------------------------
--
-- 8KBytes Block RAM for FLEX9
-- $C000 - $DFFF
--
----------------------------------------
 
component flex_ram
  Port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr     : in  std_logic_vector (12 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    data_in    : in  std_logic_vector (7 downto 0)
  );
end component;
 
----------------------------------------
--
-- 32KBytes Block RAM 0000
-- $0000 - $7FFF
--
----------------------------------------
 
component ram_32k
  Port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr     : in  std_logic_vector (14 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    data_in    : in  std_logic_vector (7 downto 0)
  );
end component;
 
 
----------------------------------------
--
-- 16KBytes Block RAM 8000
-- $8000 - $BFFF
--
----------------------------------------
 
component ram_16k
  Port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr     : in  std_logic_vector (13 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    data_in    : in  std_logic_vector (7 downto 0)
  );
end component;
 
-----------------------------------------------------------------
--
-- 6850 Compatible ACIA / UART
--
-----------------------------------------------------------------
 
component acia6850
  port (
    clk      : in  Std_Logic;  -- System Clock
    rst      : in  Std_Logic;  -- Reset input (active high)
    cs       : in  Std_Logic;  -- miniUART Chip Select
    rw       : in  Std_Logic;  -- Read / Not Write
    addr     : in  Std_Logic;  -- Register Select
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
    irq      : out Std_Logic;  -- Interrupt
    RxC      : in  Std_Logic;  -- Receive Baud Clock
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
    RxD      : in  Std_Logic;  -- Receive Data
    TxD      : out Std_Logic;  -- Transmit Data
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
    CTS_n    : in  Std_Logic;  -- Clear To Send
    RTS_n    : out Std_Logic   -- Request To send
  );
end component;
 
-----------------------------------------------------------------
--
-- ACIA Clock divider
--
-----------------------------------------------------------------
 
component ACIA_Clock
  generic (
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
  );
  port (
    clk      : in  Std_Logic;  -- System Clock Input
    ACIA_clk : out Std_logic   -- ACIA Clock output
  );
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component timer
  port (
    clk       : in std_logic;
    rst       : in std_logic;
    cs        : in std_logic;
    rw        : in std_logic;
    addr      : in std_logic;
    data_in   : in std_logic_vector(7 downto 0);
    data_out  : out std_logic_vector(7 downto 0);
    irq       : out std_logic
  );
end component;
 
------------------------------------------------------------
--
-- Bus Trap logic
--
------------------------------------------------------------
 
component trap
  port (
    clk        : in  std_logic;
    rst        : in  std_logic;
    cs         : in  std_logic;
    rw         : in  std_logic;
    vma        : in  std_logic;
    addr       : in  std_logic_vector(15 downto 0);
    data_in    : in  std_logic_vector(7 downto 0);
    data_out   : out std_logic_vector(7 downto 0);
    irq        : out std_logic
  );
end component;
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
 
component dat_ram
  port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr_lo  : in  std_logic_vector(3 downto 0);
    addr_hi  : in  std_logic_vector(3 downto 0);
    data_in  : in  std_logic_vector(7 downto 0);
    data_out : out std_logic_vector(7 downto 0)
  );
end component;
 
--
-- Clock buffer
--
 
component BUFG
   Port (
     i: in std_logic;
     o: out std_logic
  );
end component;
 
begin
 
  --
  -- pushbutton debounce
  --
  my_singlestep: btn_debounce
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
 
  RESET      <= pbtn(0); -- Right PB
  NMI        <= pbtn(1); -- Center PB
 
  --
  -- Generate CPU & Pixel Clock from Memory Clock
  --
 
  my_prescaler : process( clk_i, clk_count )
  begin
    if rising_edge( clk_i ) then
      if clk_count = 0 then
        clk_count <= CPU_CLK_DIV-1;
      else
        clk_count <= clk_count - 1;
      end if;
      if clk_count = 0 then
         clk25 <= '0';
      elsif clk_count = (CPU_CLK_DIV/2) then
         clk25 <= '1';
      end if;
    end if;
  end process;
 
  --
  -- Reset button and reset timer
  --
  my_switch_assignments : process( rst_i, RESET)
  begin
    rst_i <= RESET;
    cpu_reset <= rst_i;
  end process;
 
  clk_i <= CLKA;
 
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
 
  my_cpu : cpu09
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      vma       => cpu_vma,
      addr      => cpu_addr(15 downto 0),
      rw        => cpu_rw,
      data_out  => cpu_data_out,
      data_in   => cpu_data_in,
      irq       => cpu_irq,
      firq      => cpu_firq,
      nmi       => cpu_nmi,
      halt      => cpu_halt,
      hold      => cpu_hold
    );
 
  my_rom : mon_rom
    port map (
      clk   => cpu_clk,
      rst   => cpu_reset,
      cs    => rom_cs,
      rw    => '1',
      addr  => cpu_addr(11 downto 0),
      data_in => cpu_data_out,
      data_out => rom_data_out
    );
 
  my_flex : flex_ram
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => flex_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(12 downto 0),
      data_out     => flex_data_out,
      data_in     => cpu_data_out
    );
 
  my_32k : ram_32k
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => ram1_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(14 downto 0),
      data_out     => ram1_data_out,
      data_in     => cpu_data_out
    );
 
  my_16k : ram_16k
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => ram2_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(13 downto 0),
      data_out     => ram2_data_out,
      data_in     => cpu_data_out
    );
 
  my_acia  : acia6850
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => acia_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(0),
      data_in   => cpu_data_out,
      data_out  => acia_data_out,
      irq       => acia_irq,
      RxC       => acia_clk,
      TxC       => acia_clk,
      RxD       => RXD,
      TxD       => TXD,
      DCD_n     => DCD_n,
      CTS_n     => CTS_n,
      RTS_n     => RTS_n
    );
 
  --
  -- RS232 signals:
  --
  my_acia_assignments : process( RS232_RXD, RS232_CTS,
                                 TXD, RTS_n )
  begin
    RXD       <= RS232_RXD;
    CTS_n     <= RS232_CTS;
    DCD_n     <= '0';
    RS232_TXD <= TXD;
    RS232_RTS <= RTS_n;
  end process;
 
  my_ACIA_Clock : ACIA_Clock
    generic map(
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
    )
    port map(
      clk        => clk_i,
      acia_clk   => acia_clk
    );
 
  ----------------------------------------
  --
  -- Timer Module
  --
  ----------------------------------------
  my_timer  : timer
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => timer_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(0),
      data_in   => cpu_data_out,
      data_out  => timer_data_out,
      irq       => timer_irq
    );
 
  ----------------------------------------
  --
  -- Bus Trap Interrupt logic
  --
  ----------------------------------------
  my_trap : trap
    port map (
      clk        => cpu_clk,
      rst        => cpu_reset,
      cs         => trap_cs,
      rw         => cpu_rw,
      vma        => cpu_vma,
      addr       => cpu_addr,
      data_in    => cpu_data_out,
      data_out   => trap_data_out,
      irq        => trap_irq
    );
 
  my_dat : dat_ram
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => dat_cs,
      rw        => cpu_rw,
      addr_hi   => cpu_addr(15 downto 12),
      addr_lo   => cpu_addr(3 downto 0),
      data_in   => cpu_data_out,
      data_out  => dat_addr(7 downto 0)
    );
 
  cpu_clk_buffer : BUFG
    port map(
      i => Clk25,
      o => cpu_clk
    );
 
  ----------------------------------------------------------------------
  --
  -- Process to decode memory map
  --
  ----------------------------------------------------------------------
 
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
                     dat_addr,
                     rom_data_out,
                     flex_data_out,
                     acia_data_out,
                     timer_data_out,
                     trap_data_out,
                     ram1_data_out, ram2_data_out
                     )
  begin
    cpu_data_in <= (others=>'0');
    dat_cs      <= '0';
    rom_cs      <= '0';
    flex_cs     <= '0';
    acia_cs     <= '0';
    timer_cs    <= '0';
    trap_cs     <= '0';
    ram1_cs      <= '0';
    ram2_cs      <= '0';
 
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
      cpu_data_in <= rom_data_out;
      dat_cs      <= cpu_vma;              -- write DAT
      rom_cs      <= cpu_vma;              -- read  ROM
 
    --
    -- Sys09Bug Monitor ROM $F000 - $FFFF
    --
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
      cpu_data_in <= rom_data_out;
      rom_cs      <= cpu_vma;
 
    --
    -- IO Devices $E000 - $E7FF
    --
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
      case cpu_addr(11 downto 8) is
        --
        -- SWTPC peripherals from $E000 to $E0FF
        --
        when "0000" =>
          case cpu_addr(7 downto 4) is
          --
          -- Console Port ACIA $E000 - $E00F
          --
            when "0000" => -- $E000
              cpu_data_in <= acia_data_out;
              acia_cs     <= cpu_vma;
 
            --
            -- Reserved
            -- Floppy Disk Controller port $E010 - $E01F
            --
 
            --
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
            --
            when "0100" => -- $E040
              cpu_data_in <= (others=> '0');
 
            --
            -- Timer $E050 - $E05F
            --
            when "0101" => -- $E050
              cpu_data_in <= timer_data_out;
              timer_cs    <= cpu_vma;
 
            --
            -- Bus Trap Logic $E060 - $E06F
            --
            when "0110" => -- $E060
              cpu_data_in <= trap_data_out;
              trap_cs     <= cpu_vma;
 
            --
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
            --
 
            --
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
            --
 
            --
            -- Remaining 6 slots reserved for non SWTPc Peripherals
            --
            when others => -- $E0A0 to $E0FF
              null;
          end case;
 
        --
        -- $E200 to $EFFF reserved for future use
        --
        when others =>
           null;
      end case;
 
    --
    -- Block RAM (32k) $00000 - $07FFF
    --
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
      cpu_data_in <= ram1_data_out;
      ram1_cs     <= cpu_vma;
 
    --
    -- Block RAM (16k) $08000 - $0BFFF
    --
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
      cpu_data_in <= ram2_data_out;
      ram2_cs     <= cpu_vma;
 
    --
    -- Flex RAM (8k) $0C000 - $0DFFF
    --
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
      cpu_data_in <= flex_data_out;
      flex_cs     <= cpu_vma;
 
    --
    -- Everything else is RAM
    --
    else
      cpu_data_in <= (others => '0');
      ram3_cs      <= cpu_vma;
    end if;
 
  end process;
 
  --
  -- Interrupts and other bus control signals
  --
  interrupts : process( NMI,
                      acia_irq,
                      trap_irq,
                      timer_irq
                      )
  begin
    cpu_irq    <= acia_irq;
    cpu_nmi    <= trap_irq or NMI;
    cpu_firq   <= timer_irq;
    cpu_halt   <= '0';
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
  end process;
 
  --
  -- Flash 7 segment LEDS
  --
  my_led_flasher: process( clk_i, rst_i, CountL )
  begin
    if rst_i = '1' then
         CountL <= "00000000000000000000000000";
    elsif rising_edge(clk_i) then
         CountL <= CountL + 1;
    end if;
    --S(7 downto 0) <= CountL(23 downto 16);
  end process;
 
  status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
  begin
    case sw is
         when "1000" =>
           led(3 downto 0) <= cpu_addr(3 downto 0);
    when "1001" =>
           led(3 downto 0) <= cpu_addr(7 downto 4);
         when "1010" =>
           led(3 downto 0) <= cpu_addr(11 downto 8);
    when "1011" =>
           led(3 downto 0) <= cpu_addr(15 downto 12);
    when "1100" =>
           led(3 downto 0) <= cpu_data_in(3 downto 0);
    when "1101" =>
           led(3 downto 0) <= cpu_data_in(7 downto 4);
    when "0000" =>
           led(3) <= '0';
      led(2) <= CountL(24);
                led(1) <= cpu_reset;
                led(0) <= NMI;
    when others => led(3 downto 0) <= (others => '0');
         end case;
  end process;
 
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
--                      cpu_halt, cpu_hold,
--                      cpu_firq, cpu_irq, cpu_nmi,
--                      cpu_addr, cpu_data_out, cpu_data_in )
--  begin
--    cpu_reset_o    <= cpu_reset;
--    cpu_clk_o      <= cpu_clk;
--    cpu_rw_o       <= cpu_rw;
--    cpu_vma_o      <= cpu_vma;
--    cpu_halt_o     <= cpu_halt;
--    cpu_hold_o     <= cpu_hold;
--    cpu_firq_o     <= cpu_firq;
--    cpu_irq_o      <= cpu_irq;
--    cpu_nmi_o      <= cpu_nmi;
--    cpu_addr_o     <= cpu_addr;
--    cpu_data_out_o <= cpu_data_out;
--    cpu_data_in_o  <= cpu_data_in;
--  end process;
 
end rtl; --===================== End of architecture =======================--
 

Line No.	Rev	Author	Line
1	165	davidgb	`--===========================================================================----`
2			`--`
3			`-- S Y N T H E Z I A B L E System09 - SOC.`
4			`--`
5			`-- www.OpenCores.Org - February 2007`
6			`-- This core adheres to the GNU public license`
7			`--`
8	187	davidgb	`-- File name : system09.vhd`
9	165	davidgb	`--`
10			`-- Purpose : Top level file for 6809 compatible system on a chip`
11	187	davidgb	`-- Designed with Digilent Zybo Z20.`
12			`-- ==========================================================================`
13			`-- Setup/Buttons`
14			`-- RS232 - connect a RS-232 Pmod to JE (upper row)`
15			`-- Configure terminal for 57600 baud 8-N-1, hardware handshake`
16			`--`
17			`-- Slide Switches - selects the nibble to display on the 4 LEDs`
18			`-- 0000 - CPU Address 3 to 0`
19			`-- 0001 - CPU Address 7 to 4`
20			`-- 0010 - CPU Address 11 to 8`
21			`-- 0011 - CPU Address 15 to 12`
22			`-- 0100 - CPU Data 3 to 0`
23			`-- 0101 - CPU Data 7 to 4`
24			`--`
25			`-- Push buttons`
26			`-- BTN3 BTN2 BTN1 BTN0`
27			`-- (unused) Single NMI RESET`
28			`-- Step`
29			`--`
30			`-- Single-Step functionality is controlled by the CLOCK_MODE constant below`
31			`--`
32			`-- Memory Map :`
33	165	davidgb	`--`
34	187	davidgb	`-- $0000 - User program RAM (32K Bytes)`
35			`-- $8000 - User program RAM (16K Bytes)`
36			`-- $C000 - Flex Operating System memory (8K Bytes)`
37			`-- $E000 - ACIA (SWTPc)`
38			`-- $E050 - Timer`
39			`-- $E060 - Bus trap`
40			`-- $F000 - Sys09Bug monitor Program (4K Bytes)`
41			`-- ==========================================================================`
42			`--`
43	165	davidgb	`-- Dependencies : ieee.Std_Logic_1164`
44			`-- ieee.std_logic_unsigned`
45			`-- ieee.std_logic_arith`
46			`-- ieee.numeric_std`
47			`-- unisim.vcomponents`
48			`--`
49	187	davidgb	`-- Uses : mon_rom (sys09swt.vhd) SWTPc S-Bug 1.7 Monitor ROM`
50			`-- cpu09 (cpu09.vhd) CPU core`
51			`-- ACIA_6850 (acia6850.vhd) ACIA / UART`
52			`-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.`
53	165	davidgb	`-- timer (timer.vhd) Interrupt timer`
54			`-- trap (trap.vhd) Bus condition trap logic`
55	187	davidgb	`-- flex_ram (flex9ram.vhd) Flex operating system`
56			`-- ram_16K (ram16k_b16.vhd) 32 KBytes of Block RAM`
57	165	davidgb	`-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM`
58			`--`
59			`--===========================================================================----`
60			`--`
61			`-- Revision History:`
62			`--===========================================================================--`
63	187	davidgb	`-- Version 0.1 - Jan 20, 2021`
64			`-- Copied from the System09_Xess-XSA3S1000 vhdl`
65	165	davidgb	`--===========================================================================--`
66			`library ieee;`
67			`use ieee.std_logic_1164.all;`
68			`use IEEE.STD_LOGIC_ARITH.ALL;`
69			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
70			`use ieee.numeric_std.all;`
71			`library work;`
72			`use work.common.all;`
73			`library unisim;`
74			`use unisim.vcomponents.all;`
75
76			`entity system09 is`
77			`port(`
78	187	davidgb	`CLKA : in Std_Logic; -- 125 MHz Clock input`
79	165	davidgb
80	193	davidgb	`-- RS232 Port - via Pmod RS232`
81	199	davidgb	`RS232_CTS : in Std_Logic;`
82			`RS232_RTS : out Std_Logic;`
83	187	davidgb	`RS232_RXD : in Std_Logic;`
84			`RS232_TXD : out Std_Logic;`
85	165	davidgb
86	187	davidgb	`-- slide switches`
87			`sw : in std_logic_vector(3 downto 0);`
88			`-- push buttons [Unused, Single-Step, NMI, RESET]`
89			`btn : in std_logic_vector(3 downto 0);`
90			`-- Status 4 LEDs`
91			`led : out std_logic_vector(3 downto 0)`
92	165	davidgb	`);`
93			`end system09;`
94
95			`-------------------------------------------------------------------------------`
96			`-- Architecture for System09`
97			`-------------------------------------------------------------------------------`
98			`architecture rtl of system09 is`
99
100			`-----------------------------------------------------------------------------`
101			`-- constants`
102			`-----------------------------------------------------------------------------`
103	187	davidgb	`constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step`
104
105			`constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)`
106	165	davidgb	`constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)`
107			`constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);`
108			`constant BAUD_RATE : integer := 57600; -- Baud Rate`
109			`constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;`
110
111			`-----------------------------------------------------------------------------`
112			`-- Signals`
113	177	davidgb	`-----------------------------------------------------------------------------`
114	187	davidgb	`signal pbtn : std_logic_vector(3 downto 0);`
115	193	davidgb	`signal NMI : std_logic;`
116			`signal RESET : std_logic;`
117	187	davidgb	`signal SINGLE_STEP : std_logic;`
118
119	165	davidgb	`-- BOOT ROM`
120			`signal rom_cs : Std_logic;`
121			`signal rom_data_out : Std_Logic_Vector(7 downto 0);`
122
123			`-- Flex Memory & Monitor Stack`
124			`signal flex_cs : Std_logic;`
125			`signal flex_data_out : Std_Logic_Vector(7 downto 0);`
126
127			`-- ACIA/UART Interface signals`
128			`signal acia_data_out : Std_Logic_Vector(7 downto 0);`
129			`signal acia_cs : Std_Logic;`
130			`signal acia_irq : Std_Logic;`
131			`signal acia_clk : Std_Logic;`
132	193	davidgb	`signal RXD : Std_Logic;`
133			`signal TXD : Std_Logic;`
134	165	davidgb	`signal DCD_n : Std_Logic;`
135			`signal RTS_n : Std_Logic;`
136			`signal CTS_n : Std_Logic;`
137
138			`-- RAM`
139	177	davidgb	`signal ram1_cs : std_logic;`
140			`signal ram1_data_out : std_logic_vector(7 downto 0);`
141			`signal ram2_cs : std_logic;`
142			`signal ram2_data_out : std_logic_vector(7 downto 0);`
143			`signal ram3_cs : std_logic;`
144	165	davidgb
145			`-- CPU Interface signals`
146			`signal cpu_reset : Std_Logic;`
147			`signal cpu_clk : Std_Logic;`
148			`signal cpu_rw : std_logic;`
149			`signal cpu_vma : std_logic;`
150			`signal cpu_halt : std_logic;`
151			`signal cpu_hold : std_logic;`
152			`signal cpu_firq : std_logic;`
153			`signal cpu_irq : std_logic;`
154			`signal cpu_nmi : std_logic;`
155			`signal cpu_addr : std_logic_vector(15 downto 0);`
156			`signal cpu_data_in : std_logic_vector(7 downto 0);`
157			`signal cpu_data_out : std_logic_vector(7 downto 0);`
158
159			`-- Dynamic Address Translation`
160			`signal dat_cs : std_logic;`
161			`signal dat_addr : std_logic_vector(7 downto 0);`
162
163			`-- timer`
164			`signal timer_data_out : std_logic_vector(7 downto 0);`
165			`signal timer_cs : std_logic;`
166			`signal timer_irq : std_logic;`
167
168			`-- trap`
169			`signal trap_cs : std_logic;`
170			`signal trap_data_out : std_logic_vector(7 downto 0);`
171			`signal trap_irq : std_logic;`
172
173			`signal rst_i : std_logic; -- internal reset signal`
174	187	davidgb	`signal clk_i : std_logic; -- internal master clock signal`
175	165	davidgb
176	196	davidgb	`signal CountL : std_logic_vector(25 downto 0);`
177	165	davidgb	`signal clk_count : natural range 0 to CPU_CLK_DIV;`
178			`signal Clk25 : std_logic;`
179	187	davidgb
180
181			`component btn_debounce`
182			`Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0);`
183			`CLK : in STD_LOGIC;`
184			`BTN_O : out STD_LOGIC_VECTOR (3 downto 0));`
185			`end component;`
186
187	165	davidgb
188			`-----------------------------------------------------------------`
189			`--`
190			`-- CPU09 CPU core`
191			`--`
192			`-----------------------------------------------------------------`
193
194			`component cpu09`
195			`port (`
196			`clk: in std_logic;`
197			`rst: in std_logic;`
198			`vma: out std_logic;`
199			`addr: out std_logic_vector(15 downto 0);`
200			`rw: out std_logic; -- Asynchronous memory interface`
201			`data_out: out std_logic_vector(7 downto 0);`
202			`data_in: in std_logic_vector(7 downto 0);`
203			`irq: in std_logic;`
204			`firq: in std_logic;`
205			`nmi: in std_logic;`
206			`halt: in std_logic;`
207			`hold: in std_logic`
208			`);`
209			`end component;`
210
211			`----------------------------------------`
212			`--`
213			`-- 4K Block RAM Monitor ROM`
214			`-- $F000 - $FFFF`
215			`--`
216			`----------------------------------------`
217
218			`component mon_rom`
219			`Port (`
220			`clk : in std_logic;`
221			`rst : in std_logic;`
222			`cs : in std_logic;`
223			`rw : in std_logic;`
224			`addr : in std_logic_vector (11 downto 0);`
225			`data_out : out std_logic_vector (7 downto 0);`
226			`data_in : in std_logic_vector (7 downto 0)`
227			`);`
228			`end component;`
229
230			`----------------------------------------`
231			`--`
232			`-- 8KBytes Block RAM for FLEX9`
233			`-- $C000 - $DFFF`
234			`--`
235			`----------------------------------------`
236
237			`component flex_ram`
238			`Port (`
239			`clk : in std_logic;`
240			`rst : in std_logic;`
241			`cs : in std_logic;`
242			`rw : in std_logic;`
243			`addr : in std_logic_vector (12 downto 0);`
244			`data_out : out std_logic_vector (7 downto 0);`
245			`data_in : in std_logic_vector (7 downto 0)`
246			`);`
247			`end component;`
248	177	davidgb
249			`----------------------------------------`
250			`--`
251			`-- 32KBytes Block RAM 0000`
252			`-- $0000 - $7FFF`
253			`--`
254			`----------------------------------------`
255	165	davidgb
256	177	davidgb	`component ram_32k`
257			`Port (`
258			`clk : in std_logic;`
259			`rst : in std_logic;`
260			`cs : in std_logic;`
261			`rw : in std_logic;`
262			`addr : in std_logic_vector (14 downto 0);`
263			`data_out : out std_logic_vector (7 downto 0);`
264			`data_in : in std_logic_vector (7 downto 0)`
265			`);`
266			`end component;`
267
268
269			`----------------------------------------`
270			`--`
271			`-- 16KBytes Block RAM 8000`
272			`-- $8000 - $BFFF`
273			`--`
274			`----------------------------------------`
275
276			`component ram_16k`
277			`Port (`
278			`clk : in std_logic;`
279			`rst : in std_logic;`
280			`cs : in std_logic;`
281			`rw : in std_logic;`
282			`addr : in std_logic_vector (13 downto 0);`
283			`data_out : out std_logic_vector (7 downto 0);`
284			`data_in : in std_logic_vector (7 downto 0)`
285			`);`
286			`end component;`
287
288	165	davidgb	`-----------------------------------------------------------------`
289			`--`
290			`-- 6850 Compatible ACIA / UART`
291			`--`
292			`-----------------------------------------------------------------`
293
294			`component acia6850`
295			`port (`
296			`clk : in Std_Logic; -- System Clock`
297			`rst : in Std_Logic; -- Reset input (active high)`
298			`cs : in Std_Logic; -- miniUART Chip Select`
299			`rw : in Std_Logic; -- Read / Not Write`
300			`addr : in Std_Logic; -- Register Select`
301			`data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In`
302			`data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out`
303			`irq : out Std_Logic; -- Interrupt`
304			`RxC : in Std_Logic; -- Receive Baud Clock`
305			`TxC : in Std_Logic; -- Transmit Baud Clock`
306			`RxD : in Std_Logic; -- Receive Data`
307			`TxD : out Std_Logic; -- Transmit Data`
308			`DCD_n : in Std_Logic; -- Data Carrier Detect`
309			`CTS_n : in Std_Logic; -- Clear To Send`
310			`RTS_n : out Std_Logic -- Request To send`
311			`);`
312			`end component;`
313
314			`-----------------------------------------------------------------`
315			`--`
316			`-- ACIA Clock divider`
317			`--`
318			`-----------------------------------------------------------------`
319
320			`component ACIA_Clock`
321			`generic (`
322			`SYS_CLK_FREQ : integer := SYS_CLK_FREQ;`
323			`ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ`
324			`);`
325			`port (`
326			`clk : in Std_Logic; -- System Clock Input`
327			`ACIA_clk : out Std_logic -- ACIA Clock output`
328			`);`
329			`end component;`
330
331			`----------------------------------------`
332			`--`
333			`-- Timer module`
334			`--`
335			`----------------------------------------`
336
337			`component timer`
338			`port (`
339			`clk : in std_logic;`
340			`rst : in std_logic;`
341			`cs : in std_logic;`
342			`rw : in std_logic;`
343			`addr : in std_logic;`
344			`data_in : in std_logic_vector(7 downto 0);`
345			`data_out : out std_logic_vector(7 downto 0);`
346			`irq : out std_logic`
347			`);`
348			`end component;`
349
350			`------------------------------------------------------------`
351			`--`
352			`-- Bus Trap logic`
353			`--`
354			`------------------------------------------------------------`
355
356			`component trap`
357			`port (`
358			`clk : in std_logic;`
359			`rst : in std_logic;`
360			`cs : in std_logic;`
361			`rw : in std_logic;`
362			`vma : in std_logic;`
363			`addr : in std_logic_vector(15 downto 0);`
364			`data_in : in std_logic_vector(7 downto 0);`
365			`data_out : out std_logic_vector(7 downto 0);`
366			`irq : out std_logic`
367			`);`
368			`end component;`
369
370			`----------------------------------------`
371			`--`
372			`-- Dynamic Address Translation Registers`
373			`--`
374			`----------------------------------------`
375
376			`component dat_ram`
377			`port (`
378			`clk : in std_logic;`
379			`rst : in std_logic;`
380			`cs : in std_logic;`
381			`rw : in std_logic;`
382			`addr_lo : in std_logic_vector(3 downto 0);`
383			`addr_hi : in std_logic_vector(3 downto 0);`
384			`data_in : in std_logic_vector(7 downto 0);`
385			`data_out : out std_logic_vector(7 downto 0)`
386			`);`
387			`end component;`
388	187	davidgb
389	165	davidgb	`--`
390			`-- Clock buffer`
391			`--`
392
393			`component BUFG`
394			`Port (`
395			`i: in std_logic;`
396			`o: out std_logic`
397			`);`
398			`end component;`
399
400	187	davidgb	`begin`
401	177	davidgb
402	187	davidgb	`--`
403			`-- pushbutton debounce`
404			`--`
405			`my_singlestep: btn_debounce`
406			`port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);`
407
408	193	davidgb	`RESET <= pbtn(0); -- Right PB`
409			`NMI <= pbtn(1); -- Center PB`
410	187	davidgb
411			`--`
412			`-- Generate CPU & Pixel Clock from Memory Clock`
413			`--`
414	196	davidgb
415			`my_prescaler : process( clk_i, clk_count )`
416			`begin`
417			`if rising_edge( clk_i ) then`
418			`if clk_count = 0 then`
419			`clk_count <= CPU_CLK_DIV-1;`
420			`else`
421			`clk_count <= clk_count - 1;`
422	187	davidgb	`end if;`
423	196	davidgb	`if clk_count = 0 then`
424			`clk25 <= '0';`
425			`elsif clk_count = (CPU_CLK_DIV/2) then`
426			`clk25 <= '1';`
427			`end if;`
428			`end if;`
429			`end process;`
430	187	davidgb
431			`--`
432			`-- Reset button and reset timer`
433			`--`
434	193	davidgb	`my_switch_assignments : process( rst_i, RESET)`
435	187	davidgb	`begin`
436	193	davidgb	`rst_i <= RESET;`
437	187	davidgb	`cpu_reset <= rst_i;`
438			`end process;`
439
440			`clk_i <= CLKA;`
441
442	165	davidgb	`-----------------------------------------------------------------------------`
443			`-- Instantiation of internal components`
444			`-----------------------------------------------------------------------------`
445
446			`my_cpu : cpu09`
447			`port map (`
448			`clk => cpu_clk,`
449			`rst => cpu_reset,`
450			`vma => cpu_vma,`
451			`addr => cpu_addr(15 downto 0),`
452			`rw => cpu_rw,`
453			`data_out => cpu_data_out,`
454			`data_in => cpu_data_in,`
455			`irq => cpu_irq,`
456			`firq => cpu_firq,`
457			`nmi => cpu_nmi,`
458			`halt => cpu_halt,`
459			`hold => cpu_hold`
460			`);`
461
462			`my_rom : mon_rom`
463			`port map (`
464			`clk => cpu_clk,`
465			`rst => cpu_reset,`
466			`cs => rom_cs,`
467			`rw => '1',`
468			`addr => cpu_addr(11 downto 0),`
469			`data_in => cpu_data_out,`
470			`data_out => rom_data_out`
471			`);`
472
473			`my_flex : flex_ram`
474			`port map (`
475			`clk => cpu_clk,`
476			`rst => cpu_reset,`
477			`cs => flex_cs,`
478			`rw => cpu_rw,`
479			`addr => cpu_addr(12 downto 0),`
480			`data_out => flex_data_out,`
481			`data_in => cpu_data_out`
482	177	davidgb	`);`
483
484			`my_32k : ram_32k`
485			`port map (`
486			`clk => cpu_clk,`
487			`rst => cpu_reset,`
488			`cs => ram1_cs,`
489			`rw => cpu_rw,`
490			`addr => cpu_addr(14 downto 0),`
491			`data_out => ram1_data_out,`
492			`data_in => cpu_data_out`
493			`);`
494
495			`my_16k : ram_16k`
496			`port map (`
497			`clk => cpu_clk,`
498			`rst => cpu_reset,`
499			`cs => ram2_cs,`
500			`rw => cpu_rw,`

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