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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Blame information for rev 200

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1 165 davidgb 
--===========================================================================----
2 
--
3 
--  S Y N T H E Z I A B L E    System09 - SOC.
4 
--
5 
--  www.OpenCores.Org - February 2007
6 
--  This core adheres to the GNU public license
7 
--
8 187 davidgb 
-- File name      : system09.vhd
9 165 davidgb 
--
10 
-- Purpose        : Top level file for 6809 compatible system on a chip
11 187 davidgb 
--                  Designed with Digilent Zybo Z20.
12 
-- ==========================================================================
13 
-- Setup/Buttons
14 
--    RS232 - connect a RS-232 Pmod to JE (upper row)
15 
--    Configure terminal for 57600 baud 8-N-1, hardware handshake
16 
--
17 
-- Slide Switches - selects the nibble to display on the 4 LEDs
18 
--    0000 - CPU Address 3 to 0
19 
--    0001 - CPU Address 7 to 4
20 
--    0010 - CPU Address 11 to 8
21 
--    0011 - CPU Address 15 to 12
22 
--    0100 - CPU Data 3 to 0
23 
--    0101 - CPU Data 7 to 4
24 
--
25 
-- Push buttons
26 
--     BTN3     BTN2     BTN1     BTN0
27 
--    (unused)  Single   NMI      RESET
28 
--              Step
29 
--
30 
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
31 
--
32 
-- Memory Map     :
33 165 davidgb 
--
34 187 davidgb 
-- $0000 - User program RAM (32K Bytes)
35 
-- $8000 - User program RAM (16K Bytes)
36 
-- $C000 - Flex Operating System memory (8K Bytes)
37 
-- $E000 - ACIA (SWTPc)
38 
-- $E050 - Timer
39 
-- $E060 - Bus trap
40 
-- $F000 - Sys09Bug monitor Program (4K Bytes)
41 
-- ==========================================================================
42 
--
43 165 davidgb 
-- Dependencies   : ieee.Std_Logic_1164
44 
--                  ieee.std_logic_unsigned
45 
--                  ieee.std_logic_arith
46 
--                  ieee.numeric_std
47 
--                  unisim.vcomponents
48 
--
49 187 davidgb 
-- Uses           : mon_rom    (sys09swt.vhd)         SWTPc S-Bug 1.7 Monitor ROM
50 
--                  cpu09      (cpu09.vhd)            CPU core
51 
--                  ACIA_6850  (acia6850.vhd)         ACIA / UART
52 
--                  ACIA_Clock (ACIA_Clock.vhd)       ACIA clock.
53 165 davidgb 
--                  timer      (timer.vhd)            Interrupt timer
54 
--                  trap       (trap.vhd)             Bus condition trap logic
55 187 davidgb 
--                  flex_ram   (flex9ram.vhd)         Flex operating system
56 
--                  ram_16K    (ram16k_b16.vhd)       32 KBytes of Block RAM
57 165 davidgb 
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
58 
--
59 
--===========================================================================----
60 
--
61 
-- Revision History:
62 
--===========================================================================--
63 187 davidgb 
-- Version 0.1 - Jan 20, 2021
64 
--    Copied from the System09_Xess-XSA3S1000 vhdl
65 165 davidgb 
--===========================================================================--
66 
library ieee;
67 
   use ieee.std_logic_1164.all;
68 
   use IEEE.STD_LOGIC_ARITH.ALL;
69 
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
70 
   use ieee.numeric_std.all;
71 
library work;
72 
   use work.common.all;
73 
library unisim;
74 
   use unisim.vcomponents.all;
75 
 
76 
entity system09 is
77 
  port(
78 187 davidgb 
    CLKA         : in  Std_Logic;  -- 125 MHz Clock input
79 165 davidgb 
 
80 193 davidgb 
    -- RS232 Port - via Pmod RS232
81 199 davidgb 
    RS232_CTS    : in  Std_Logic;
82 
    RS232_RTS    : out Std_Logic;
83 187 davidgb 
    RS232_RXD    : in  Std_Logic;
84 
    RS232_TXD    : out Std_Logic;
85 200 davidgb 
 
86 
--      TMDS_Clk_p : out std_logic;
87 
--      TMDS_Clk_n : out std_logic;
88 
--      TMDS_Data_p : out std_logic_vector(2 downto 0);
89 
--      TMDS_Data_n : out std_logic_vector(2 downto 0);
90 
 
91 
    -- raw output from VDU8
92 
    red, green, blue, hsync, vsync, blank : out std_logic;
93 
 
94 187 davidgb 
    -- slide switches
95 
         sw           : in std_logic_vector(3 downto 0);
96 
         -- push buttons [Unused, Single-Step, NMI, RESET]
97 
         btn          : in std_logic_vector(3 downto 0);
98 
    -- Status 4 LEDs
99 
    led          : out std_logic_vector(3 downto 0)
100 165 davidgb 
  );
101 
end system09;
102 
 
103 
-------------------------------------------------------------------------------
104 
-- Architecture for System09
105 
-------------------------------------------------------------------------------
106 
architecture rtl of system09 is
107 
 
108 
  -----------------------------------------------------------------------------
109 
  -- constants
110 
  -----------------------------------------------------------------------------
111 187 davidgb 
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
112 
 
113 
  constant SYS_CLK_FREQ         : natural := 125_000_000;  -- FPGA System Clock (in Hz)
114 165 davidgb 
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
115 200 davidgb 
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
116 
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
117 
  constant VGA_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
118 165 davidgb 
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
119 
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
120 
 
121 
  -----------------------------------------------------------------------------
122 
  -- Signals
123 177 davidgb 
  -----------------------------------------------------------------------------
124 187 davidgb 
  signal pbtn           : std_logic_vector(3 downto 0);
125 193 davidgb 
  signal NMI            : std_logic;
126 
  signal RESET          : std_logic;
127 187 davidgb 
  signal SINGLE_STEP    : std_logic;
128 
 
129 165 davidgb 
  -- BOOT ROM
130 
  signal rom_cs         : Std_logic;
131 
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
132 
 
133 
  -- Flex Memory & Monitor Stack
134 
  signal flex_cs        : Std_logic;
135 
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
136 
 
137 
  -- ACIA/UART Interface signals
138 
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
139 
  signal acia_cs        : Std_Logic;
140 
  signal acia_irq       : Std_Logic;
141 
  signal acia_clk       : Std_Logic;
142 193 davidgb 
  signal RXD            : Std_Logic;
143 
  signal TXD            : Std_Logic;
144 165 davidgb 
  signal DCD_n          : Std_Logic;
145 
  signal RTS_n          : Std_Logic;
146 
  signal CTS_n          : Std_Logic;
147 
 
148 
  -- RAM
149 177 davidgb 
  signal ram1_cs         : std_logic;
150 
  signal ram1_data_out   : std_logic_vector(7 downto 0);
151 
  signal ram2_cs         : std_logic;
152 
  signal ram2_data_out   : std_logic_vector(7 downto 0);
153 
  signal ram3_cs         : std_logic;
154 165 davidgb 
 
155 
  -- CPU Interface signals
156 
  signal cpu_reset      : Std_Logic;
157 
  signal cpu_clk        : Std_Logic;
158 
  signal cpu_rw         : std_logic;
159 
  signal cpu_vma        : std_logic;
160 
  signal cpu_halt       : std_logic;
161 
  signal cpu_hold       : std_logic;
162 
  signal cpu_firq       : std_logic;
163 
  signal cpu_irq        : std_logic;
164 
  signal cpu_nmi        : std_logic;
165 
  signal cpu_addr       : std_logic_vector(15 downto 0);
166 
  signal cpu_data_in    : std_logic_vector(7 downto 0);
167 
  signal cpu_data_out   : std_logic_vector(7 downto 0);
168 
 
169 
  -- Dynamic Address Translation
170 
  signal dat_cs       : std_logic;
171 
  signal dat_addr     : std_logic_vector(7 downto 0);
172 200 davidgb 
 
173 
  -- Video Display Unit (single-bit for each RGB color)
174 
  signal vdu_cs         : std_logic;
175 
  signal vdu_data_out   : std_logic_vector(7 downto 0);
176 
  signal vga_red_o      : std_logic;
177 
  signal vga_green_o    : std_logic;
178 
  signal vga_blue_o     : std_logic;
179 
  signal vga_blank_o    : std_logic; -- new signal
180 
  -- original VGA interface
181 
  signal  vga_vsync_n  :  Std_Logic;
182 
  signal  vga_hsync_n  :  Std_Logic;
183 
  signal  VGA_blue     :  std_logic_vector(7 downto 0);
184 
  signal  VGA_green    :  std_logic_vector(7 downto 0);
185 
  signal  VGA_red      :  std_logic_vector(7 downto 0);
186 
  signal vid_pData :  std_logic_vector(23 downto 0);
187 
  signal serial_clk_unused : std_logic;
188 165 davidgb 
  -- timer
189 
  signal timer_data_out : std_logic_vector(7 downto 0);
190 
  signal timer_cs       : std_logic;
191 
  signal timer_irq      : std_logic;
192 
 
193 
  -- trap
194 
  signal trap_cs        : std_logic;
195 
  signal trap_data_out  : std_logic_vector(7 downto 0);
196 
  signal trap_irq       : std_logic;
197 
 
198 
  signal rst_i         : std_logic;     -- internal reset signal
199 187 davidgb 
  signal clk_i         : std_logic;     -- internal master clock signal
200 165 davidgb 
 
201 196 davidgb 
  signal CountL        : std_logic_vector(25 downto 0);
202 165 davidgb 
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
203 200 davidgb 
  signal Clk25         : std_logic;
204 
  signal vga_clk       : std_logic;
205 187 davidgb 
 
206 
component btn_debounce
207 
    Port ( BTN_I : in  STD_LOGIC_VECTOR (3 downto 0);
208 
           CLK : in  STD_LOGIC;
209 
           BTN_O : out  STD_LOGIC_VECTOR (3 downto 0));
210 
end component;
211 
 
212 165 davidgb 
 
213 
-----------------------------------------------------------------
214 
--
215 
-- CPU09 CPU core
216 
--
217 
-----------------------------------------------------------------
218 
 
219 
component cpu09
220 
  port (
221 
    clk:      in  std_logic;
222 
    rst:      in  std_logic;
223 
    vma:      out std_logic;
224 
    addr:     out std_logic_vector(15 downto 0);
225 
    rw:       out std_logic;     -- Asynchronous memory interface
226 
    data_out: out std_logic_vector(7 downto 0);
227 
    data_in:  in  std_logic_vector(7 downto 0);
228 
    irq:      in  std_logic;
229 
    firq:     in  std_logic;
230 
    nmi:      in  std_logic;
231 
    halt:     in  std_logic;
232 
    hold:     in  std_logic
233 
  );
234 
end component;
235 
 
236 
----------------------------------------
237 
--
238 
-- 4K Block RAM Monitor ROM
239 
-- $F000 - $FFFF
240 
--
241 
----------------------------------------
242 
 
243 
component mon_rom
244 
  Port (
245 
    clk   : in  std_logic;
246 
    rst   : in  std_logic;
247 
    cs    : in  std_logic;
248 
    rw    : in  std_logic;
249 
    addr  : in  std_logic_vector (11 downto 0);
250 
    data_out : out std_logic_vector (7 downto 0);
251 
    data_in : in  std_logic_vector (7 downto 0)
252 
  );
253 
end component;
254 
 
255 
----------------------------------------
256 
--
257 
-- 8KBytes Block RAM for FLEX9
258 
-- $C000 - $DFFF
259 
--
260 
----------------------------------------
261 
 
262 
component flex_ram
263 
  Port (
264 
    clk      : in  std_logic;
265 
    rst      : in  std_logic;
266 
    cs       : in  std_logic;
267 
    rw       : in  std_logic;
268 
    addr     : in  std_logic_vector (12 downto 0);
269 
    data_out    : out std_logic_vector (7 downto 0);
270 
    data_in    : in  std_logic_vector (7 downto 0)
271 
  );
272 
end component;
273 177 davidgb 
 
274 
----------------------------------------
275 
--
276 
-- 32KBytes Block RAM 0000
277 
-- $0000 - $7FFF
278 
--
279 
----------------------------------------
280 165 davidgb 
 
281 177 davidgb 
component ram_32k
282 
  Port (
283 
    clk      : in  std_logic;
284 
    rst      : in  std_logic;
285 
    cs       : in  std_logic;
286 
    rw       : in  std_logic;
287 
    addr     : in  std_logic_vector (14 downto 0);
288 
    data_out    : out std_logic_vector (7 downto 0);
289 
    data_in    : in  std_logic_vector (7 downto 0)
290 
  );
291 
end component;
292 
 
293 
 
294 
----------------------------------------
295 
--
296 
-- 16KBytes Block RAM 8000
297 
-- $8000 - $BFFF
298 
--
299 
----------------------------------------
300 
 
301 
component ram_16k
302 
  Port (
303 
    clk      : in  std_logic;
304 
    rst      : in  std_logic;
305 
    cs       : in  std_logic;
306 
    rw       : in  std_logic;
307 
    addr     : in  std_logic_vector (13 downto 0);
308 
    data_out    : out std_logic_vector (7 downto 0);
309 
    data_in    : in  std_logic_vector (7 downto 0)
310 
  );
311 
end component;
312 
 
313 165 davidgb 
-----------------------------------------------------------------
314 
--
315 
-- 6850 Compatible ACIA / UART
316 
--
317 
-----------------------------------------------------------------
318 
 
319 
component acia6850
320 
  port (
321 
    clk      : in  Std_Logic;  -- System Clock
322 
    rst      : in  Std_Logic;  -- Reset input (active high)
323 
    cs       : in  Std_Logic;  -- miniUART Chip Select
324 
    rw       : in  Std_Logic;  -- Read / Not Write
325 
    addr     : in  Std_Logic;  -- Register Select
326 
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In
327 
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
328 
    irq      : out Std_Logic;  -- Interrupt
329 
    RxC      : in  Std_Logic;  -- Receive Baud Clock
330 
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
331 
    RxD      : in  Std_Logic;  -- Receive Data
332 
    TxD      : out Std_Logic;  -- Transmit Data
333 
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
334 
    CTS_n    : in  Std_Logic;  -- Clear To Send
335 
    RTS_n    : out Std_Logic   -- Request To send
336 
  );
337 
end component;
338 
 
339 
-----------------------------------------------------------------
340 
--
341 
-- ACIA Clock divider
342 
--
343 
-----------------------------------------------------------------
344 
 
345 
component ACIA_Clock
346 
  generic (
347 
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
348 
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
349 
  );
350 
  port (
351 
    clk      : in  Std_Logic;  -- System Clock Input
352 
    ACIA_clk : out Std_logic   -- ACIA Clock output
353 
  );
354 
end component;
355 200 davidgb 
 
356 
 
357 
----------------------------------------
358 
--
359 
-- Video Display Unit.
360 
--
361 
----------------------------------------
362 165 davidgb 
 
363 200 davidgb 
component vdu8
364 
  generic(
365 
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
366 
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
367 
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
368 
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
369 
    VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
370 
    VGA_LIN_PER_CHAR       : integer := 16; -- LINES
371 
    VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
372 
    VGA_HOR_SYNC           : integer := 96; -- PIXELS
373 
    VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
374 
    VGA_VER_BACK_PORCH     : integer := 13; -- LINES
375 
    VGA_VER_SYNC           : integer := 2;  -- LINES
376 
    VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
377 
  );
378 
  port(
379 
    -- control register interface
380 
    vdu_clk      : in  std_logic;  -- CPU Clock - 25MHz
381 
    vdu_rst      : in  std_logic;
382 
    vdu_cs       : in  std_logic;
383 
    vdu_rw       : in  std_logic;
384 
    vdu_addr     : in  std_logic_vector(2 downto 0);
385 
    vdu_data_in  : in  std_logic_vector(7 downto 0);
386 
    vdu_data_out : out std_logic_vector(7 downto 0);
387 
 
388 
    -- vga port connections
389 
    vga_clk      : in  std_logic; -- VGA Pixel Clock - 25 MHz
390 
    vga_red_o    : out std_logic;
391 
    vga_green_o  : out std_logic;
392 
    vga_blue_o   : out std_logic;
393 
         vga_blank_o  : out std_logic; -- new signal "blank"
394 
    vga_hsync_o  : out std_logic;
395 
    vga_vsync_o  : out std_logic
396 
  );
397 
end component;
398 
 
399 
 
400 165 davidgb 
----------------------------------------
401 
--
402 
-- Timer module
403 
--
404 
----------------------------------------
405 
 
406 
component timer
407 
  port (
408 
    clk       : in std_logic;
409 
    rst       : in std_logic;
410 
    cs        : in std_logic;
411 
    rw        : in std_logic;
412 
    addr      : in std_logic;
413 
    data_in   : in std_logic_vector(7 downto 0);
414 
    data_out  : out std_logic_vector(7 downto 0);
415 
    irq       : out std_logic
416 
  );
417 
end component;
418 
 
419 
------------------------------------------------------------
420 
--
421 
-- Bus Trap logic
422 
--
423 
------------------------------------------------------------
424 
 
425 
component trap
426 
  port (
427 
    clk        : in  std_logic;
428 
    rst        : in  std_logic;
429 
    cs         : in  std_logic;
430 
    rw         : in  std_logic;
431 
    vma        : in  std_logic;
432 
    addr       : in  std_logic_vector(15 downto 0);
433 
    data_in    : in  std_logic_vector(7 downto 0);
434 
    data_out   : out std_logic_vector(7 downto 0);
435 
    irq        : out std_logic
436 
  );
437 
end component;
438 
 
439 
----------------------------------------
440 
--
441 
-- Dynamic Address Translation Registers
442 
--
443 
----------------------------------------
444 
 
445 
component dat_ram
446 
  port (
447 
    clk      : in  std_logic;
448 
    rst      : in  std_logic;
449 
    cs       : in  std_logic;
450 
    rw       : in  std_logic;
451 
    addr_lo  : in  std_logic_vector(3 downto 0);
452 
    addr_hi  : in  std_logic_vector(3 downto 0);
453 
    data_in  : in  std_logic_vector(7 downto 0);
454 
    data_out : out std_logic_vector(7 downto 0)
455 
  );
456 
end component;
457 187 davidgb 
 
458 165 davidgb 
--
459 
-- Clock buffer
460 
--
461 
 
462 
component BUFG
463 
   Port (
464 
     i: in std_logic;
465 
     o: out std_logic
466 
  );
467 
end component;
468 
 
469 187 davidgb 
begin
470 177 davidgb 
 
471 187 davidgb 
  --
472 
  -- pushbutton debounce
473 
  --
474 
  my_singlestep: btn_debounce
475 
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
476 
 
477 193 davidgb 
  RESET      <= pbtn(0); -- Right PB
478 
  NMI        <= pbtn(1); -- Center PB
479 187 davidgb 
 
480 
  --
481 
  -- Generate CPU & Pixel Clock from Memory Clock
482 
  --
483 196 davidgb 
 
484 
  my_prescaler : process( clk_i, clk_count )
485 
  begin
486 
    if rising_edge( clk_i ) then
487 
      if clk_count = 0 then
488 
        clk_count <= CPU_CLK_DIV-1;
489 
      else
490 
        clk_count <= clk_count - 1;
491 187 davidgb 
      end if;
492 196 davidgb 
      if clk_count = 0 then
493 
         clk25 <= '0';
494 
      elsif clk_count = (CPU_CLK_DIV/2) then
495 
         clk25 <= '1';
496 
      end if;
497 
    end if;
498 
  end process;
499 187 davidgb 
 
500 
  --
501 
  -- Reset button and reset timer
502 
  --
503 193 davidgb 
  my_switch_assignments : process( rst_i, RESET)
504 187 davidgb 
  begin
505 193 davidgb 
    rst_i <= RESET;
506 187 davidgb 
    cpu_reset <= rst_i;
507 
  end process;
508 
 
509 
  clk_i <= CLKA;
510 
 
511 165 davidgb 
  -----------------------------------------------------------------------------
512 
  -- Instantiation of internal components
513 
  -----------------------------------------------------------------------------
514 
 
515 
  my_cpu : cpu09
516 
    port map (
517 
      clk       => cpu_clk,
518 
      rst       => cpu_reset,
519 
      vma       => cpu_vma,
520 
      addr      => cpu_addr(15 downto 0),
521 
      rw        => cpu_rw,
522 
      data_out  => cpu_data_out,
523 
      data_in   => cpu_data_in,
524 
      irq       => cpu_irq,
525 
      firq      => cpu_firq,
526 
      nmi       => cpu_nmi,
527 
      halt      => cpu_halt,
528 
      hold      => cpu_hold
529 
    );
530 
 
531 
  my_rom : mon_rom
532 
    port map (
533 
      clk   => cpu_clk,
534 
      rst   => cpu_reset,
535 
      cs    => rom_cs,
536 
      rw    => '1',
537 
      addr  => cpu_addr(11 downto 0),
538 
      data_in => cpu_data_out,
539 
      data_out => rom_data_out
540 
    );
541 
 
542 
  my_flex : flex_ram
543 
    port map (
544 
      clk       => cpu_clk,
545 
      rst       => cpu_reset,
546 
      cs        => flex_cs,
547 
      rw        => cpu_rw,
548 
      addr      => cpu_addr(12 downto 0),
549 
      data_out     => flex_data_out,
550 
      data_in     => cpu_data_out
551 177 davidgb 
    );
552 
 
553 
  my_32k : ram_32k
554 
    port map (
555 
      clk       => cpu_clk,
556 
      rst       => cpu_reset,
557 
      cs        => ram1_cs,
558 
      rw        => cpu_rw,
559 
      addr      => cpu_addr(14 downto 0),
560 
      data_out     => ram1_data_out,
561 
      data_in     => cpu_data_out
562 
    );
563 
 
564 
  my_16k : ram_16k
565 
    port map (
566 
      clk       => cpu_clk,
567 
      rst       => cpu_reset,
568 
      cs        => ram2_cs,
569 
      rw        => cpu_rw,
570 
      addr      => cpu_addr(13 downto 0),
571 
      data_out     => ram2_data_out,
572 
      data_in     => cpu_data_out
573 
    );
574 
 
575 165 davidgb 
  my_acia  : acia6850
576 
    port map (
577 
      clk       => cpu_clk,
578 
      rst       => cpu_reset,
579 
      cs        => acia_cs,
580 
      rw        => cpu_rw,
581 
      addr      => cpu_addr(0),
582 
      data_in   => cpu_data_out,
583 
      data_out  => acia_data_out,
584 
      irq       => acia_irq,
585 
      RxC       => acia_clk,
586 
      TxC       => acia_clk,
587 193 davidgb 
      RxD       => RXD,
588 
      TxD       => TXD,
589 
      DCD_n     => DCD_n,
590 
      CTS_n     => CTS_n,
591 
      RTS_n     => RTS_n
592 
    );
593 
 
594 
  --
595 
  -- RS232 signals:
596 
  --
597 199 davidgb 
  my_acia_assignments : process( RS232_RXD, RS232_CTS,
598 196 davidgb 
                                 TXD, RTS_n )
599 193 davidgb 
  begin
600 
    RXD       <= RS232_RXD;
601 199 davidgb 
    CTS_n     <= RS232_CTS;
602 193 davidgb 
    DCD_n     <= '0';
603 
    RS232_TXD <= TXD;
604 199 davidgb 
    RS232_RTS <= RTS_n;
605 193 davidgb 
  end process;
606 187 davidgb 
 
607 165 davidgb 
  my_ACIA_Clock : ACIA_Clock
608 
    generic map(
609 187 davidgb 
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
610 165 davidgb 
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
611 
    )
612 
    port map(
613 193 davidgb 
      clk        => clk_i,
614 165 davidgb 
      acia_clk   => acia_clk
615 
    );
616 200 davidgb 
 
617 
  ----------------------------------------
618 
  --
619 
  -- Video Display Unit instantiation
620 
  --
621 
  ----------------------------------------
622 
  my_vdu : vdu8
623 
    generic map(
624 
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
625 
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
626 
      VGA_HOR_CHARS          => 80, -- CHARACTERS
627 
      VGA_VER_CHARS          => 25, -- CHARACTERS
628 
      VGA_PIX_PER_CHAR       => 8,  -- PIXELS
629 
      VGA_LIN_PER_CHAR       => 16, -- LINES
630 
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
631 
      VGA_HOR_SYNC           => 96, -- PIXELS
632 
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
633 
      VGA_VER_BACK_PORCH     => 13, -- LINES
634 
      VGA_VER_SYNC           => 2,  -- LINES
635 
      VGA_VER_FRONT_PORCH    => 35  -- LINES
636 
    )
637 
    port map(
638 
      -- Control Registers
639 
      vdu_clk       => cpu_clk,               -- 12.5 MHz System Clock in
640 
      vdu_rst       => cpu_reset,
641 
      vdu_cs        => vdu_cs,
642 
      vdu_rw        => cpu_rw,
643 
      vdu_addr      => cpu_addr(2 downto 0),
644 
      vdu_data_in   => cpu_data_out,
645 
      vdu_data_out  => vdu_data_out,
646 
      -- vga port connections
647 
      vga_clk       => vga_clk,               -- 25 MHz VDU pixel clock
648 
      vga_red_o     => red,
649 
      vga_green_o   => green,
650 
      vga_blue_o    => blue,
651 
                vga_blank_o   => blank, -- new signal
652 
      vga_hsync_o   => hsync,
653 
      vga_vsync_o   => vsync
654 
   );
655 165 davidgb 
 
656 
  ----------------------------------------
657 
  --
658 
  -- Timer Module
659 
  --
660 
  ----------------------------------------
661 
  my_timer  : timer
662 
    port map (
663 
      clk       => cpu_clk,
664 
      rst       => cpu_reset,
665 
      cs        => timer_cs,
666 
      rw        => cpu_rw,
667 
      addr      => cpu_addr(0),
668 
      data_in   => cpu_data_out,
669 
      data_out  => timer_data_out,
670 
      irq       => timer_irq
671 
    );
672 
 
673 
  ----------------------------------------
674 
  --
675 
  -- Bus Trap Interrupt logic
676 
  --
677 
  ----------------------------------------
678 
  my_trap : trap
679 
    port map (
680 
      clk        => cpu_clk,
681 
      rst        => cpu_reset,
682 
      cs         => trap_cs,
683 
      rw         => cpu_rw,
684 
      vma        => cpu_vma,
685 
      addr       => cpu_addr,
686 
      data_in    => cpu_data_out,
687 
      data_out   => trap_data_out,
688 
      irq        => trap_irq
689 
    );
690 
 
691 
  my_dat : dat_ram
692 
    port map (
693 
      clk       => cpu_clk,
694 
      rst       => cpu_reset,
695 
      cs        => dat_cs,
696 
      rw        => cpu_rw,
697 
      addr_hi   => cpu_addr(15 downto 12),
698 
      addr_lo   => cpu_addr(3 downto 0),
699 
      data_in   => cpu_data_out,
700 
      data_out  => dat_addr(7 downto 0)
701 
    );
702 
 
703 
  cpu_clk_buffer : BUFG
704 
    port map(
705 
      i => Clk25,
706 
      o => cpu_clk
707 
    );
708 
 
709 
  ----------------------------------------------------------------------
710 
  --
711 
  -- Process to decode memory map
712 
  --
713 
  ----------------------------------------------------------------------
714 
 
715 
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
716 
                     dat_addr,
717 
                     rom_data_out,
718 
                     flex_data_out,
719 
                     acia_data_out,
720 200 davidgb 
                     vdu_data_out,
721 165 davidgb 
                     timer_data_out,
722 
                     trap_data_out,
723 177 davidgb 
                     ram1_data_out, ram2_data_out
724 165 davidgb 
                     )
725 
  begin
726 
    cpu_data_in <= (others=>'0');
727 
    dat_cs      <= '0';
728 
    rom_cs      <= '0';
729 
    flex_cs     <= '0';
730 200 davidgb 
    acia_cs     <= '0';
731 
    vdu_cs      <= '0';
732 165 davidgb 
    timer_cs    <= '0';
733 
    trap_cs     <= '0';
734 177 davidgb 
    ram1_cs      <= '0';
735 
    ram2_cs      <= '0';
736 
 
737 165 davidgb 
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
738 
      cpu_data_in <= rom_data_out;
739 
      dat_cs      <= cpu_vma;              -- write DAT
740 
      rom_cs      <= cpu_vma;              -- read  ROM
741 
 
742 
    --
743 
    -- Sys09Bug Monitor ROM $F000 - $FFFF
744 
    --
745 
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
746 
      cpu_data_in <= rom_data_out;
747 
      rom_cs      <= cpu_vma;
748 
 
749 
    --
750 
    -- IO Devices $E000 - $E7FF
751 
    --
752 
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
753 
      case cpu_addr(11 downto 8) is
754 
        --
755 
        -- SWTPC peripherals from $E000 to $E0FF
756 
        --
757 
        when "0000" =>
758 
          case cpu_addr(7 downto 4) is
759 
          --
760 
          -- Console Port ACIA $E000 - $E00F
761 
          --
762 
            when "0000" => -- $E000
763 
              cpu_data_in <= acia_data_out;
764 
              acia_cs     <= cpu_vma;
765 
 
766 
            --
767 
            -- Reserved
768 
            -- Floppy Disk Controller port $E010 - $E01F
769 
            --
770 
            --
771 200 davidgb 
            -- VDU port $E030 - $E03F
772 
            --
773 
            when "0011" => -- $E030
774 
              cpu_data_in <= vdu_data_out;
775 
              vdu_cs      <= cpu_vma;
776 
 
777 
            --
778 165 davidgb 
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
779 
            --
780 
            when "0100" => -- $E040
781 
              cpu_data_in <= (others=> '0');
782 
 
783 
            --
784 
            -- Timer $E050 - $E05F
785 
            --
786 
            when "0101" => -- $E050
787 
              cpu_data_in <= timer_data_out;
788 
              timer_cs    <= cpu_vma;
789 
 
790 
            --
791 
            -- Bus Trap Logic $E060 - $E06F
792 
            --
793 
            when "0110" => -- $E060
794 
              cpu_data_in <= trap_data_out;
795 
              trap_cs     <= cpu_vma;
796 
 
797 
            --
798 
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
799 
            --
800 
 
801 
            --
802 
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
803 
            --
804 
 
805 
            --
806 
            -- Remaining 6 slots reserved for non SWTPc Peripherals
807 
            --
808 
            when others => -- $E0A0 to $E0FF
809 
              null;
810 
          end case;
811 
 
812 
        --
813 
        -- $E200 to $EFFF reserved for future use
814 
        --
815 
        when others =>
816 
           null;
817 
      end case;
818 177 davidgb 
 
819 
    --
820 193 davidgb 
    -- Block RAM (32k) $00000 - $07FFF
821 177 davidgb 
    --
822 193 davidgb 
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
823 177 davidgb 
      cpu_data_in <= ram1_data_out;
824 
      ram1_cs     <= cpu_vma;
825 
 
826 
    --
827 193 davidgb 
    -- Block RAM (16k) $08000 - $0BFFF
828 177 davidgb 
    --
829 193 davidgb 
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
830 177 davidgb 
      cpu_data_in <= ram2_data_out;
831 
      ram2_cs     <= cpu_vma;
832 165 davidgb 
 
833 
    --
834 193 davidgb 
    -- Flex RAM (8k) $0C000 - $0DFFF
835 
    --
836 
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
837 
      cpu_data_in <= flex_data_out;
838 
      flex_cs     <= cpu_vma;
839 
 
840 
    --
841 165 davidgb 
    -- Everything else is RAM
842 
    --
843 
    else
844 177 davidgb 
      cpu_data_in <= (others => '0');
845 
      ram3_cs      <= cpu_vma;
846 165 davidgb 
    end if;
847 
 
848 
  end process;
849 
 
850 
  --
851 
  -- Interrupts and other bus control signals
852 
  --
853 193 davidgb 
  interrupts : process( NMI,
854 165 davidgb 
                      acia_irq,
855 
                      trap_irq,
856 
                      timer_irq
857 
                      )
858 
  begin
859 
    cpu_irq    <= acia_irq;
860 193 davidgb 
    cpu_nmi    <= trap_irq or NMI;
861 165 davidgb 
    cpu_firq   <= timer_irq;
862 
    cpu_halt   <= '0';
863 177 davidgb 
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
864 165 davidgb 
  end process;
865 
 
866 
  --
867 187 davidgb 
  -- Flash 7 segment LEDS
868 165 davidgb 
  --
869 187 davidgb 
  my_led_flasher: process( clk_i, rst_i, CountL )
870 165 davidgb 
  begin
871 187 davidgb 
    if rst_i = '1' then
872 196 davidgb 
         CountL <= "00000000000000000000000000";
873 187 davidgb 
    elsif rising_edge(clk_i) then
874 
         CountL <= CountL + 1;
875 165 davidgb 
    end if;
876 187 davidgb 
    --S(7 downto 0) <= CountL(23 downto 16);
877 165 davidgb 
  end process;
878 
 
879 193 davidgb 
  status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
880 187 davidgb 
  begin
881 
    case sw is
882 196 davidgb 
         when "1000" =>
883 187 davidgb 
           led(3 downto 0) <= cpu_addr(3 downto 0);
884 196 davidgb 
    when "1001" =>
885 187 davidgb 
           led(3 downto 0) <= cpu_addr(7 downto 4);
886 196 davidgb 
         when "1010" =>
887 187 davidgb 
           led(3 downto 0) <= cpu_addr(11 downto 8);
888 196 davidgb 
    when "1011" =>
889 187 davidgb 
           led(3 downto 0) <= cpu_addr(15 downto 12);
890 196 davidgb 
    when "1100" =>
891 187 davidgb 
           led(3 downto 0) <= cpu_data_in(3 downto 0);
892 196 davidgb 
    when "1101" =>
893 
           led(3 downto 0) <= cpu_data_in(7 downto 4);
894 
    when "0000" =>
895 
           led(3) <= '0';
896 
      led(2) <= CountL(24);
897 
                led(1) <= cpu_reset;
898 
                led(0) <= NMI;
899 187 davidgb 
    when others => led(3 downto 0) <= (others => '0');
900 
         end case;
901 165 davidgb 
  end process;
902 
 
903 
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
904 
--                      cpu_halt, cpu_hold,
905 
--                      cpu_firq, cpu_irq, cpu_nmi,
906 
--                      cpu_addr, cpu_data_out, cpu_data_in )
907 
--  begin
908 
--    cpu_reset_o    <= cpu_reset;
909 
--    cpu_clk_o      <= cpu_clk;
910 
--    cpu_rw_o       <= cpu_rw;
911 
--    cpu_vma_o      <= cpu_vma;
912 
--    cpu_halt_o     <= cpu_halt;
913 
--    cpu_hold_o     <= cpu_hold;
914 
--    cpu_firq_o     <= cpu_firq;
915 
--    cpu_irq_o      <= cpu_irq;
916 
--    cpu_nmi_o      <= cpu_nmi;
917 
--    cpu_addr_o     <= cpu_addr;
918 
--    cpu_data_out_o <= cpu_data_out;
919 
--    cpu_data_in_o  <= cpu_data_in;
920 
--  end process;
921 
 
922 
end rtl; --===================== End of architecture =======================--
923 
 

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