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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Blame information for rev 202

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1 165 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8 187 davidgb
-- File name      : system09.vhd
9 165 davidgb
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11 187 davidgb
--                  Designed with Digilent Zybo Z20.
12
-- ==========================================================================
13
-- Setup/Buttons
14
--    RS232 - connect a RS-232 Pmod to JE (upper row)
15
--    Configure terminal for 57600 baud 8-N-1, hardware handshake
16
--
17
-- Slide Switches - selects the nibble to display on the 4 LEDs
18
--    0000 - CPU Address 3 to 0
19
--    0001 - CPU Address 7 to 4
20
--    0010 - CPU Address 11 to 8
21
--    0011 - CPU Address 15 to 12
22
--    0100 - CPU Data 3 to 0
23
--    0101 - CPU Data 7 to 4
24
--
25
-- Push buttons
26
--     BTN3     BTN2     BTN1     BTN0
27
--    (unused)  Single   NMI      RESET
28
--              Step
29
--
30
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
31
--
32
-- Memory Map     :
33 165 davidgb
--
34 187 davidgb
-- $0000 - User program RAM (32K Bytes)
35
-- $8000 - User program RAM (16K Bytes)
36
-- $C000 - Flex Operating System memory (8K Bytes)
37
-- $E000 - ACIA (SWTPc)
38
-- $E050 - Timer
39
-- $E060 - Bus trap
40
-- $F000 - Sys09Bug monitor Program (4K Bytes)
41
-- ==========================================================================
42
--
43 165 davidgb
-- Dependencies   : ieee.Std_Logic_1164
44
--                  ieee.std_logic_unsigned
45
--                  ieee.std_logic_arith
46
--                  ieee.numeric_std
47
--                  unisim.vcomponents
48
--
49 187 davidgb
-- Uses           : mon_rom    (sys09swt.vhd)         SWTPc S-Bug 1.7 Monitor ROM 
50
--                  cpu09      (cpu09.vhd)            CPU core
51
--                  ACIA_6850  (acia6850.vhd)         ACIA / UART
52
--                  ACIA_Clock (ACIA_Clock.vhd)       ACIA clock.
53 165 davidgb
--                  timer      (timer.vhd)            Interrupt timer
54
--                  trap       (trap.vhd)             Bus condition trap logic
55 187 davidgb
--                  flex_ram   (flex9ram.vhd)         Flex operating system
56
--                  ram_16K    (ram16k_b16.vhd)       32 KBytes of Block RAM
57 165 davidgb
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
58
--                  
59
--===========================================================================----
60
--
61
-- Revision History:
62
--===========================================================================--
63 187 davidgb
-- Version 0.1 - Jan 20, 2021
64
--    Copied from the System09_Xess-XSA3S1000 vhdl
65 165 davidgb
--===========================================================================--
66
library ieee;
67
   use ieee.std_logic_1164.all;
68
   use IEEE.STD_LOGIC_ARITH.ALL;
69
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
70
   use ieee.numeric_std.all;
71
library work;
72
   use work.common.all;
73
library unisim;
74
   use unisim.vcomponents.all;
75
 
76
entity system09 is
77
  port(
78 187 davidgb
    CLKA         : in  Std_Logic;  -- 125 MHz Clock input
79 165 davidgb
 
80 193 davidgb
    -- RS232 Port - via Pmod RS232
81 199 davidgb
    RS232_CTS    : in  Std_Logic;
82
    RS232_RTS    : out Std_Logic;
83 187 davidgb
    RS232_RXD    : in  Std_Logic;
84
    RS232_TXD    : out Std_Logic;
85 200 davidgb
 
86
--      TMDS_Clk_p : out std_logic;
87
--      TMDS_Clk_n : out std_logic;
88
--      TMDS_Data_p : out std_logic_vector(2 downto 0);
89
--      TMDS_Data_n : out std_logic_vector(2 downto 0);
90
 
91 202 davidgb
    -- CRTC output signals
92
    VGA_vsync_n  : out Std_Logic;
93
    VGA_hsync_n  : out Std_Logic;
94
    VGA_blue     : out std_logic_vector(3 downto 0);
95
    VGA_green    : out std_logic_vector(3 downto 0);
96
    VGA_red      : out std_logic_vector(3 downto 0);
97 200 davidgb
 
98 187 davidgb
    -- slide switches
99
         sw           : in std_logic_vector(3 downto 0);
100
         -- push buttons [Unused, Single-Step, NMI, RESET]
101
         btn          : in std_logic_vector(3 downto 0);
102
    -- Status 4 LEDs
103
    led          : out std_logic_vector(3 downto 0)
104 165 davidgb
  );
105
end system09;
106
 
107
-------------------------------------------------------------------------------
108
-- Architecture for System09
109
-------------------------------------------------------------------------------
110
architecture rtl of system09 is
111
 
112
  -----------------------------------------------------------------------------
113
  -- constants
114
  -----------------------------------------------------------------------------
115 187 davidgb
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
116
 
117
  constant SYS_CLK_FREQ         : natural := 125_000_000;  -- FPGA System Clock (in Hz)
118 165 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
119 200 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
120
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
121 202 davidgb
  constant VGA_CLK_DIV          : natural := (SYS_CLK_FREQ/VGA_CLK_FREQ);
122 165 davidgb
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
123
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
124
 
125
  -----------------------------------------------------------------------------
126
  -- Signals
127 177 davidgb
  -----------------------------------------------------------------------------
128 187 davidgb
  signal pbtn           : std_logic_vector(3 downto 0);
129 193 davidgb
  signal NMI            : std_logic;
130
  signal RESET          : std_logic;
131 187 davidgb
  signal SINGLE_STEP    : std_logic;
132
 
133 165 davidgb
  -- BOOT ROM
134
  signal rom_cs         : Std_logic;
135
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
136
 
137
  -- Flex Memory & Monitor Stack
138
  signal flex_cs        : Std_logic;
139
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
140
 
141
  -- ACIA/UART Interface signals
142
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
143
  signal acia_cs        : Std_Logic;
144
  signal acia_irq       : Std_Logic;
145
  signal acia_clk       : Std_Logic;
146 193 davidgb
  signal RXD            : Std_Logic;
147
  signal TXD            : Std_Logic;
148 165 davidgb
  signal DCD_n          : Std_Logic;
149
  signal RTS_n          : Std_Logic;
150
  signal CTS_n          : Std_Logic;
151
 
152
  -- RAM
153 177 davidgb
  signal ram1_cs         : std_logic;
154
  signal ram1_data_out   : std_logic_vector(7 downto 0);
155
  signal ram2_cs         : std_logic;
156
  signal ram2_data_out   : std_logic_vector(7 downto 0);
157
  signal ram3_cs         : std_logic;
158 165 davidgb
 
159
  -- CPU Interface signals
160
  signal cpu_reset      : Std_Logic;
161
  signal cpu_clk        : Std_Logic;
162
  signal cpu_rw         : std_logic;
163
  signal cpu_vma        : std_logic;
164
  signal cpu_halt       : std_logic;
165
  signal cpu_hold       : std_logic;
166
  signal cpu_firq       : std_logic;
167
  signal cpu_irq        : std_logic;
168
  signal cpu_nmi        : std_logic;
169
  signal cpu_addr       : std_logic_vector(15 downto 0);
170
  signal cpu_data_in    : std_logic_vector(7 downto 0);
171
  signal cpu_data_out   : std_logic_vector(7 downto 0);
172
 
173
  -- Dynamic Address Translation
174
  signal dat_cs       : std_logic;
175
  signal dat_addr     : std_logic_vector(7 downto 0);
176 200 davidgb
 
177 202 davidgb
  -- Video Display Unit
178 200 davidgb
  signal vdu_cs         : std_logic;
179
  signal vdu_data_out   : std_logic_vector(7 downto 0);
180
  signal vga_red_o      : std_logic;
181
  signal vga_green_o    : std_logic;
182
  signal vga_blue_o     : std_logic;
183 202 davidgb
 
184 200 davidgb
  signal serial_clk_unused : std_logic;
185 165 davidgb
  -- timer
186
  signal timer_data_out : std_logic_vector(7 downto 0);
187
  signal timer_cs       : std_logic;
188
  signal timer_irq      : std_logic;
189
 
190
  -- trap
191
  signal trap_cs        : std_logic;
192
  signal trap_data_out  : std_logic_vector(7 downto 0);
193
  signal trap_irq       : std_logic;
194
 
195
  signal rst_i         : std_logic;     -- internal reset signal
196 187 davidgb
  signal clk_i         : std_logic;     -- internal master clock signal
197 165 davidgb
 
198 196 davidgb
  signal CountL        : std_logic_vector(25 downto 0);
199 165 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
200 200 davidgb
  signal Clk25         : std_logic;
201
  signal vga_clk       : std_logic;
202 187 davidgb
 
203
component btn_debounce
204
    Port ( BTN_I : in  STD_LOGIC_VECTOR (3 downto 0);
205
           CLK : in  STD_LOGIC;
206
           BTN_O : out  STD_LOGIC_VECTOR (3 downto 0));
207
end component;
208
 
209 165 davidgb
 
210
-----------------------------------------------------------------
211
--
212
-- CPU09 CPU core
213
--
214
-----------------------------------------------------------------
215
 
216
component cpu09
217
  port (
218
    clk:      in  std_logic;
219
    rst:      in  std_logic;
220
    vma:      out std_logic;
221
    addr:     out std_logic_vector(15 downto 0);
222
    rw:       out std_logic;     -- Asynchronous memory interface
223
    data_out: out std_logic_vector(7 downto 0);
224
    data_in:  in  std_logic_vector(7 downto 0);
225
    irq:      in  std_logic;
226
    firq:     in  std_logic;
227
    nmi:      in  std_logic;
228
    halt:     in  std_logic;
229
    hold:     in  std_logic
230
  );
231
end component;
232
 
233
----------------------------------------
234
--
235
-- 4K Block RAM Monitor ROM
236
-- $F000 - $FFFF
237
--
238
----------------------------------------
239
 
240
component mon_rom
241
  Port (
242
    clk   : in  std_logic;
243
    rst   : in  std_logic;
244
    cs    : in  std_logic;
245
    rw    : in  std_logic;
246
    addr  : in  std_logic_vector (11 downto 0);
247
    data_out : out std_logic_vector (7 downto 0);
248
    data_in : in  std_logic_vector (7 downto 0)
249
  );
250
end component;
251
 
252
----------------------------------------
253
--
254
-- 8KBytes Block RAM for FLEX9
255
-- $C000 - $DFFF
256
--
257
----------------------------------------
258
 
259
component flex_ram
260
  Port (
261
    clk      : in  std_logic;
262
    rst      : in  std_logic;
263
    cs       : in  std_logic;
264
    rw       : in  std_logic;
265
    addr     : in  std_logic_vector (12 downto 0);
266
    data_out    : out std_logic_vector (7 downto 0);
267
    data_in    : in  std_logic_vector (7 downto 0)
268
  );
269
end component;
270 177 davidgb
 
271
----------------------------------------
272
--
273
-- 32KBytes Block RAM 0000
274
-- $0000 - $7FFF
275
--
276
----------------------------------------
277 165 davidgb
 
278 177 davidgb
component ram_32k
279
  Port (
280
    clk      : in  std_logic;
281
    rst      : in  std_logic;
282
    cs       : in  std_logic;
283
    rw       : in  std_logic;
284
    addr     : in  std_logic_vector (14 downto 0);
285
    data_out    : out std_logic_vector (7 downto 0);
286
    data_in    : in  std_logic_vector (7 downto 0)
287
  );
288
end component;
289
 
290
 
291
----------------------------------------
292
--
293
-- 16KBytes Block RAM 8000
294
-- $8000 - $BFFF
295
--
296
----------------------------------------
297
 
298
component ram_16k
299
  Port (
300
    clk      : in  std_logic;
301
    rst      : in  std_logic;
302
    cs       : in  std_logic;
303
    rw       : in  std_logic;
304
    addr     : in  std_logic_vector (13 downto 0);
305
    data_out    : out std_logic_vector (7 downto 0);
306
    data_in    : in  std_logic_vector (7 downto 0)
307
  );
308
end component;
309
 
310 165 davidgb
-----------------------------------------------------------------
311
--
312
-- 6850 Compatible ACIA / UART
313
--
314
-----------------------------------------------------------------
315
 
316
component acia6850
317
  port (
318
    clk      : in  Std_Logic;  -- System Clock
319
    rst      : in  Std_Logic;  -- Reset input (active high)
320
    cs       : in  Std_Logic;  -- miniUART Chip Select
321
    rw       : in  Std_Logic;  -- Read / Not Write
322
    addr     : in  Std_Logic;  -- Register Select
323
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
324
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
325
    irq      : out Std_Logic;  -- Interrupt
326
    RxC      : in  Std_Logic;  -- Receive Baud Clock
327
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
328
    RxD      : in  Std_Logic;  -- Receive Data
329
    TxD      : out Std_Logic;  -- Transmit Data
330
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
331
    CTS_n    : in  Std_Logic;  -- Clear To Send
332
    RTS_n    : out Std_Logic   -- Request To send
333
  );
334
end component;
335
 
336
-----------------------------------------------------------------
337
--
338
-- ACIA Clock divider
339
--
340
-----------------------------------------------------------------
341
 
342
component ACIA_Clock
343
  generic (
344
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
345
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
346
  );
347
  port (
348
    clk      : in  Std_Logic;  -- System Clock Input
349
    ACIA_clk : out Std_logic   -- ACIA Clock output
350
  );
351
end component;
352 200 davidgb
 
353
 
354
----------------------------------------
355
--
356
-- Video Display Unit.
357
--
358
----------------------------------------
359 165 davidgb
 
360 200 davidgb
component vdu8
361
  generic(
362
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
363
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
364
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
365
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
366
    VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
367
    VGA_LIN_PER_CHAR       : integer := 16; -- LINES
368
    VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
369
    VGA_HOR_SYNC           : integer := 96; -- PIXELS
370
    VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
371
    VGA_VER_BACK_PORCH     : integer := 13; -- LINES
372
    VGA_VER_SYNC           : integer := 2;  -- LINES
373
    VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
374
  );
375
  port(
376
    -- control register interface
377
    vdu_clk      : in  std_logic;  -- CPU Clock - 25MHz
378
    vdu_rst      : in  std_logic;
379
    vdu_cs       : in  std_logic;
380
    vdu_rw       : in  std_logic;
381
    vdu_addr     : in  std_logic_vector(2 downto 0);
382
    vdu_data_in  : in  std_logic_vector(7 downto 0);
383
    vdu_data_out : out std_logic_vector(7 downto 0);
384
 
385
    -- vga port connections
386
    vga_clk      : in  std_logic; -- VGA Pixel Clock - 25 MHz
387
    vga_red_o    : out std_logic;
388
    vga_green_o  : out std_logic;
389 202 davidgb
    vga_blue_o   : out std_logic;
390 200 davidgb
    vga_hsync_o  : out std_logic;
391
    vga_vsync_o  : out std_logic
392
  );
393
end component;
394
 
395
 
396 165 davidgb
----------------------------------------
397
--
398
-- Timer module
399
--
400
----------------------------------------
401
 
402
component timer
403
  port (
404
    clk       : in std_logic;
405
    rst       : in std_logic;
406
    cs        : in std_logic;
407
    rw        : in std_logic;
408
    addr      : in std_logic;
409
    data_in   : in std_logic_vector(7 downto 0);
410
    data_out  : out std_logic_vector(7 downto 0);
411
    irq       : out std_logic
412
  );
413
end component;
414
 
415
------------------------------------------------------------
416
--
417
-- Bus Trap logic
418
--
419
------------------------------------------------------------
420
 
421
component trap
422
  port (
423
    clk        : in  std_logic;
424
    rst        : in  std_logic;
425
    cs         : in  std_logic;
426
    rw         : in  std_logic;
427
    vma        : in  std_logic;
428
    addr       : in  std_logic_vector(15 downto 0);
429
    data_in    : in  std_logic_vector(7 downto 0);
430
    data_out   : out std_logic_vector(7 downto 0);
431
    irq        : out std_logic
432
  );
433
end component;
434
 
435
----------------------------------------
436
--
437
-- Dynamic Address Translation Registers
438
--
439
----------------------------------------
440
 
441
component dat_ram
442
  port (
443
    clk      : in  std_logic;
444
    rst      : in  std_logic;
445
    cs       : in  std_logic;
446
    rw       : in  std_logic;
447
    addr_lo  : in  std_logic_vector(3 downto 0);
448
    addr_hi  : in  std_logic_vector(3 downto 0);
449
    data_in  : in  std_logic_vector(7 downto 0);
450
    data_out : out std_logic_vector(7 downto 0)
451
  );
452
end component;
453 187 davidgb
 
454 165 davidgb
--
455
-- Clock buffer
456
--
457
 
458
component BUFG
459
   Port (
460
     i: in std_logic;
461
     o: out std_logic
462
  );
463
end component;
464
 
465 187 davidgb
begin
466 177 davidgb
 
467 187 davidgb
  --
468
  -- pushbutton debounce
469
  --
470
  my_singlestep: btn_debounce
471
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
472
 
473 193 davidgb
  RESET      <= pbtn(0); -- Right PB
474
  NMI        <= pbtn(1); -- Center PB
475 187 davidgb
 
476
  --
477
  -- Generate CPU & Pixel Clock from Memory Clock
478
  --
479 196 davidgb
 
480
  my_prescaler : process( clk_i, clk_count )
481
  begin
482
    if rising_edge( clk_i ) then
483
      if clk_count = 0 then
484
        clk_count <= CPU_CLK_DIV-1;
485
      else
486
        clk_count <= clk_count - 1;
487 187 davidgb
      end if;
488 196 davidgb
      if clk_count = 0 then
489
         clk25 <= '0';
490
      elsif clk_count = (CPU_CLK_DIV/2) then
491
         clk25 <= '1';
492
      end if;
493
    end if;
494
  end process;
495 187 davidgb
 
496
  --
497
  -- Reset button and reset timer
498
  --
499 193 davidgb
  my_switch_assignments : process( rst_i, RESET)
500 187 davidgb
  begin
501 193 davidgb
    rst_i <= RESET;
502 187 davidgb
    cpu_reset <= rst_i;
503
  end process;
504
 
505
  clk_i <= CLKA;
506
 
507 165 davidgb
  -----------------------------------------------------------------------------
508
  -- Instantiation of internal components
509
  -----------------------------------------------------------------------------
510
 
511
  my_cpu : cpu09
512
    port map (
513
      clk       => cpu_clk,
514
      rst       => cpu_reset,
515
      vma       => cpu_vma,
516
      addr      => cpu_addr(15 downto 0),
517
      rw        => cpu_rw,
518
      data_out  => cpu_data_out,
519
      data_in   => cpu_data_in,
520
      irq       => cpu_irq,
521
      firq      => cpu_firq,
522
      nmi       => cpu_nmi,
523
      halt      => cpu_halt,
524
      hold      => cpu_hold
525
    );
526
 
527
  my_rom : mon_rom
528
    port map (
529
      clk   => cpu_clk,
530
      rst   => cpu_reset,
531
      cs    => rom_cs,
532
      rw    => '1',
533
      addr  => cpu_addr(11 downto 0),
534
      data_in => cpu_data_out,
535
      data_out => rom_data_out
536
    );
537
 
538
  my_flex : flex_ram
539
    port map (
540
      clk       => cpu_clk,
541
      rst       => cpu_reset,
542
      cs        => flex_cs,
543
      rw        => cpu_rw,
544
      addr      => cpu_addr(12 downto 0),
545
      data_out     => flex_data_out,
546
      data_in     => cpu_data_out
547 177 davidgb
    );
548
 
549
  my_32k : ram_32k
550
    port map (
551
      clk       => cpu_clk,
552
      rst       => cpu_reset,
553
      cs        => ram1_cs,
554
      rw        => cpu_rw,
555
      addr      => cpu_addr(14 downto 0),
556
      data_out     => ram1_data_out,
557
      data_in     => cpu_data_out
558
    );
559
 
560
  my_16k : ram_16k
561
    port map (
562
      clk       => cpu_clk,
563
      rst       => cpu_reset,
564
      cs        => ram2_cs,
565
      rw        => cpu_rw,
566
      addr      => cpu_addr(13 downto 0),
567
      data_out     => ram2_data_out,
568
      data_in     => cpu_data_out
569
    );
570
 
571 165 davidgb
  my_acia  : acia6850
572
    port map (
573
      clk       => cpu_clk,
574
      rst       => cpu_reset,
575
      cs        => acia_cs,
576
      rw        => cpu_rw,
577
      addr      => cpu_addr(0),
578
      data_in   => cpu_data_out,
579
      data_out  => acia_data_out,
580
      irq       => acia_irq,
581
      RxC       => acia_clk,
582
      TxC       => acia_clk,
583 193 davidgb
      RxD       => RXD,
584
      TxD       => TXD,
585
      DCD_n     => DCD_n,
586
      CTS_n     => CTS_n,
587
      RTS_n     => RTS_n
588
    );
589
 
590
  --
591
  -- RS232 signals:
592
  --
593 199 davidgb
  my_acia_assignments : process( RS232_RXD, RS232_CTS,
594 196 davidgb
                                 TXD, RTS_n )
595 193 davidgb
  begin
596
    RXD       <= RS232_RXD;
597 199 davidgb
    CTS_n     <= RS232_CTS;
598 193 davidgb
    DCD_n     <= '0';
599
    RS232_TXD <= TXD;
600 199 davidgb
    RS232_RTS <= RTS_n;
601 193 davidgb
  end process;
602 187 davidgb
 
603 165 davidgb
  my_ACIA_Clock : ACIA_Clock
604
    generic map(
605 187 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
606 165 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
607
    )
608
    port map(
609 193 davidgb
      clk        => clk_i,
610 165 davidgb
      acia_clk   => acia_clk
611
    );
612 200 davidgb
 
613
  ----------------------------------------
614
  --
615
  -- Video Display Unit instantiation
616
  --
617
  ----------------------------------------
618
  my_vdu : vdu8
619
    generic map(
620
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
621
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
622
      VGA_HOR_CHARS          => 80, -- CHARACTERS
623
      VGA_VER_CHARS          => 25, -- CHARACTERS
624
      VGA_PIX_PER_CHAR       => 8,  -- PIXELS
625
      VGA_LIN_PER_CHAR       => 16, -- LINES
626
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
627
      VGA_HOR_SYNC           => 96, -- PIXELS
628
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
629
      VGA_VER_BACK_PORCH     => 13, -- LINES
630
      VGA_VER_SYNC           => 2,  -- LINES
631
      VGA_VER_FRONT_PORCH    => 35  -- LINES
632
    )
633
    port map(
634
      -- Control Registers
635
      vdu_clk       => cpu_clk,               -- 12.5 MHz System Clock in
636
      vdu_rst       => cpu_reset,
637
      vdu_cs        => vdu_cs,
638
      vdu_rw        => cpu_rw,
639
      vdu_addr      => cpu_addr(2 downto 0),
640
      vdu_data_in   => cpu_data_out,
641
      vdu_data_out  => vdu_data_out,
642
      -- vga port connections
643
      vga_clk       => vga_clk,               -- 25 MHz VDU pixel clock
644 202 davidgb
      vga_red_o     => vga_red_o,
645
      vga_green_o   => vga_green_o,
646
      vga_blue_o    => vga_blue_o,
647
      vga_hsync_o   => VGA_hsync_n,
648
      vga_vsync_o   => VGA_vsync_n
649 200 davidgb
   );
650 202 davidgb
  --
651
  -- VGA ouputs
652
  --
653
  my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
654
  begin
655
    VGA_red(0)   <= vga_red_o;
656
    VGA_red(1)   <= vga_red_o;
657
    VGA_red(2)   <= vga_red_o;
658
    VGA_red(3)   <= vga_red_o;
659
    VGA_green(0) <= vga_green_o;
660
    VGA_green(1) <= vga_green_o;
661
    VGA_green(2) <= vga_green_o;
662
    VGA_green(3) <= vga_green_o;
663
    VGA_blue(0)  <= vga_blue_o;
664
    VGA_blue(1)  <= vga_blue_o;
665
    VGA_blue(2)  <= vga_blue_o;
666
    VGA_blue(3)  <= vga_blue_o;
667
  end process;
668
 
669 165 davidgb
 
670
  ----------------------------------------
671
  --
672
  -- Timer Module
673
  --
674
  ----------------------------------------
675
  my_timer  : timer
676
    port map (
677
      clk       => cpu_clk,
678
      rst       => cpu_reset,
679
      cs        => timer_cs,
680
      rw        => cpu_rw,
681
      addr      => cpu_addr(0),
682
      data_in   => cpu_data_out,
683
      data_out  => timer_data_out,
684
      irq       => timer_irq
685
    );
686
 
687
  ----------------------------------------
688
  --
689
  -- Bus Trap Interrupt logic
690
  --
691
  ----------------------------------------
692
  my_trap : trap
693
    port map (
694
      clk        => cpu_clk,
695
      rst        => cpu_reset,
696
      cs         => trap_cs,
697
      rw         => cpu_rw,
698
      vma        => cpu_vma,
699
      addr       => cpu_addr,
700
      data_in    => cpu_data_out,
701
      data_out   => trap_data_out,
702
      irq        => trap_irq
703
    );
704
 
705
  my_dat : dat_ram
706
    port map (
707
      clk       => cpu_clk,
708
      rst       => cpu_reset,
709
      cs        => dat_cs,
710
      rw        => cpu_rw,
711
      addr_hi   => cpu_addr(15 downto 12),
712
      addr_lo   => cpu_addr(3 downto 0),
713
      data_in   => cpu_data_out,
714
      data_out  => dat_addr(7 downto 0)
715
    );
716
 
717
  cpu_clk_buffer : BUFG
718
    port map(
719
      i => Clk25,
720
      o => cpu_clk
721
    );
722 202 davidgb
  vga_clk_buffer : BUFG
723
    port map(
724
      i => Clk25,
725
      o => vga_clk
726
    );
727 165 davidgb
  ----------------------------------------------------------------------
728
  --
729
  -- Process to decode memory map
730
  --
731
  ----------------------------------------------------------------------
732
 
733
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
734
                     dat_addr,
735
                     rom_data_out,
736
                     flex_data_out,
737
                     acia_data_out,
738 200 davidgb
                     vdu_data_out,
739 165 davidgb
                     timer_data_out,
740
                     trap_data_out,
741 177 davidgb
                     ram1_data_out, ram2_data_out
742 165 davidgb
                     )
743
  begin
744
    cpu_data_in <= (others=>'0');
745
    dat_cs      <= '0';
746
    rom_cs      <= '0';
747
    flex_cs     <= '0';
748 200 davidgb
    acia_cs     <= '0';
749
    vdu_cs      <= '0';
750 165 davidgb
    timer_cs    <= '0';
751
    trap_cs     <= '0';
752 177 davidgb
    ram1_cs      <= '0';
753
    ram2_cs      <= '0';
754
 
755 165 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
756
      cpu_data_in <= rom_data_out;
757
      dat_cs      <= cpu_vma;              -- write DAT
758
      rom_cs      <= cpu_vma;              -- read  ROM
759
 
760
    --
761
    -- Sys09Bug Monitor ROM $F000 - $FFFF
762
    --
763
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
764
      cpu_data_in <= rom_data_out;
765
      rom_cs      <= cpu_vma;
766
 
767
    --
768
    -- IO Devices $E000 - $E7FF
769
    --
770
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
771
      case cpu_addr(11 downto 8) is
772
        --
773
        -- SWTPC peripherals from $E000 to $E0FF
774
        --
775
        when "0000" =>
776
          case cpu_addr(7 downto 4) is
777
          --
778
          -- Console Port ACIA $E000 - $E00F
779
          --
780
            when "0000" => -- $E000
781
              cpu_data_in <= acia_data_out;
782
              acia_cs     <= cpu_vma;
783
 
784
            --
785
            -- Reserved
786
            -- Floppy Disk Controller port $E010 - $E01F
787
            --
788
            --
789 200 davidgb
            -- VDU port $E030 - $E03F
790
            --
791
            when "0011" => -- $E030
792
              cpu_data_in <= vdu_data_out;
793
              vdu_cs      <= cpu_vma;
794
 
795
            --
796 165 davidgb
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
797
            --
798
            when "0100" => -- $E040
799
              cpu_data_in <= (others=> '0');
800
 
801
            --
802
            -- Timer $E050 - $E05F
803
            --
804
            when "0101" => -- $E050
805
              cpu_data_in <= timer_data_out;
806
              timer_cs    <= cpu_vma;
807
 
808
            --
809
            -- Bus Trap Logic $E060 - $E06F
810
            --
811
            when "0110" => -- $E060
812
              cpu_data_in <= trap_data_out;
813
              trap_cs     <= cpu_vma;
814
 
815
            --
816
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
817
            --
818
 
819
            --
820
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
821
            --
822
 
823
            --
824
            -- Remaining 6 slots reserved for non SWTPc Peripherals
825
            --
826
            when others => -- $E0A0 to $E0FF
827
              null;
828
          end case;
829
 
830
        --
831
        -- $E200 to $EFFF reserved for future use
832
        --
833
        when others =>
834
           null;
835
      end case;
836 177 davidgb
 
837
    --
838 193 davidgb
    -- Block RAM (32k) $00000 - $07FFF
839 177 davidgb
    --
840 193 davidgb
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
841 177 davidgb
      cpu_data_in <= ram1_data_out;
842
      ram1_cs     <= cpu_vma;
843
 
844
    --
845 193 davidgb
    -- Block RAM (16k) $08000 - $0BFFF
846 177 davidgb
    --
847 193 davidgb
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
848 177 davidgb
      cpu_data_in <= ram2_data_out;
849
      ram2_cs     <= cpu_vma;
850 165 davidgb
 
851
    --
852 193 davidgb
    -- Flex RAM (8k) $0C000 - $0DFFF
853
    --
854
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
855
      cpu_data_in <= flex_data_out;
856
      flex_cs     <= cpu_vma;
857
 
858
    --
859 165 davidgb
    -- Everything else is RAM
860
    --
861
    else
862 177 davidgb
      cpu_data_in <= (others => '0');
863
      ram3_cs      <= cpu_vma;
864 165 davidgb
    end if;
865
 
866
  end process;
867
 
868
  --
869
  -- Interrupts and other bus control signals
870
  --
871 193 davidgb
  interrupts : process( NMI,
872 165 davidgb
                      acia_irq,
873
                      trap_irq,
874
                      timer_irq
875
                      )
876
  begin
877
    cpu_irq    <= acia_irq;
878 193 davidgb
    cpu_nmi    <= trap_irq or NMI;
879 165 davidgb
    cpu_firq   <= timer_irq;
880
    cpu_halt   <= '0';
881 177 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
882 165 davidgb
  end process;
883
 
884
  --
885 187 davidgb
  -- Flash 7 segment LEDS
886 165 davidgb
  --
887 187 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
888 165 davidgb
  begin
889 187 davidgb
    if rst_i = '1' then
890 196 davidgb
         CountL <= "00000000000000000000000000";
891 187 davidgb
    elsif rising_edge(clk_i) then
892
         CountL <= CountL + 1;
893 165 davidgb
    end if;
894 187 davidgb
    --S(7 downto 0) <= CountL(23 downto 16);
895 165 davidgb
  end process;
896
 
897 193 davidgb
  status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
898 187 davidgb
  begin
899
    case sw is
900 196 davidgb
         when "1000" =>
901 187 davidgb
           led(3 downto 0) <= cpu_addr(3 downto 0);
902 196 davidgb
    when "1001" =>
903 187 davidgb
           led(3 downto 0) <= cpu_addr(7 downto 4);
904 196 davidgb
         when "1010" =>
905 187 davidgb
           led(3 downto 0) <= cpu_addr(11 downto 8);
906 196 davidgb
    when "1011" =>
907 187 davidgb
           led(3 downto 0) <= cpu_addr(15 downto 12);
908 196 davidgb
    when "1100" =>
909 187 davidgb
           led(3 downto 0) <= cpu_data_in(3 downto 0);
910 196 davidgb
    when "1101" =>
911
           led(3 downto 0) <= cpu_data_in(7 downto 4);
912
    when "0000" =>
913
           led(3) <= '0';
914
      led(2) <= CountL(24);
915
                led(1) <= cpu_reset;
916
                led(0) <= NMI;
917 187 davidgb
    when others => led(3 downto 0) <= (others => '0');
918
         end case;
919 165 davidgb
  end process;
920
 
921
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
922
--                      cpu_halt, cpu_hold,
923
--                      cpu_firq, cpu_irq, cpu_nmi,
924
--                      cpu_addr, cpu_data_out, cpu_data_in )
925
--  begin
926
--    cpu_reset_o    <= cpu_reset;
927
--    cpu_clk_o      <= cpu_clk;
928
--    cpu_rw_o       <= cpu_rw;
929
--    cpu_vma_o      <= cpu_vma;
930
--    cpu_halt_o     <= cpu_halt;
931
--    cpu_hold_o     <= cpu_hold;
932
--    cpu_firq_o     <= cpu_firq;
933
--    cpu_irq_o      <= cpu_irq;
934
--    cpu_nmi_o      <= cpu_nmi;
935
--    cpu_addr_o     <= cpu_addr;
936
--    cpu_data_out_o <= cpu_data_out;
937
--    cpu_data_in_o  <= cpu_data_in;
938
--  end process;
939
 
940
end rtl; --===================== End of architecture =======================--
941
 

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