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[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [secd_ram_controller_hans.vhd] - Blame information for rev 105

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-- secd_ram_controller.vhd
--
-- Multiplex the external 16 bit SRAM to the 32 bit interface required
-- by the CPU and provide for an 8 bit backside port for the 6809 to
-- read and write SECD memory
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
entity secd_ram_controller is
  port(
    clk              : in std_logic;
    reset            : in std_logic;
 
    secd_stopped     : in std_logic;
 
                                        -- Internal interface to SECD (16k x 32)
    din32            : in std_logic_vector(31 downto 0);
    dout32           : out std_logic_vector(31 downto 0);
    addr32           : in std_logic_vector(13 downto 0);
    read32_enable    : in std_logic;
    write32_enable   : in std_logic;
    busy32           : out std_logic;
 
                                        -- Internal interface to 6809 (64k x 8)
    clk8             : in std_logic;
    din8             : in std_logic_vector(7 downto 0);
    dout8            : out std_logic_vector(7 downto 0);
    addr8            : in std_logic_vector(15 downto 0);
    rw8              : in std_logic;
    cs8_ram          : in std_logic;
    hold8            : out std_logic;
    cs8_cf           : in std_logic;
 
                                        -- External interface
    ram_oen          : out std_logic;
    ram_cen          : out std_logic;
    ram_wen          : out std_logic;
    ram_io           : inout std_logic_vector(15 downto 0);
    ram_a            : out std_logic_vector(20 downto 1);
    ram_bhen         : out std_logic;
    ram_blen         : out std_logic
    );
end;
 
architecture external_ram of secd_ram_controller is
 
  type hold_state_type is ( hold_release_state, hold_request_state );
 
  signal cf_hold_state : hold_state_type;
 
  signal cf_release  : std_logic;
  signal cf_count    : std_logic_vector(3 downto 0);
 
  type state_type is (idle,
                      read32_high, read32_high_deselect, read32_low,
                      write32_high, write32_high_deselect, write32_low,
                      read8_ram, write8_ram, read8_cf, write8_cf );
 
  signal state : state_type;
  signal dout8_en : std_logic;
 
begin
 
 
  secd_ram_process : process( clk, state, reset,
                              read32_enable, write32_enable, addr32, din32,
                              cs8_ram, rw8, addr8, din8 )
  begin
    if reset = '1' then
        ram_a(20 downto 1) <= (others => '0');
        ram_cen  <= '1';
        ram_oen  <= '1';
        ram_wen  <= '1';
        ram_bhen <= '1';
        ram_blen <= '1';
        ram_io   <= (others => 'Z');
                  dout8_en <= '0';
        hold8    <= '0';
        busy32   <= '0';
        state    <= idle;
    elsif rising_edge(clk) then
      case state is
        when idle =>
          ram_a(20 downto 1) <= (others => '0');
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_bhen <= '1';
          ram_blen <= '1';
          ram_io   <= (others => 'Z');
          dout8_en <= '0';
          if read32_enable = '1' then
            ram_a(1) <= '0';
            ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
            ram_cen  <= '0';
            ram_oen  <= '0';
            ram_wen  <= '1';
            ram_bhen <= '0';
            ram_blen <= '0';
            hold8    <= cs8_ram or cs8_cf;
            busy32   <= '1';
            state    <= read32_high;
          elsif write32_enable = '1' then
            ram_a(1) <= '0';
            ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
            ram_cen  <= '0';
            ram_oen  <= '1';
            ram_wen  <= '0';
            ram_bhen <= '0';
            ram_blen <= '0';
            ram_io   <= din32(31 downto 16);
            hold8    <= cs8_ram or cs8_cf;
            busy32   <= '1';
            state <= write32_high;
          elsif (cs8_ram = '1') and (rw8 = '1') then
            ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
            ram_cen  <= '0';
            ram_oen  <= '0';
            ram_wen  <= '1';
            ram_bhen <= addr8(0);
            ram_blen <= not addr8(0);
            dout8_en <= '1';
            hold8    <= '0';
            busy32   <= '1';
            state    <= read8_ram;
          elsif (cs8_ram = '1') and (rw8 = '0') then
            ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
            ram_cen  <= '0';
            ram_oen  <= '1';
            ram_wen  <= '0';
            ram_bhen <= addr8(0);
            ram_blen <= not addr8(0);
            if addr8(0) = '0' then
              ram_io(15 downto 8) <= din8;
              ram_io( 7 downto 0) <= (others => 'Z');
            else
              ram_io(15 downto 8) <= (others => 'Z');
              ram_io( 7 downto 0) <= din8;
            end if;
            hold8    <= '0';
            busy32   <= '1';
            state    <= write8_ram;
          elsif (cs8_cf = '1') and (rw8 = '1') then
            ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
            dout8_en <= '1';
            busy32   <= '1';
            if cf_release = '1' then
              hold8  <= '0';
              state  <= read8_cf;
            else
              hold8  <= '1';
              state  <= idle;
            end if;
          elsif (cs8_cf = '1') and (rw8 = '0') then
            ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
            busy32   <= '1';
            if addr8(0) = '0' then
              ram_io(15 downto 8) <= din8;
              ram_io( 7 downto 0) <= (others => 'Z');
            else
              ram_io(15 downto 8) <= (others => 'Z');
              ram_io( 7 downto 0) <= din8;
            end if;
            if cf_release = '1' then
              hold8  <= '0';
              state  <= write8_cf;
            else
              hold8  <= '1';
              state  <= idle;
            end if;
          else
            hold8    <= '0';
            busy32   <= '0';
            state    <= idle;
          end if;
 
        when read32_high =>
          ram_a(1) <= '1';
          ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_bhen <= '1';
          ram_blen <= '1';
          ram_io   <= (others => 'Z');
                         dout32(31 downto 16) <= ram_io;
          busy32   <= '1';
          dout8_en <= '0';
          hold8    <= cs8_ram or cs8_cf;
          state    <= read32_high_deselect;
 
        when read32_high_deselect =>
          ram_a(1) <= '1';
          ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
          ram_cen  <= '0';
          ram_oen  <= '0';
          ram_wen  <= '1';
          ram_bhen <= '0';
          ram_blen <= '0';
          ram_io   <= (others => 'Z');
          busy32   <= '1';
          dout8_en <= '0';
          hold8    <= cs8_ram or cs8_cf;
          state    <= read32_low;
 
        when read32_low =>
          ram_a(1) <= '0';
          ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_bhen <= '1';
          ram_blen <= '1';
          ram_io   <= (others => 'Z');
                         dout32(15 downto 0) <= ram_io;
          busy32   <= '0';
          dout8_en <= '0';
          hold8    <= cs8_ram or cs8_cf;
          state    <= idle;
 
        when write32_high =>
          ram_a(1) <= '1';
          ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_bhen <= '1';
          ram_blen <= '1';
          ram_io   <= (others => 'Z');
          busy32   <= '1';
          dout8_en <= '0';
          hold8    <= cs8_ram or cs8_cf;
          state    <= write32_high_deselect;
 
        when write32_high_deselect =>
          ram_a(1) <= '1';
          ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
          ram_cen  <= '0';
          ram_oen  <= '1';
          ram_wen  <= '0';
          ram_bhen <= '0';
          ram_blen <= '0';
          ram_io   <= din32(15 downto 0);
          busy32   <= '1';
          dout8_en <= '0';
          hold8    <= cs8_ram or cs8_cf;
          state    <= write32_low;
 
        when write32_low =>
          ram_a(1) <= '0';
          ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_bhen <= '1';
          ram_blen <= '1';
          ram_io   <= (others => 'Z');
          busy32   <= '0';
          dout8_en <= '0';
          hold8    <= cs8_ram or cs8_cf;
          state    <= idle;
 
        when read8_ram =>
          ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_io   <= (others => 'Z');
          busy32   <= '0';
          dout8_en <= '0';
          hold8    <= '0';
          state    <= idle;
 
        when write8_ram =>
          ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_io(15 downto 0) <= (others => 'Z');
          busy32   <= '0';
          dout8_en <= '0';
          hold8    <= '0';
          state    <= idle;
 
        when read8_cf =>
          ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_bhen <= '1';
          ram_blen <= '1';
          ram_io   <= (others => 'Z');
          busy32   <= '0';
          dout8_en <= '0';
          hold8    <= '0';
          state    <= idle;
 
        when write8_cf =>
          ram_a(1) <= '1';
          ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
          ram_cen  <= '1';
          ram_oen  <= '1';
          ram_wen  <= '1';
          ram_bhen <= '1';
          ram_blen <= '1';
          busy32   <= '1';
          dout8_en <= '0';
          hold8    <= '0';
          state    <= idle;
 
        when others =>
          null;
 
      end case;
    end if;
  end process;
 
--
-- 8 Bit data bus output enable process
--
-- The point of this process is that data must be
-- passed through from the ram input,
-- and not clocked, so it is ready for the CPU
-- on the trailing clock edge
--  
dout8_selector : process( dout8_en, addr8, ram_io )
begin
    if dout8_en = '0' then
             dout8 <= ( others => '0' );
    else
        if addr8(0) = '0' then
            dout8 <= ram_io(15 downto 8);
        else
            dout8 <= ram_io(7 downto 0);
        end if;
    end if;
end process;
 
--
-- Hold CF access       for a few cycles
-- synchronize with the CPU clock
-- hold release is set on the rising edge
-- of the CPU clock so that you have one
-- VGA clock cycle to return to the idle state
-- of the secd_ram_process state machine.
--
  cf_hold_proc: process( clk8, reset )
  begin
    if reset = '1' then
      cf_release    <= '0';
      cf_count      <= "0000";
      cf_hold_state <= hold_release_state;
    elsif rising_edge( clk8 ) then
      case cf_hold_state is
        when hold_release_state =>
          cf_release <= '0';
          if cs8_cf = '1' then
            cf_count      <= "0011";
            cf_hold_state <= hold_request_state;
          end if;
 
        when hold_request_state =>
          cf_count <= cf_count - "0001";
          if cf_count = "0000" then
            cf_release    <= '1';
            cf_hold_state <= hold_release_state;
          end if;
        when others =>
          null;
      end case;
    end if;
 
  end process;
 
end;

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[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [secd_ram_controller_hans.vhd] - Blame information for rev 105

Line No.	Rev	Author	Line
1	105	davidgb	`-- secd_ram_controller.vhd`
2			`--`
3			`-- Multiplex the external 16 bit SRAM to the 32 bit interface required`
4			`-- by the CPU and provide for an 8 bit backside port for the 6809 to`
5			`-- read and write SECD memory`
6
7			`library ieee;`
8
9			`use ieee.std_logic_1164.all;`
10			`use ieee.numeric_std.all;`
11			`use ieee.std_logic_unsigned.all;`
12
13			`entity secd_ram_controller is`
14			`port(`
15			`clk : in std_logic;`
16			`reset : in std_logic;`
17
18			`secd_stopped : in std_logic;`
19
20			`-- Internal interface to SECD (16k x 32)`
21			`din32 : in std_logic_vector(31 downto 0);`
22			`dout32 : out std_logic_vector(31 downto 0);`
23			`addr32 : in std_logic_vector(13 downto 0);`
24			`read32_enable : in std_logic;`
25			`write32_enable : in std_logic;`
26			`busy32 : out std_logic;`
27
28			`-- Internal interface to 6809 (64k x 8)`
29			`clk8 : in std_logic;`
30			`din8 : in std_logic_vector(7 downto 0);`
31			`dout8 : out std_logic_vector(7 downto 0);`
32			`addr8 : in std_logic_vector(15 downto 0);`
33			`rw8 : in std_logic;`
34			`cs8_ram : in std_logic;`
35			`hold8 : out std_logic;`
36			`cs8_cf : in std_logic;`
37
38			`-- External interface`
39			`ram_oen : out std_logic;`
40			`ram_cen : out std_logic;`
41			`ram_wen : out std_logic;`
42			`ram_io : inout std_logic_vector(15 downto 0);`
43			`ram_a : out std_logic_vector(20 downto 1);`
44			`ram_bhen : out std_logic;`
45			`ram_blen : out std_logic`
46			`);`
47			`end;`
48
49			`architecture external_ram of secd_ram_controller is`
50
51			`type hold_state_type is ( hold_release_state, hold_request_state );`
52
53			`signal cf_hold_state : hold_state_type;`
54
55			`signal cf_release : std_logic;`
56			`signal cf_count : std_logic_vector(3 downto 0);`
57
58			`type state_type is (idle,`
59			`read32_high, read32_high_deselect, read32_low,`
60			`write32_high, write32_high_deselect, write32_low,`
61			`read8_ram, write8_ram, read8_cf, write8_cf );`
62
63			`signal state : state_type;`
64			`signal dout8_en : std_logic;`
65
66			`begin`
67
68
69			`secd_ram_process : process( clk, state, reset,`
70			`read32_enable, write32_enable, addr32, din32,`
71			`cs8_ram, rw8, addr8, din8 )`
72			`begin`
73			`if reset = '1' then`
74			`ram_a(20 downto 1) <= (others => '0');`
75			`ram_cen <= '1';`
76			`ram_oen <= '1';`
77			`ram_wen <= '1';`
78			`ram_bhen <= '1';`
79			`ram_blen <= '1';`
80			`ram_io <= (others => 'Z');`
81			`dout8_en <= '0';`
82			`hold8 <= '0';`
83			`busy32 <= '0';`
84			`state <= idle;`
85			`elsif rising_edge(clk) then`
86			`case state is`
87			`when idle =>`
88			`ram_a(20 downto 1) <= (others => '0');`
89			`ram_cen <= '1';`
90			`ram_oen <= '1';`
91			`ram_wen <= '1';`
92			`ram_bhen <= '1';`
93			`ram_blen <= '1';`
94			`ram_io <= (others => 'Z');`
95			`dout8_en <= '0';`
96			`if read32_enable = '1' then`
97			`ram_a(1) <= '0';`
98			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
99			`ram_cen <= '0';`
100			`ram_oen <= '0';`
101			`ram_wen <= '1';`
102			`ram_bhen <= '0';`
103			`ram_blen <= '0';`
104			`hold8 <= cs8_ram or cs8_cf;`
105			`busy32 <= '1';`
106			`state <= read32_high;`
107			`elsif write32_enable = '1' then`
108			`ram_a(1) <= '0';`
109			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
110			`ram_cen <= '0';`
111			`ram_oen <= '1';`
112			`ram_wen <= '0';`
113			`ram_bhen <= '0';`
114			`ram_blen <= '0';`
115			`ram_io <= din32(31 downto 16);`
116			`hold8 <= cs8_ram or cs8_cf;`
117			`busy32 <= '1';`
118			`state <= write32_high;`
119			`elsif (cs8_ram = '1') and (rw8 = '1') then`
120			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
121			`ram_cen <= '0';`
122			`ram_oen <= '0';`
123			`ram_wen <= '1';`
124			`ram_bhen <= addr8(0);`
125			`ram_blen <= not addr8(0);`
126			`dout8_en <= '1';`
127			`hold8 <= '0';`
128			`busy32 <= '1';`
129			`state <= read8_ram;`
130			`elsif (cs8_ram = '1') and (rw8 = '0') then`
131			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
132			`ram_cen <= '0';`
133			`ram_oen <= '1';`
134			`ram_wen <= '0';`
135			`ram_bhen <= addr8(0);`
136			`ram_blen <= not addr8(0);`
137			`if addr8(0) = '0' then`
138			`ram_io(15 downto 8) <= din8;`
139			`ram_io( 7 downto 0) <= (others => 'Z');`
140			`else`
141			`ram_io(15 downto 8) <= (others => 'Z');`
142			`ram_io( 7 downto 0) <= din8;`
143			`end if;`
144			`hold8 <= '0';`
145			`busy32 <= '1';`
146			`state <= write8_ram;`
147			`elsif (cs8_cf = '1') and (rw8 = '1') then`
148			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
149			`dout8_en <= '1';`
150			`busy32 <= '1';`
151			`if cf_release = '1' then`
152			`hold8 <= '0';`
153			`state <= read8_cf;`
154			`else`
155			`hold8 <= '1';`
156			`state <= idle;`
157			`end if;`
158			`elsif (cs8_cf = '1') and (rw8 = '0') then`
159			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
160			`busy32 <= '1';`
161			`if addr8(0) = '0' then`
162			`ram_io(15 downto 8) <= din8;`
163			`ram_io( 7 downto 0) <= (others => 'Z');`
164			`else`
165			`ram_io(15 downto 8) <= (others => 'Z');`
166			`ram_io( 7 downto 0) <= din8;`
167			`end if;`
168			`if cf_release = '1' then`
169			`hold8 <= '0';`
170			`state <= write8_cf;`
171			`else`
172			`hold8 <= '1';`
173			`state <= idle;`
174			`end if;`
175			`else`
176			`hold8 <= '0';`
177			`busy32 <= '0';`
178			`state <= idle;`
179			`end if;`
180
181			`when read32_high =>`
182			`ram_a(1) <= '1';`
183			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
184			`ram_cen <= '1';`
185			`ram_oen <= '1';`
186			`ram_wen <= '1';`
187			`ram_bhen <= '1';`
188			`ram_blen <= '1';`
189			`ram_io <= (others => 'Z');`
190			`dout32(31 downto 16) <= ram_io;`
191			`busy32 <= '1';`
192			`dout8_en <= '0';`
193			`hold8 <= cs8_ram or cs8_cf;`
194			`state <= read32_high_deselect;`
195
196			`when read32_high_deselect =>`
197			`ram_a(1) <= '1';`
198			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
199			`ram_cen <= '0';`
200			`ram_oen <= '0';`
201			`ram_wen <= '1';`
202			`ram_bhen <= '0';`
203			`ram_blen <= '0';`
204			`ram_io <= (others => 'Z');`
205			`busy32 <= '1';`
206			`dout8_en <= '0';`
207			`hold8 <= cs8_ram or cs8_cf;`
208			`state <= read32_low;`
209
210			`when read32_low =>`
211			`ram_a(1) <= '0';`
212			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
213			`ram_cen <= '1';`
214			`ram_oen <= '1';`
215			`ram_wen <= '1';`
216			`ram_bhen <= '1';`
217			`ram_blen <= '1';`
218			`ram_io <= (others => 'Z');`
219			`dout32(15 downto 0) <= ram_io;`
220			`busy32 <= '0';`
221			`dout8_en <= '0';`
222			`hold8 <= cs8_ram or cs8_cf;`
223			`state <= idle;`
224
225			`when write32_high =>`
226			`ram_a(1) <= '1';`
227			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
228			`ram_cen <= '1';`
229			`ram_oen <= '1';`
230			`ram_wen <= '1';`
231			`ram_bhen <= '1';`
232			`ram_blen <= '1';`
233			`ram_io <= (others => 'Z');`
234			`busy32 <= '1';`
235			`dout8_en <= '0';`
236			`hold8 <= cs8_ram or cs8_cf;`
237			`state <= write32_high_deselect;`
238
239			`when write32_high_deselect =>`
240			`ram_a(1) <= '1';`
241			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
242			`ram_cen <= '0';`
243			`ram_oen <= '1';`
244			`ram_wen <= '0';`
245			`ram_bhen <= '0';`
246			`ram_blen <= '0';`
247			`ram_io <= din32(15 downto 0);`
248			`busy32 <= '1';`
249			`dout8_en <= '0';`
250			`hold8 <= cs8_ram or cs8_cf;`
251			`state <= write32_low;`
252
253			`when write32_low =>`
254			`ram_a(1) <= '0';`
255			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
256			`ram_cen <= '1';`
257			`ram_oen <= '1';`
258			`ram_wen <= '1';`
259			`ram_bhen <= '1';`
260			`ram_blen <= '1';`
261			`ram_io <= (others => 'Z');`
262			`busy32 <= '0';`
263			`dout8_en <= '0';`
264			`hold8 <= cs8_ram or cs8_cf;`
265			`state <= idle;`
266
267			`when read8_ram =>`
268			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
269			`ram_cen <= '1';`
270			`ram_oen <= '1';`
271			`ram_wen <= '1';`
272			`ram_io <= (others => 'Z');`
273			`busy32 <= '0';`
274			`dout8_en <= '0';`
275			`hold8 <= '0';`
276			`state <= idle;`
277
278			`when write8_ram =>`
279			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
280			`ram_cen <= '1';`
281			`ram_oen <= '1';`
282			`ram_wen <= '1';`
283			`ram_io(15 downto 0) <= (others => 'Z');`
284			`busy32 <= '0';`
285			`dout8_en <= '0';`
286			`hold8 <= '0';`
287			`state <= idle;`
288
289			`when read8_cf =>`
290			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
291			`ram_cen <= '1';`
292			`ram_oen <= '1';`
293			`ram_wen <= '1';`
294			`ram_bhen <= '1';`
295			`ram_blen <= '1';`
296			`ram_io <= (others => 'Z');`
297			`busy32 <= '0';`
298			`dout8_en <= '0';`
299			`hold8 <= '0';`
300			`state <= idle;`
301
302			`when write8_cf =>`
303			`ram_a(1) <= '1';`
304			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
305			`ram_cen <= '1';`
306			`ram_oen <= '1';`
307			`ram_wen <= '1';`
308			`ram_bhen <= '1';`
309			`ram_blen <= '1';`
310			`busy32 <= '1';`
311			`dout8_en <= '0';`
312			`hold8 <= '0';`
313			`state <= idle;`
314
315			`when others =>`
316			`null;`
317
318			`end case;`
319			`end if;`
320			`end process;`
321
322			`--`
323			`-- 8 Bit data bus output enable process`
324			`--`
325			`-- The point of this process is that data must be`
326			`-- passed through from the ram input,`
327			`-- and not clocked, so it is ready for the CPU`
328			`-- on the trailing clock edge`
329			`--`
330			`dout8_selector : process( dout8_en, addr8, ram_io )`
331			`begin`
332			`if dout8_en = '0' then`
333			`dout8 <= ( others => '0' );`
334			`else`
335			`if addr8(0) = '0' then`
336			`dout8 <= ram_io(15 downto 8);`
337			`else`
338			`dout8 <= ram_io(7 downto 0);`
339			`end if;`
340			`end if;`
341			`end process;`
342
343			`--`
344			`-- Hold CF access for a few cycles`
345			`-- synchronize with the CPU clock`
346			`-- hold release is set on the rising edge`
347			`-- of the CPU clock so that you have one`
348			`-- VGA clock cycle to return to the idle state`
349			`-- of the secd_ram_process state machine.`
350			`--`
351			`cf_hold_proc: process( clk8, reset )`
352			`begin`
353			`if reset = '1' then`
354			`cf_release <= '0';`
355			`cf_count <= "0000";`
356			`cf_hold_state <= hold_release_state;`
357			`elsif rising_edge( clk8 ) then`
358			`case cf_hold_state is`
359			`when hold_release_state =>`
360			`cf_release <= '0';`
361			`if cs8_cf = '1' then`
362			`cf_count <= "0011";`
363			`cf_hold_state <= hold_request_state;`
364			`end if;`
365
366			`when hold_request_state =>`
367			`cf_count <= cf_count - "0001";`
368			`if cf_count = "0000" then`
369			`cf_release <= '1';`
370			`cf_hold_state <= hold_release_state;`
371			`end if;`
372			`when others =>`
373			`null;`
374			`end case;`
375			`end if;`
376
377			`end process;`
378
379			`end;`