URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Xess_XuLA/] [iseconfig/] [System09_Xess_XuLA.projectmgr] - Blame information for rev 122

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         2
         /My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/XSASDRAM
         /My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/XSASDRAM/common
         /My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/my_keyboard - keyboard - rtl
         /My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/my_vdu - vdu8 - RTL
         /My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/u1 - XSASDRAMCntl - arch
         /XSASDRAMCntl - arch C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|xsasdramcntl.vhd
         /cpu09 - rtl C:|VHDL|System09_sandbox_JK|rtl|VHDL|cpu09.vhd
         /ps2_keyboard - rtl C:|VHDL|System09_sandbox_JK|rtl|VHDL|ps2_keyboard.vhd
      
      
         System09_Xess_XuLA
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001a8000000020000000000000000000000000000000064ffffffff000000810000000000000002000001a80000000100000000000000000000000100000000
      true
      System09_Xess_XuLA
   
   
      
         1
         Design Utilities/Compile HDL Simulation Libraries
      
      
         Compile HDL Simulation Libraries
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001e4000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e40000000100000000
      false
      Compile HDL Simulation Libraries
   
   
      
         1
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000263000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001970000000100000000
      false
      acia6850.vhd
   
   
      
         1
      
      
         sdramcntl.vhd
      
      0
      0
      000000ff000000000000000100000001000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
      false
      sdramcntl.vhd
   
   
      
         1
         Configure Target Device
         Design Utilities
         Implement Design/Map
         Implement Design/Map/Generate Post-Map Static Timing
         Implement Design/Place & Route
         Implement Design/Translate
         Synthesize - XST
         User Constraints
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001e4000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e40000000100000000
      false
      
   
   
      
         1
      
      
         Edit Constraints (Text)
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001e4000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e40000000100000000
      false
      Edit Constraints (Text)
   
   
      
         1
      
      
         
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000184000000010000000100000000000000000000000064ffffffff000000810000000000000001000001840000000100000000
      false
      
   
   000000ff00000000000000020000011b0000011b01000000050100000002
   Implementation
   


Line No.	Rev	Author	Line
1	122	dilbert57
2
3
4
5
6
7
8
9			`2`
10			`/My_System09 - rtl C:\|VHDL\|System09_sandbox_JK\|rtl\|System09_Xess_XuLA\|System09_Xess_XuLA.vhd/XSASDRAM`
11			`/My_System09 - rtl C:\|VHDL\|System09_sandbox_JK\|rtl\|System09_Xess_XuLA\|System09_Xess_XuLA.vhd/XSASDRAM/common`
12			`/My_System09 - rtl C:\|VHDL\|System09_sandbox_JK\|rtl\|System09_Xess_XuLA\|System09_Xess_XuLA.vhd/my_keyboard - keyboard - rtl`
13			`/My_System09 - rtl C:\|VHDL\|System09_sandbox_JK\|rtl\|System09_Xess_XuLA\|System09_Xess_XuLA.vhd/my_vdu - vdu8 - RTL`
14			`/My_System09 - rtl C:\|VHDL\|System09_sandbox_JK\|rtl\|System09_Xess_XuLA\|System09_Xess_XuLA.vhd/u1 - XSASDRAMCntl - arch`
15			`/XSASDRAMCntl - arch C:\|VHDL\|System09_sandbox_JK\|rtl\|System09_Xess_XuLA\|xsasdramcntl.vhd`
16			`/cpu09 - rtl C:\|VHDL\|System09_sandbox_JK\|rtl\|VHDL\|cpu09.vhd`
17			`/ps2_keyboard - rtl C:\|VHDL\|System09_sandbox_JK\|rtl\|VHDL\|ps2_keyboard.vhd`
18
19
20			`System09_Xess_XuLA`
21
22			`0`
23			`0`
24			`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001a8000000020000000000000000000000000000000064ffffffff000000810000000000000002000001a80000000100000000000000000000000100000000`
25			`true`
26			`System09_Xess_XuLA`
27
28
29
30			`1`
31			`Design Utilities/Compile HDL Simulation Libraries`
32
33
34			`Compile HDL Simulation Libraries`
35
36			`0`
37			`0`
38			`000000ff000000000000000100000001000000000000000000000000000000000000000000000001e4000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e40000000100000000`
39			`false`
40			`Compile HDL Simulation Libraries`
41
42
43
44			`1`
45
46
47			`0`
48			`0`
49			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000263000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001970000000100000000`
50			`false`
51			`acia6850.vhd`
52
53
54
55			`1`
56
57
58			`sdramcntl.vhd`
59
60			`0`
61			`0`
62			`000000ff000000000000000100000001000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000`
63			`false`
64			`sdramcntl.vhd`
65
66
67
68			`1`
69			`Configure Target Device`
70			`Design Utilities`
71			`Implement Design/Map`
72			`Implement Design/Map/Generate Post-Map Static Timing`
73			`Implement Design/Place & Route`
74			`Implement Design/Translate`
75			`Synthesize - XST`
76			`User Constraints`
77
78
79
80
81			`0`
82			`0`
83			`000000ff000000000000000100000001000000000000000000000000000000000000000000000001e4000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e40000000100000000`
84			`false`
85
86
87
88
89			`1`
90
91
92			`Edit Constraints (Text)`
93
94			`0`
95			`0`
96			`000000ff000000000000000100000001000000000000000000000000000000000000000000000001e4000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e40000000100000000`
97			`false`
98			`Edit Constraints (Text)`
99
100
101
102			`1`
103
104
105
106
107			`0`
108			`0`
109			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000184000000010000000100000000000000000000000064ffffffff000000810000000000000001000001840000000100000000`
110			`false`
111
112
113			`000000ff00000000000000020000011b0000011b01000000050100000002`
114			`Implementation`
115
116

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Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Xess_XuLA/] [iseconfig/] [System09_Xess_XuLA.projectmgr] - Blame information for rev 122