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[/] [System09/] [trunk/] [rtl/] [VHDL/] [cpu09.vhd] - Blame information for rev 99

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1 99 davidgb
--===========================================================================--
2
--                                                                           --
3
--        Synthesizable 6809 instruction compatible VHDL CPU core            --
4
--                                                                           --
5
--===========================================================================--
6
--
7
-- File name      : cpu09.vhd
8
--
9
-- Entity name    : cpu09
10
--
11
-- Purpose        : 6809 instruction compatible CPU core written in VHDL
12
--                  Not cycle compatible with the original 6809 CPU
13
--
14
-- Dependencies   : ieee.std_logic_1164
15
--                  ieee.std_logic_unsigned
16
--
17
-- Author         : John E. Kent
18
--
19
-- Email          : dilbert57@opencores.org      
20
--
21
-- Web            : http://opencores.org/project,system09
22
--
23
-- 
24
--  Copyright (C) 2003 - 2010 John Kent
25
--
26
--  This program is free software: you can redistribute it and/or modify
27
--  it under the terms of the GNU General Public License as published by
28
--  the Free Software Foundation, either version 3 of the License, or
29
--  (at your option) any later version.
30
--
31
--  This program is distributed in the hope that it will be useful,
32
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
33
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34
--  GNU General Public License for more details.
35
--
36
--  You should have received a copy of the GNU General Public License
37
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
38
--
39
--===========================================================================--
40
--                                                                           --
41
--                                Revision History                           --
42
--                                                                           --
43
--===========================================================================--
44
--
45
-- Version 0.1 - 26 June 2003 - John Kent
46
-- Added extra level in state stack
47
-- fixed some calls to the extended addressing state
48
--
49
-- Version 0.2 - 5 Sept 2003 - John Kent
50
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
51
-- Added/Fixed STY and STS instructions.
52
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
53
-- CMPX Loaded ACCA and ACCB - Now fixed 
54
--
55
-- Version 1.0 - 6 Sep 2003 - John Kent 
56
-- Initial release to Open Cores
57
-- reversed clock edge
58
--
59
-- Version 1.1 - 29 November 2003 John kent
60
--      ACCA and ACCB indexed offsets are 2's complement.
61
-- ALU Right Mux now sign extends ACCA & ACCB offsets
62
-- Absolute Indirect addressing performed a read on the
63
-- second byte of the address rather than a fetch
64
-- so it formed an incorrect address. Now fixed. 
65
--
66
-- Version 1.2 - 29 November 2003 John Kent
67
-- LEAX and LEAY affect the Z bit only
68
--      LEAS and LEAU do not affect any condition codes
69
-- added an extra ALU control for LEA.
70
--
71
-- Version 1.3 - 12 December 2003 John Kent
72
-- CWAI did not work, was missed a PUSH_ST on calling
73
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
74
-- finding this fault.
75
--
76
-- Version 1.4 - 12 December 2003 John Kent
77
-- Missing cc_ctrl assignment in otherwise case of 
78
-- lea_state resulted in cc_ctrl being latched in
79
-- that state.  
80
-- The otherwise statement should never be reached,
81
-- and has been fixed simply to resolve synthesis warnings.
82
--
83
-- Version 1.5 - 17 january 2004 John kent
84
-- The clear instruction used "alu_ld8" to control the ALU
85
-- rather than "alu_clr". This mean the Carry was not being
86
-- cleared correctly.
87
--
88
-- Version 1.6 - 24 January 2004 John Kent
89
-- Fixed problems in PSHU instruction
90
--
91
-- Version 1.7 - 25 January 2004 John Kent
92
-- removed redundant "alu_inx" and "alu_dex'
93
-- Removed "test_alu" and "test_cc"
94
-- STD instruction did not set condition codes
95
-- JMP direct was not decoded properly
96
-- CLR direct performed an unwanted read cycle
97
-- Bogus "latch_md" in Page2 indexed addressing
98
--
99
-- Version 1.8 - 27 January 2004 John Kent
100
-- CWAI in decode1_state should increment the PC.
101
-- ABX is supposed to be an unsigned addition.
102
-- Added extra ALU function
103
-- ASR8 slightly changed in the ALU.
104
--
105
--      Version 1.9 - 20 August 2005
106
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
107
-- rather than LSR16. There was a problem with single 
108
-- operand instructions using the MD register which is
109
-- sign extended on the first 8 bit fetch.
110
--
111
-- Version 1.10 - 13 September 2005
112
-- TFR & EXG instructions did not work for the Condition Code Register
113
-- An extra case has been added to the ALU for the alu_tfr control 
114
-- to assign the left ALU input (alu_left) to the condition code
115
-- outputs (cc_out). 
116
--
117
-- Version 1.11 - 16 September 2005
118
-- JSR ,X should not predecrement S before calculating the jump address.
119
-- The reason is that JSR [0,S] needs S to point to the top of the stack
120
-- to fetch a valid vector address. The solution is to have the addressing
121
-- mode microcode called before decrementing S and then decrementing S in
122
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
123
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
124
-- pushed on the stack. This adds one extra bus cycle, but resolves the
125
-- addressing conflict. I've also removed the pre-decement S in 
126
-- JSR EXTENDED as it also calls JSR_STATE.
127
--
128
-- Version 1.12 - 6th June 2006
129
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
130
-- This is different to the 6800. CLR should reset the V bit.
131
--
132
-- Version 1.13 - 7th July 2006
133
-- Disable NMI on reset until S Stack pointer has been loaded.
134
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
135
--
136
-- Version 1.14 - 11th July 2006
137
-- 1. Added new state to RTI called rti_entire_state.
138
-- This state tests the CC register after it has been loaded
139
-- from the stack. Previously the current CC was tested which
140
-- was incorrect. The Entire Flag should be set before the
141
-- interrupt stacks the CC.
142
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
143
-- which was an enumerated state, but not defined anywhere.
144
-- rti_state has been changed to rti_cc_state so that bogus interrupt
145
-- will perform an RTI after entering that state.
146
-- 3. Sync should generate an interrupt if the interrupt masks
147
-- are cleared. If the interrupt masks are set, then an interrupt
148
-- will cause the the PC to advance to the next instruction.
149
-- Note that I don't wait for an interrupt to be asserted for
150
-- three clock cycles.
151
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
152
-- the Multiply instruction replacing "alu_add16". This is similar 
153
-- to "alu_add16" except it sets the Carry bit to B7 of the result
154
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
155
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
156
-- flags. The logic was re-arranged so that it adds md or zero so 
157
-- that the Carry condition code is set on zero multiplicands.
158
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
159
-- and Zero Flags. It will also affect the Overflow (V) flag although
160
-- the operation is undefined. It's anyones guess what DAA does to V.
161
--
162
-- Version 1.15 - 25th Feb 2007 - John Kent
163
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
164
-- Changed sensitivity lists.
165
--
166
-- Version 1.16 - 5th February 2008 - John Kent
167
-- FIRQ interrupts should take priority over IRQ Interrupts.
168
-- This presumably means they should be tested for before IRQ
169
-- when they happen concurrently.
170
--
171
-- Version 1.17 - 18th February 2008 - John Kent
172
-- NMI in CWAI should mask IRQ and FIRQ interrupts
173
--
174
-- Version 1.18 - 21st February 2008 - John Kent
175
-- Removed default register settings in each case statement
176
-- and placed them at the beginning of the state sequencer.
177
-- Modified the SYNC instruction so that the interrupt vector(iv)
178
-- is not set unless an unmasked FIRQ or IRQ is received.
179
--
180
-- Version 1.19 - 25th February 2008 - John Kent
181
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
182
-- Enumerated separate states for MASKI and MASKIF states
183
-- Removed code on BSR/JSR in fetch cycle
184
--
185
library ieee;
186
use ieee.std_logic_1164.all;
187
use ieee.std_logic_unsigned.all;
188
 
189
entity cpu09 is
190
        port (
191
                clk      :      in std_logic;
192
                rst      :  in std_logic;
193
                vma      : out std_logic;
194
                addr     : out std_logic_vector(15 downto 0);
195
                rw       : out std_logic;
196
           data_out : out std_logic_vector(7 downto 0);
197
           data_in  :  in std_logic_vector(7 downto 0);
198
                irq      :  in std_logic;
199
                firq     :  in std_logic;
200
                nmi      :  in std_logic;
201
                halt     :  in std_logic;
202
                hold     :  in std_logic
203
                );
204
end cpu09;
205
 
206
architecture rtl of cpu09 is
207
 
208
  constant EBIT : integer := 7;
209
  constant FBIT : integer := 6;
210
  constant HBIT : integer := 5;
211
  constant IBIT : integer := 4;
212
  constant NBIT : integer := 3;
213
  constant ZBIT : integer := 2;
214
  constant VBIT : integer := 1;
215
  constant CBIT : integer := 0;
216
 
217
  --
218
  -- Interrupt vector modifiers
219
  --
220
  constant RST_VEC  : std_logic_vector(2 downto 0) := "111";
221
  constant NMI_VEC  : std_logic_vector(2 downto 0) := "110";
222
  constant SWI_VEC  : std_logic_vector(2 downto 0) := "101";
223
  constant IRQ_VEC  : std_logic_vector(2 downto 0) := "100";
224
  constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
225
  constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
226
  constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
227
  constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
228
 
229
        type state_type is (-- Start off in Reset
230
                            reset_state,
231
                                                          -- Fetch Interrupt Vectors (including reset)
232
                                                          vect_lo_state, vect_hi_state,
233
                       -- Fetch Instruction Cycle
234
                       fetch_state,
235
                                                          -- Decode Instruction Cycles
236
                       decode1_state, decode2_state, decode3_state,
237
                                                          -- Calculate Effective Address
238
                                                     imm16_state,
239
                                 indexed_state, index8_state, index16_state, index16_2_state,
240
                                                          pcrel8_state, pcrel16_state, pcrel16_2_state,
241
                                                          indexaddr_state, indexaddr2_state,
242
                                                     postincr1_state, postincr2_state,
243
                                                          indirect_state, indirect2_state, indirect3_state,
244
                       extended_state,
245
                                                          -- single ops
246
                                                          single_op_read_state,
247
                                                     single_op_exec_state,
248
                            single_op_write_state,
249
                                                          -- Dual op states
250
                                                          dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
251
                                                     dual_op_write8_state, dual_op_write16_state,
252
                       -- 
253
                                                     sync_state, halt_state, error_state,
254
                                                          --
255
                                                          andcc_state, orcc_state,
256
                                                          tfr_state, exg_state, exg1_state,
257
                                                          lea_state,
258
                                                          -- Multiplication
259
                                                     mul_state, mulea_state, muld_state,
260
                                                     mul0_state, mul1_state, mul2_state, mul3_state,
261
                                                     mul4_state, mul5_state, mul6_state, mul7_state,
262
                                                          --  Branches
263
                                                          lbranch_state, sbranch_state,
264
                                                          -- Jumps, Subroutine Calls and Returns
265
                       jsr_state, jmp_state,
266
                       push_return_hi_state, push_return_lo_state,
267
                       pull_return_hi_state, pull_return_lo_state,
268
                                                          -- Interrupt cycles
269
                                                          int_nmiirq_state, int_firq_state,
270
                                                          int_entire_state, int_fast_state,
271
                                                          int_pcl_state,  int_pch_state,
272
                                                     int_upl_state,  int_uph_state,
273
                                                     int_iyl_state,  int_iyh_state,
274
                                                     int_ixl_state,  int_ixh_state,
275
                                                     int_dp_state,
276
                                           int_accb_state, int_acca_state,
277
                                                     int_cc_state,
278
                                                     int_cwai_state,
279
                                                          int_maski_state, int_maskif_state,
280
                                                          -- Return From Interrupt
281
                                                     rti_cc_state,   rti_entire_state,
282
                                                          rti_acca_state, rti_accb_state,
283
                                                     rti_dp_state,
284
                                                     rti_ixl_state,  rti_ixh_state,
285
                                                     rti_iyl_state,  rti_iyh_state,
286
                                                     rti_upl_state,  rti_uph_state,
287
                                                     rti_pcl_state,  rti_pch_state,
288
                                                          -- Push Registers using SP
289
                                                          pshs_state,
290
                                                     pshs_pcl_state,  pshs_pch_state,
291
                                                     pshs_upl_state,  pshs_uph_state,
292
                                                     pshs_iyl_state,  pshs_iyh_state,
293
                                                     pshs_ixl_state,  pshs_ixh_state,
294
                                                     pshs_dp_state,
295
                                                     pshs_acca_state, pshs_accb_state,
296
                                                     pshs_cc_state,
297
                                                          -- Pull Registers using SP
298
                                                          puls_state,
299
                                                          puls_cc_state,
300
                                                          puls_acca_state, puls_accb_state,
301
                                                          puls_dp_state,
302
                                                     puls_ixl_state,  puls_ixh_state,
303
                                                     puls_iyl_state,  puls_iyh_state,
304
                                                     puls_upl_state,  puls_uph_state,
305
                                                     puls_pcl_state,  puls_pch_state,
306
                                                          -- Push Registers using UP
307
                                                          pshu_state,
308
                                                     pshu_pcl_state,  pshu_pch_state,
309
                                                     pshu_spl_state,  pshu_sph_state,
310
                                                     pshu_iyl_state,  pshu_iyh_state,
311
                                                     pshu_ixl_state,  pshu_ixh_state,
312
                                                     pshu_dp_state,
313
                                                     pshu_acca_state, pshu_accb_state,
314
                                                     pshu_cc_state,
315
                                                          -- Pull Registers using UP
316
                                                          pulu_state,
317
                                                          pulu_cc_state,
318
                                                          pulu_acca_state, pulu_accb_state,
319
                                                          pulu_dp_state,
320
                                                     pulu_ixl_state,  pulu_ixh_state,
321
                                                     pulu_iyl_state,  pulu_iyh_state,
322
                                                     pulu_spl_state,  pulu_sph_state,
323
                                                     pulu_pcl_state,  pulu_pch_state );
324
 
325
        type stack_type is array(2 downto 0) of state_type;
326
        type st_type    is (idle_st, push_st, pull_st );
327
        type addr_type  is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
328
        type dout_type  is (cc_dout, acca_dout, accb_dout, dp_dout,
329
                       ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
330
                       up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
331
                       pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
332
   type op_type    is (reset_op, fetch_op, latch_op );
333
   type pre_type   is (reset_pre, fetch_pre, latch_pre );
334
   type cc_type    is (reset_cc, load_cc, pull_cc, latch_cc );
335
   type acca_type  is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
336
   type accb_type  is (reset_accb, load_accb, pull_accb, latch_accb );
337
   type dp_type    is (reset_dp, load_dp, pull_dp, latch_dp );
338
        type ix_type    is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
339
        type iy_type    is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
340
        type sp_type    is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
341
        type up_type    is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
342
        type pc_type    is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
343
   type md_type    is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
344
   type ea_type    is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
345
        type iv_type    is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
346
        type nmi_type   is (reset_nmi, set_nmi, latch_nmi );
347
        type left_type  is (cc_left, acca_left, accb_left, dp_left,
348
                                                          ix_left, iy_left, up_left, sp_left,
349
                       accd_left, md_left, pc_left, ea_left );
350
        type right_type is (ea_right, zero_right, one_right, two_right,
351
                       acca_right, accb_right, accd_right,
352
                                                          md_right, md_sign5_right, md_sign8_right );
353
   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
354
                       alu_and, alu_ora, alu_eor,
355
                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
356
                                                     alu_lsr16, alu_lsl16,
357
                                                     alu_ror8, alu_rol8, alu_mul,
358
                                                     alu_asr8, alu_asl8, alu_lsr8,
359
                                                     alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
360
                                                          alu_seif, alu_sei, alu_see, alu_cle,
361
                                                     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
362
 
363
        signal op_code:     std_logic_vector(7 downto 0);
364
        signal pre_code:    std_logic_vector(7 downto 0);
365
        signal acca:        std_logic_vector(7 downto 0);
366
        signal accb:        std_logic_vector(7 downto 0);
367
   signal cc:          std_logic_vector(7 downto 0);
368
        signal cc_out:      std_logic_vector(7 downto 0);
369
        signal dp:          std_logic_vector(7 downto 0);
370
        signal xreg:        std_logic_vector(15 downto 0);
371
        signal yreg:        std_logic_vector(15 downto 0);
372
        signal sp:          std_logic_vector(15 downto 0);
373
        signal up:          std_logic_vector(15 downto 0);
374
        signal ea:          std_logic_vector(15 downto 0);
375
        signal pc:              std_logic_vector(15 downto 0);
376
        signal md:          std_logic_vector(15 downto 0);
377
   signal left:        std_logic_vector(15 downto 0);
378
   signal right:       std_logic_vector(15 downto 0);
379
        signal out_alu:     std_logic_vector(15 downto 0);
380
        signal iv:          std_logic_vector(2 downto 0);
381
        signal nmi_req:     std_logic;
382
        signal nmi_ack:     std_logic;
383
        signal nmi_enable:  std_logic;
384
 
385
        signal state:        state_type;
386
        signal next_state:   state_type;
387
        signal saved_state:  state_type;
388
        signal return_state: state_type;
389
        signal state_stack:  stack_type;
390
        signal st_ctrl:      st_type;
391
   signal pc_ctrl:      pc_type;
392
   signal ea_ctrl:      ea_type;
393
   signal op_ctrl:      op_type;
394
        signal pre_ctrl:     pre_type;
395
        signal md_ctrl:      md_type;
396
        signal acca_ctrl:    acca_type;
397
        signal accb_ctrl:    accb_type;
398
        signal ix_ctrl:      ix_type;
399
        signal iy_ctrl:      iy_type;
400
        signal cc_ctrl:      cc_type;
401
        signal dp_ctrl:      dp_type;
402
        signal sp_ctrl:      sp_type;
403
        signal up_ctrl:      up_type;
404
        signal iv_ctrl:      iv_type;
405
        signal left_ctrl:    left_type;
406
        signal right_ctrl:   right_type;
407
   signal alu_ctrl:     alu_type;
408
   signal addr_ctrl:    addr_type;
409
   signal dout_ctrl:    dout_type;
410
   signal nmi_ctrl:     nmi_type;
411
 
412
 
413
begin
414
 
415
----------------------------------
416
--
417
-- State machine stack
418
--
419
----------------------------------
420
--state_stack_proc: process( clk, hold, state_stack, st_ctrl, 
421
--                           return_state, fetch_state  )
422
state_stack_proc: process( clk, state_stack )
423
begin
424
  if clk'event and clk = '0' then
425
    if hold= '1' then
426
           state_stack(0) <= state_stack(0);
427
           state_stack(1) <= state_stack(1);
428
           state_stack(2) <= state_stack(2);
429
         else
430
           case st_ctrl is
431
                when idle_st =>
432
                  state_stack(0) <= state_stack(0);
433
             state_stack(1) <= state_stack(1);
434
             state_stack(2) <= state_stack(2);
435
      when push_st =>
436
                  state_stack(0) <= return_state;
437
             state_stack(1) <= state_stack(0);
438
             state_stack(2) <= state_stack(1);
439
      when pull_st =>
440
                  state_stack(0) <= state_stack(1);
441
             state_stack(1) <= state_stack(2);
442
             state_stack(2) <= fetch_state;
443
                when others =>
444
                  state_stack(0) <= state_stack(0);
445
             state_stack(1) <= state_stack(1);
446
             state_stack(2) <= state_stack(2);
447
           end case;
448
    end if;
449
  end if;
450
  saved_state <= state_stack(0);
451
end process;
452
 
453
----------------------------------
454
--
455
-- Program Counter Control
456
--
457
----------------------------------
458
 
459
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
460
pc_reg: process( clk )
461
begin
462
  if clk'event and clk = '0' then
463
    if hold= '1' then
464
           pc <= pc;
465
         else
466
    case pc_ctrl is
467
         when reset_pc =>
468
           pc <= "0000000000000000";
469
         when load_pc =>
470
           pc <= out_alu(15 downto 0);
471
         when pull_lo_pc =>
472
           pc(7 downto 0) <= data_in;
473
         when pull_hi_pc =>
474
           pc(15 downto 8) <= data_in;
475
         when incr_pc =>
476
           pc <= pc + 1;
477
         when others =>
478
--       when latch_pc =>
479
      pc <= pc;
480
    end case;
481
         end if;
482
  end if;
483
end process;
484
 
485
----------------------------------
486
--
487
-- Effective Address  Control
488
--
489
----------------------------------
490
 
491
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
492
ea_reg: process( clk )
493
begin
494
 
495
  if clk'event and clk = '0' then
496
    if hold= '1' then
497
           ea <= ea;
498
         else
499
    case ea_ctrl is
500
         when reset_ea =>
501
           ea <= "0000000000000000";
502
         when fetch_first_ea =>
503
           ea(7 downto 0) <= data_in;
504
      ea(15 downto 8) <= dp;
505
         when fetch_next_ea =>
506
           ea(15 downto 8) <= ea(7 downto 0);
507
      ea(7 downto 0)  <= data_in;
508
         when load_ea =>
509
           ea <= out_alu(15 downto 0);
510
         when others =>
511
--       when latch_ea =>
512
      ea <= ea;
513
    end case;
514
         end if;
515
  end if;
516
end process;
517
 
518
--------------------------------
519
--
520
-- Accumulator A
521
--
522
--------------------------------
523
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
524
acca_reg : process( clk )
525
begin
526
  if clk'event and clk = '0' then
527
    if hold= '1' then
528
           acca <= acca;
529
         else
530
    case acca_ctrl is
531
    when reset_acca =>
532
           acca <= "00000000";
533
         when load_acca =>
534
           acca <= out_alu(7 downto 0);
535
         when load_hi_acca =>
536
           acca <= out_alu(15 downto 8);
537
         when pull_acca =>
538
           acca <= data_in;
539
         when others =>
540
--       when latch_acca =>
541
           acca <= acca;
542
    end case;
543
         end if;
544
  end if;
545
end process;
546
 
547
--------------------------------
548
--
549
-- Accumulator B
550
--
551
--------------------------------
552
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
553
accb_reg : process( clk )
554
begin
555
  if clk'event and clk = '0' then
556
    if hold= '1' then
557
           accb <= accb;
558
         else
559
    case accb_ctrl is
560
    when reset_accb =>
561
           accb <= "00000000";
562
         when load_accb =>
563
           accb <= out_alu(7 downto 0);
564
         when pull_accb =>
565
           accb <= data_in;
566
         when others =>
567
--       when latch_accb =>
568
           accb <= accb;
569
    end case;
570
         end if;
571
  end if;
572
end process;
573
 
574
--------------------------------
575
--
576
-- X Index register
577
--
578
--------------------------------
579
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
580
ix_reg : process( clk )
581
begin
582
  if clk'event and clk = '0' then
583
    if hold= '1' then
584
           xreg <= xreg;
585
         else
586
    case ix_ctrl is
587
    when reset_ix =>
588
           xreg <= "0000000000000000";
589
         when load_ix =>
590
           xreg <= out_alu(15 downto 0);
591
         when pull_hi_ix =>
592
           xreg(15 downto 8) <= data_in;
593
         when pull_lo_ix =>
594
           xreg(7 downto 0) <= data_in;
595
         when others =>
596
--       when latch_ix =>
597
           xreg <= xreg;
598
    end case;
599
         end if;
600
  end if;
601
end process;
602
 
603
--------------------------------
604
--
605
-- Y Index register
606
--
607
--------------------------------
608
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
609
iy_reg : process( clk )
610
begin
611
  if clk'event and clk = '0' then
612
    if hold= '1' then
613
           yreg <= yreg;
614
         else
615
    case iy_ctrl is
616
    when reset_iy =>
617
           yreg <= "0000000000000000";
618
         when load_iy =>
619
           yreg <= out_alu(15 downto 0);
620
         when pull_hi_iy =>
621
           yreg(15 downto 8) <= data_in;
622
         when pull_lo_iy =>
623
           yreg(7 downto 0) <= data_in;
624
         when others =>
625
--       when latch_iy =>
626
           yreg <= yreg;
627
    end case;
628
         end if;
629
  end if;
630
end process;
631
 
632
--------------------------------
633
--
634
-- S stack pointer
635
--
636
--------------------------------
637
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
638
sp_reg : process( clk )
639
begin
640
  if clk'event and clk = '0' then
641
    if hold= '1' then
642
           sp <= sp;
643
                nmi_enable <= nmi_enable;
644
         else
645
    case sp_ctrl is
646
    when reset_sp =>
647
           sp <= "0000000000000000";
648
                nmi_enable <= '0';
649
         when load_sp =>
650
           sp <= out_alu(15 downto 0);
651
                nmi_enable <= '1';
652
         when pull_hi_sp =>
653
           sp(15 downto 8) <= data_in;
654
                nmi_enable <= nmi_enable;
655
         when pull_lo_sp =>
656
           sp(7 downto 0) <= data_in;
657
                nmi_enable <= '1';
658
         when others =>
659
--       when latch_sp =>
660
           sp <= sp;
661
                nmi_enable <= nmi_enable;
662
    end case;
663
         end if;
664
  end if;
665
end process;
666
 
667
--------------------------------
668
--
669
-- U stack pointer
670
--
671
--------------------------------
672
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
673
up_reg : process( clk )
674
begin
675
  if clk'event and clk = '0' then
676
    if hold= '1' then
677
           up <= up;
678
         else
679
    case up_ctrl is
680
    when reset_up =>
681
           up <= "0000000000000000";
682
         when load_up =>
683
           up <= out_alu(15 downto 0);
684
         when pull_hi_up =>
685
           up(15 downto 8) <= data_in;
686
         when pull_lo_up =>
687
           up(7 downto 0) <= data_in;
688
         when others =>
689
--       when latch_up =>
690
           up <= up;
691
    end case;
692
         end if;
693
  end if;
694
end process;
695
 
696
--------------------------------
697
--
698
-- Memory Data
699
--
700
--------------------------------
701
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
702
md_reg : process( clk )
703
begin
704
  if clk'event and clk = '0' then
705
    if hold= '1' then
706
           md <= md;
707
         else
708
    case md_ctrl is
709
    when reset_md =>
710
           md <= "0000000000000000";
711
         when load_md =>
712
           md <= out_alu(15 downto 0);
713
         when fetch_first_md => -- sign extend md for branches
714
           md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
715
                              data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
716
           md(7 downto 0) <= data_in;
717
         when fetch_next_md =>
718
           md(15 downto 8) <= md(7 downto 0);
719
                md(7 downto 0) <= data_in;
720
         when shiftl_md =>
721
           md(15 downto 1) <= md(14 downto 0);
722
                md(0) <= '0';
723
         when others =>
724
--       when latch_md =>
725
           md <= md;
726
    end case;
727
         end if;
728
  end if;
729
end process;
730
 
731
 
732
----------------------------------
733
--
734
-- Condition Codes
735
--
736
----------------------------------
737
 
738
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
739
cc_reg: process( clk )
740
begin
741
  if clk'event and clk = '0' then
742
    if hold= '1' then
743
           cc <= cc;
744
         else
745
    case cc_ctrl is
746
         when reset_cc =>
747
           cc <= "11010000"; -- set EBIT, FBIT & IBIT
748
         when load_cc =>
749
           cc <= cc_out;
750
         when pull_cc =>
751
      cc <= data_in;
752
         when others =>
753
--  when latch_cc =>
754
      cc <= cc;
755
    end case;
756
         end if;
757
  end if;
758
end process;
759
 
760
----------------------------------
761
--
762
-- Direct Page register
763
--
764
----------------------------------
765
 
766
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
767
dp_reg: process( clk )
768
begin
769
  if clk'event and clk = '0' then
770
    if hold= '1' then
771
           dp <= dp;
772
         else
773
    case dp_ctrl is
774
         when reset_dp =>
775
           dp <= "00000000";
776
         when load_dp =>
777
           dp <= out_alu(7 downto 0);
778
         when pull_dp =>
779
      dp <= data_in;
780
         when others =>
781
--  when latch_dp =>
782
      dp <= dp;
783
    end case;
784
         end if;
785
  end if;
786
end process;
787
 
788
----------------------------------
789
--
790
-- interrupt vector
791
--
792
----------------------------------
793
 
794
--iv_mux: process( clk, iv_ctrl, hold, iv )
795
iv_mux: process( clk )
796
begin
797
  if clk'event and clk = '0' then
798
    if hold= '1' then
799
           iv <= iv;
800
         else
801
    case iv_ctrl is
802
         when reset_iv =>
803
           iv <= RST_VEC;
804
         when nmi_iv =>
805
      iv <= NMI_VEC;
806
         when swi_iv =>
807
      iv <= SWI_VEC;
808
         when irq_iv =>
809
      iv <= IRQ_VEC;
810
         when firq_iv =>
811
           iv <= FIRQ_VEC;
812
         when swi2_iv =>
813
      iv <= SWI2_VEC;
814
         when swi3_iv =>
815
      iv <= SWI3_VEC;
816
         when resv_iv =>
817
      iv <= RESV_VEC;
818
         when others =>
819
           iv <= iv;
820
    end case;
821
         end if;
822
  end if;
823
end process;
824
 
825
 
826
----------------------------------
827
--
828
-- op code register
829
--
830
----------------------------------
831
 
832
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
833
op_reg: process( clk )
834
begin
835
  if clk'event and clk = '0' then
836
    if hold= '1' then
837
           op_code <= op_code;
838
         else
839
    case op_ctrl is
840
         when reset_op =>
841
           op_code <= "00010010";
842
         when fetch_op =>
843
      op_code <= data_in;
844
         when others =>
845
--       when latch_op =>
846
           op_code <= op_code;
847
    end case;
848
         end if;
849
  end if;
850
end process;
851
 
852
 
853
----------------------------------
854
--
855
-- pre byte op code register
856
--
857
----------------------------------
858
 
859
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
860
pre_reg: process( clk )
861
begin
862
  if clk'event and clk = '0' then
863
    if hold= '1' then
864
           pre_code <= pre_code;
865
         else
866
    case pre_ctrl is
867
         when reset_pre =>
868
           pre_code <= "00000000";
869
         when fetch_pre =>
870
      pre_code <= data_in;
871
         when others =>
872
--       when latch_pre =>
873
           pre_code <= pre_code;
874
    end case;
875
         end if;
876
  end if;
877
end process;
878
 
879
--------------------------------
880
--
881
-- state machine
882
--
883
--------------------------------
884
 
885
--change_state: process( clk, rst, state, hold, next_state )
886
change_state: process( clk )
887
begin
888
  if clk'event and clk = '0' then
889
    if rst = '1' then
890
           state <= reset_state;
891
    else
892
           if hold = '1' then
893
                  state <= state;
894
                else
895
        state <= next_state;
896
                end if;
897
         end if;
898
  end if;
899
end process;
900
        -- output
901
 
902
------------------------------------
903
--
904
-- Nmi register
905
--
906
------------------------------------
907
 
908
--nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack )
909
nmi_reg: process( clk )
910
begin
911
  if clk'event and clk='0' then
912
    if hold = '1' then
913
      nmi_ack <= nmi_ack;
914
    else
915
    case nmi_ctrl is
916
         when set_nmi =>
917
      nmi_ack <= '1';
918
         when reset_nmi =>
919
           nmi_ack <= '0';
920
         when others =>
921
--  when latch_nmi =>
922
           nmi_ack <= nmi_ack;
923
         end case;
924
         end if;
925
  end if;
926
end process;
927
 
928
------------------------------------
929
--
930
-- Detect Edge of NMI interrupt
931
--
932
------------------------------------
933
 
934
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
935
nmi_handler : process( rst, clk )
936
begin
937
  if rst='1' then
938
         nmi_req <= '0';
939
  elsif clk'event and clk='0' then
940
           if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
941
             nmi_req <= '1';
942
           else
943
                  if (nmi='0') and (nmi_ack='1') then
944
               nmi_req <= '0';
945
                  end if;
946
                end if;
947
  end if;
948
end process;
949
 
950
 
951
----------------------------------
952
--
953
-- Address output multiplexer
954
--
955
----------------------------------
956
 
957
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
958
begin
959
  case addr_ctrl is
960
    when idle_ad =>
961
                vma  <= '0';
962
           addr <= "1111111111111111";
963
                rw   <= '1';
964
    when fetch_ad =>
965
                vma  <= '1';
966
           addr <= pc;
967
                rw   <= '1';
968
         when read_ad =>
969
                vma  <= '1';
970
           addr <= ea;
971
                rw   <= '1';
972
    when write_ad =>
973
                vma  <= '1';
974
           addr <= ea;
975
                rw   <= '0';
976
         when pushs_ad =>
977
                vma  <= '1';
978
           addr <= sp;
979
                rw   <= '0';
980
    when pulls_ad =>
981
                vma  <= '1';
982
           addr <= sp;
983
                rw   <= '1';
984
         when pushu_ad =>
985
                vma  <= '1';
986
           addr <= up;
987
                rw   <= '0';
988
    when pullu_ad =>
989
                vma  <= '1';
990
           addr <= up;
991
                rw   <= '1';
992
         when int_hi_ad =>
993
                vma  <= '1';
994
           addr <= "111111111111" & iv & "0";
995
                rw   <= '1';
996
    when int_lo_ad =>
997
                vma  <= '1';
998
           addr <= "111111111111" & iv & "1";
999
                rw   <= '1';
1000
         when others =>
1001
                vma  <= '0';
1002
           addr <= "1111111111111111";
1003
                rw   <= '1';
1004
  end case;
1005
end process;
1006
 
1007
--------------------------------
1008
--
1009
-- Data Bus output
1010
--
1011
--------------------------------
1012
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
1013
begin
1014
    case dout_ctrl is
1015
         when cc_dout => -- condition code register
1016
           data_out <= cc;
1017
         when acca_dout => -- accumulator a
1018
           data_out <= acca;
1019
         when accb_dout => -- accumulator b
1020
           data_out <= accb;
1021
         when dp_dout => -- direct page register
1022
           data_out <= dp;
1023
         when ix_lo_dout => -- X index reg
1024
           data_out <= xreg(7 downto 0);
1025
         when ix_hi_dout => -- X index reg
1026
           data_out <= xreg(15 downto 8);
1027
         when iy_lo_dout => -- Y index reg
1028
           data_out <= yreg(7 downto 0);
1029
         when iy_hi_dout => -- Y index reg
1030
           data_out <= yreg(15 downto 8);
1031
         when up_lo_dout => -- U stack pointer
1032
           data_out <= up(7 downto 0);
1033
         when up_hi_dout => -- U stack pointer
1034
           data_out <= up(15 downto 8);
1035
         when sp_lo_dout => -- S stack pointer
1036
           data_out <= sp(7 downto 0);
1037
         when sp_hi_dout => -- S stack pointer
1038
           data_out <= sp(15 downto 8);
1039
         when md_lo_dout => -- alu output
1040
           data_out <= md(7 downto 0);
1041
         when md_hi_dout => -- alu output
1042
           data_out <= md(15 downto 8);
1043
         when pc_lo_dout => -- low order pc
1044
           data_out <= pc(7 downto 0);
1045
         when pc_hi_dout => -- high order pc
1046
           data_out <= pc(15 downto 8);
1047
         when others =>
1048
           data_out <= "00000000";
1049
    end case;
1050
end process;
1051
 
1052
----------------------------------
1053
--
1054
-- Left Mux
1055
--
1056
----------------------------------
1057
 
1058
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
1059
begin
1060
  case left_ctrl is
1061
         when cc_left =>
1062
           left(15 downto 8) <= "00000000";
1063
                left(7 downto 0)  <= cc;
1064
         when acca_left =>
1065
           left(15 downto 8) <= "00000000";
1066
                left(7 downto 0)  <= acca;
1067
         when accb_left =>
1068
           left(15 downto 8) <= "00000000";
1069
                left(7 downto 0)  <= accb;
1070
         when dp_left =>
1071
           left(15 downto 8) <= "00000000";
1072
                left(7 downto 0)  <= dp;
1073
         when accd_left =>
1074
           left(15 downto 8) <= acca;
1075
                left(7 downto 0)  <= accb;
1076
         when md_left =>
1077
           left <= md;
1078
         when ix_left =>
1079
           left <= xreg;
1080
         when iy_left =>
1081
           left <= yreg;
1082
         when sp_left =>
1083
           left <= sp;
1084
         when up_left =>
1085
           left <= up;
1086
         when pc_left =>
1087
           left <= pc;
1088
         when others =>
1089
--       when ea_left =>
1090
           left <= ea;
1091
    end case;
1092
end process;
1093
 
1094
----------------------------------
1095
--
1096
-- Right Mux
1097
--
1098
----------------------------------
1099
 
1100
right_mux: process( right_ctrl, md, acca, accb, ea )
1101
begin
1102
  case right_ctrl is
1103
         when ea_right =>
1104
           right <= ea;
1105
         when zero_right =>
1106
           right <= "0000000000000000";
1107
         when one_right =>
1108
           right <= "0000000000000001";
1109
         when two_right =>
1110
           right <= "0000000000000010";
1111
         when acca_right =>
1112
           if acca(7) = '0' then
1113
             right <= "00000000" & acca(7 downto 0);
1114
                else
1115
                  right <= "11111111" & acca(7 downto 0);
1116
                end if;
1117
         when accb_right =>
1118
           if accb(7) = '0' then
1119
             right <= "00000000" & accb(7 downto 0);
1120
                else
1121
                  right <= "11111111" & accb(7 downto 0);
1122
                end if;
1123
         when accd_right =>
1124
           right <= acca & accb;
1125
         when md_sign5_right =>
1126
           if md(4) = '0' then
1127
             right <= "00000000000" & md(4 downto 0);
1128
                else
1129
                  right <= "11111111111" & md(4 downto 0);
1130
                end if;
1131
         when md_sign8_right =>
1132
           if md(7) = '0' then
1133
             right <= "00000000" & md(7 downto 0);
1134
                else
1135
                  right <= "11111111" & md(7 downto 0);
1136
                end if;
1137
         when others =>
1138
--       when md_right =>
1139
           right <= md;
1140
    end case;
1141
end process;
1142
 
1143
----------------------------------
1144
--
1145
-- Arithmetic Logic Unit
1146
--
1147
----------------------------------
1148
 
1149
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
1150
variable valid_lo, valid_hi : boolean;
1151
variable carry_in : std_logic;
1152
variable daa_reg : std_logic_vector(7 downto 0);
1153
begin
1154
 
1155
  case alu_ctrl is
1156
         when alu_adc | alu_sbc |
1157
              alu_rol8 | alu_ror8 =>
1158
           carry_in := cc(CBIT);
1159
    when alu_asr8 =>
1160
           carry_in := left(7);
1161
         when others =>
1162
           carry_in := '0';
1163
  end case;
1164
 
1165
  valid_lo := left(3 downto 0) <= 9;
1166
  valid_hi := left(7 downto 4) <= 9;
1167
 
1168
  if (cc(CBIT) = '0') then
1169
    if( cc(HBIT) = '1' ) then
1170
                if valid_hi then
1171
                  daa_reg := "00000110";
1172
                else
1173
                  daa_reg := "01100110";
1174
           end if;
1175
    else
1176
                if valid_lo then
1177
                  if valid_hi then
1178
                    daa_reg := "00000000";
1179
                  else
1180
                    daa_reg := "01100000";
1181
                  end if;
1182
                else
1183
             if( left(7 downto 4) <= 8 ) then
1184
                    daa_reg := "00000110";
1185
                  else
1186
                         daa_reg := "01100110";
1187
                  end if;
1188
                end if;
1189
         end if;
1190
  else
1191
    if ( cc(HBIT) = '1' )then
1192
                daa_reg := "01100110";
1193
         else
1194
                if valid_lo then
1195
                  daa_reg := "01100000";
1196
           else
1197
                  daa_reg := "01100110";
1198
                end if;
1199
         end if;
1200
  end if;
1201
 
1202
  case alu_ctrl is
1203
         when alu_add8 | alu_inc |
1204
              alu_add16 | alu_adc | alu_mul =>
1205
                out_alu <= left + right + ("000000000000000" & carry_in);
1206
         when alu_sub8 | alu_dec |
1207
              alu_sub16 | alu_sbc =>
1208
           out_alu <= left - right - ("000000000000000" & carry_in);
1209
    when alu_abx =>
1210
           out_alu <= left + ("00000000" & right(7 downto 0)) ;
1211
         when alu_and =>
1212
           out_alu   <= left and right;         -- and/bit
1213
         when alu_ora =>
1214
           out_alu   <= left or right;  -- or
1215
         when alu_eor =>
1216
           out_alu   <= left xor right;         -- eor/xor
1217
         when alu_lsl16 | alu_asl8 | alu_rol8 =>
1218
           out_alu   <= left(14 downto 0) & carry_in;    -- rol8/asl8/lsl16
1219
         when alu_lsr16 =>
1220
           out_alu   <= carry_in & left(15 downto 1);   -- lsr16
1221
         when alu_lsr8 | alu_asr8 | alu_ror8 =>
1222
           out_alu   <= "00000000" & carry_in & left(7 downto 1);       -- ror8/asr8/lsr8
1223
         when alu_neg =>
1224
           out_alu   <= right - left;   -- neg (right=0)
1225
         when alu_com =>
1226
           out_alu   <= not left;
1227
         when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
1228
           out_alu   <= right;           -- clr, ld
1229
         when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
1230
           out_alu   <= left;
1231
         when alu_daa =>
1232
           out_alu   <= left + ("00000000" & daa_reg);
1233
         when alu_sex =>
1234
           if left(7) = '0' then
1235
              out_alu <= "00000000" & left(7 downto 0);
1236
                else
1237
                   out_alu <= "11111111" & left(7 downto 0);
1238
                end if;
1239
         when others =>
1240
           out_alu   <= left; -- nop
1241
    end case;
1242
 
1243
         --
1244
         -- carry bit
1245
         --
1246
    case alu_ctrl is
1247
         when alu_add8 | alu_adc  =>
1248
      cc_out(CBIT) <= (left(7) and right(7)) or
1249
                                (left(7) and not out_alu(7)) or
1250
                                                   (right(7) and not out_alu(7));
1251
         when alu_sub8 | alu_sbc =>
1252
      cc_out(CBIT) <= ((not left(7)) and right(7)) or
1253
                                ((not left(7)) and out_alu(7)) or
1254
                                                         (right(7) and out_alu(7));
1255
         when alu_add16  =>
1256
      cc_out(CBIT) <= (left(15) and right(15)) or
1257
                                (left(15) and not out_alu(15)) or
1258
                                                   (right(15) and not out_alu(15));
1259
         when alu_sub16 =>
1260
      cc_out(CBIT) <= ((not left(15)) and right(15)) or
1261
                                ((not left(15)) and out_alu(15)) or
1262
                                                         (right(15) and out_alu(15));
1263
         when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
1264
           cc_out(CBIT) <= left(0);
1265
         when alu_rol8 | alu_asl8 =>
1266
           cc_out(CBIT) <= left(7);
1267
         when alu_lsl16 =>
1268
           cc_out(CBIT) <= left(15);
1269
         when alu_com =>
1270
           cc_out(CBIT) <= '1';
1271
         when alu_neg | alu_clr =>
1272
           cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1273
                                out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
1274
    when alu_mul =>
1275
                cc_out(CBIT) <= out_alu(7);
1276
    when alu_daa =>
1277
           if ( daa_reg(7 downto 4) = "0110" ) then
1278
                  cc_out(CBIT) <= '1';
1279
                else
1280
                  cc_out(CBIT) <= '0';
1281
           end if;
1282
         when alu_andcc =>
1283
      cc_out(CBIT) <= left(CBIT) and cc(CBIT);
1284
         when alu_orcc =>
1285
      cc_out(CBIT) <= left(CBIT) or cc(CBIT);
1286
         when alu_tfr =>
1287
      cc_out(CBIT) <= left(CBIT);
1288
         when others =>
1289
      cc_out(CBIT) <= cc(CBIT);
1290
    end case;
1291
         --
1292
         -- Zero flag
1293
         --
1294
    case alu_ctrl is
1295
         when alu_add8 | alu_sub8 |
1296
              alu_adc | alu_sbc |
1297
              alu_and | alu_ora | alu_eor |
1298
              alu_inc | alu_dec |
1299
                        alu_neg | alu_com | alu_clr |
1300
                        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1301
                   alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1302
      cc_out(ZBIT) <= not( out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1303
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1304
         when alu_add16 | alu_sub16 | alu_mul |
1305
              alu_lsl16 | alu_lsr16 |
1306
                   alu_ld16  | alu_st16 | alu_lea =>
1307
      cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
1308
                                out_alu(11) or out_alu(10) or out_alu(9)  or out_alu(8)  or
1309
                                out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1310
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1311
         when alu_andcc =>
1312
      cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
1313
         when alu_orcc =>
1314
      cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
1315
         when alu_tfr =>
1316
      cc_out(ZBIT) <= left(ZBIT);
1317
         when others =>
1318
      cc_out(ZBIT) <= cc(ZBIT);
1319
    end case;
1320
 
1321
    --
1322
         -- negative flag
1323
         --
1324
    case alu_ctrl is
1325
         when alu_add8 | alu_sub8 |
1326
              alu_adc | alu_sbc |
1327
              alu_and | alu_ora | alu_eor |
1328
              alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1329
              alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
1330
                        alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1331
      cc_out(NBIT) <= out_alu(7);
1332
         when alu_add16 | alu_sub16 |
1333
              alu_lsl16 | alu_lsr16 |
1334
                        alu_ld16 | alu_st16 =>
1335
                cc_out(NBIT) <= out_alu(15);
1336
         when alu_andcc =>
1337
      cc_out(NBIT) <= left(NBIT) and cc(NBIT);
1338
         when alu_orcc =>
1339
      cc_out(NBIT) <= left(NBIT) or cc(NBIT);
1340
         when alu_tfr =>
1341
      cc_out(NBIT) <= left(NBIT);
1342
         when others =>
1343
      cc_out(NBIT) <= cc(NBIT);
1344
    end case;
1345
 
1346
    --
1347
         -- Interrupt mask flag
1348
    --
1349
    case alu_ctrl is
1350
         when alu_andcc =>
1351
      cc_out(IBIT) <= left(IBIT) and cc(IBIT);
1352
         when alu_orcc =>
1353
      cc_out(IBIT) <= left(IBIT) or cc(IBIT);
1354
         when alu_tfr =>
1355
      cc_out(IBIT) <= left(IBIT);
1356
    when alu_seif | alu_sei =>
1357
           cc_out(IBIT) <= '1';
1358
         when others =>
1359
                cc_out(IBIT) <= cc(IBIT);             -- interrupt mask
1360
    end case;
1361
 
1362
    --
1363
    -- Half Carry flag
1364
         --
1365
    case alu_ctrl is
1366
         when alu_add8 | alu_adc =>
1367
      cc_out(HBIT) <= (left(3) and right(3)) or
1368
                     (right(3) and not out_alu(3)) or
1369
                      (left(3) and not out_alu(3));
1370
         when alu_andcc =>
1371
      cc_out(HBIT) <= left(HBIT) and cc(HBIT);
1372
         when alu_orcc =>
1373
      cc_out(HBIT) <= left(HBIT) or cc(HBIT);
1374
         when alu_tfr =>
1375
      cc_out(HBIT) <= left(HBIT);
1376
         when others =>
1377
                cc_out(HBIT) <= cc(HBIT);
1378
    end case;
1379
 
1380
    --
1381
    -- Overflow flag
1382
         --
1383
    case alu_ctrl is
1384
         when alu_add8 | alu_adc =>
1385
      cc_out(VBIT) <= (left(7)  and      right(7)  and (not out_alu(7))) or
1386
                 ((not left(7)) and (not right(7)) and      out_alu(7));
1387
         when alu_sub8 | alu_sbc =>
1388
      cc_out(VBIT) <= (left(7)  and (not right(7)) and (not out_alu(7))) or
1389
                 ((not left(7)) and      right(7)  and      out_alu(7));
1390
         when alu_add16 =>
1391
      cc_out(VBIT) <= (left(15)  and      right(15)  and (not out_alu(15))) or
1392
                 ((not left(15)) and (not right(15)) and      out_alu(15));
1393
         when alu_sub16 =>
1394
      cc_out(VBIT) <= (left(15)  and (not right(15)) and (not out_alu(15))) or
1395
                 ((not left(15)) and      right(15) and       out_alu(15));
1396
         when alu_inc =>
1397
           cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
1398
                                      left(3)  and left(2) and left(1) and left(0));
1399
         when alu_dec | alu_neg =>
1400
           cc_out(VBIT) <= (left(7)  and (not left(6)) and (not left(5)) and (not left(4)) and
1401
                            (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
1402
-- 6809 Programming reference manual says
1403
-- V not affected by ASR, LSR and ROR
1404
-- This is different to the 6800
1405
-- John Kent 6th June 2006
1406
--       when alu_asr8 =>
1407
--         cc_out(VBIT) <= left(0) xor left(7);
1408
--       when alu_lsr8 | alu_lsr16 =>
1409
--         cc_out(VBIT) <= left(0);
1410
--       when alu_ror8 =>
1411
--      cc_out(VBIT) <= left(0) xor cc(CBIT);
1412
    when alu_lsl16 =>
1413
      cc_out(VBIT) <= left(15) xor left(14);
1414
         when alu_rol8 | alu_asl8 =>
1415
      cc_out(VBIT) <= left(7) xor left(6);
1416
--
1417
-- 11th July 2006 - John Kent
1418
-- What DAA does with V is anyones guess
1419
-- It is undefined in the 6809 programming manual
1420
--
1421
         when alu_daa =>
1422
      cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
1423
-- CLR resets V Bit
1424
-- John Kent 6th June 2006
1425
         when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
1426
              alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
1427
      cc_out(VBIT) <= '0';
1428
         when alu_andcc =>
1429
      cc_out(VBIT) <= left(VBIT) and cc(VBIT);
1430
         when alu_orcc =>
1431
      cc_out(VBIT) <= left(VBIT) or cc(VBIT);
1432
         when alu_tfr =>
1433
      cc_out(VBIT) <= left(VBIT);
1434
         when others =>
1435
                cc_out(VBIT) <= cc(VBIT);
1436
    end case;
1437
 
1438
         case alu_ctrl is
1439
         when alu_andcc =>
1440
      cc_out(FBIT) <= left(FBIT) and cc(FBIT);
1441
         when alu_orcc =>
1442
      cc_out(FBIT) <= left(FBIT) or cc(FBIT);
1443
         when alu_tfr =>
1444
      cc_out(FBIT) <= left(FBIT);
1445
    when alu_seif =>
1446
           cc_out(FBIT) <= '1';
1447
         when others =>
1448
      cc_out(FBIT) <= cc(FBIT);
1449
         end case;
1450
 
1451
         case alu_ctrl is
1452
         when alu_andcc =>
1453
      cc_out(EBIT) <= left(EBIT) and cc(EBIT);
1454
         when alu_orcc =>
1455
      cc_out(EBIT) <= left(EBIT) or cc(EBIT);
1456
         when alu_tfr =>
1457
      cc_out(EBIT) <= left(EBIT);
1458
    when alu_see =>
1459
           cc_out(EBIT) <= '1';
1460
    when alu_cle =>
1461
           cc_out(EBIT) <= '0';
1462
         when others =>
1463
           cc_out(EBIT) <= cc(EBIT);
1464
         end case;
1465
end process;
1466
 
1467
------------------------------------
1468
--
1469
-- state sequencer
1470
--
1471
------------------------------------
1472
process( state, saved_state,
1473
         op_code, pre_code,
1474
                        cc, ea, md, iv,
1475
                        irq, firq, nmi_req, nmi_ack, halt )
1476
variable cond_true : boolean;  -- variable used to evaluate coditional branches
1477
begin
1478
        -- Registers preserved
1479
        cc_ctrl    <= latch_cc;
1480
        acca_ctrl  <= latch_acca;
1481
        accb_ctrl  <= latch_accb;
1482
        dp_ctrl    <= latch_dp;
1483
        ix_ctrl    <= latch_ix;
1484
        iy_ctrl    <= latch_iy;
1485
        up_ctrl    <= latch_up;
1486
        sp_ctrl    <= latch_sp;
1487
        pc_ctrl    <= latch_pc;
1488
        md_ctrl    <= latch_md;
1489
        ea_ctrl    <= latch_ea;
1490
        iv_ctrl    <= latch_iv;
1491
        op_ctrl    <= latch_op;
1492
        pre_ctrl   <= latch_pre;
1493
        nmi_ctrl   <= latch_nmi;
1494
                  -- ALU Idle
1495
        left_ctrl  <= pc_left;
1496
        right_ctrl <= zero_right;
1497
        alu_ctrl   <= alu_nop;
1498
                  -- Bus idle
1499
        addr_ctrl  <= idle_ad;
1500
        dout_ctrl  <= cc_dout;
1501
                  -- Next State Fetch
1502
        st_ctrl      <= idle_st;
1503
        return_state <= fetch_state;
1504
        next_state   <= fetch_state;
1505
 
1506
                    case state is
1507
          when reset_state =>        --  released from reset
1508
                            -- reset the registers
1509
             op_ctrl    <= reset_op;
1510
             pre_ctrl   <= reset_pre;
1511
             cc_ctrl    <= reset_cc;
1512
                                 acca_ctrl  <= reset_acca;
1513
                                 accb_ctrl  <= reset_accb;
1514
             dp_ctrl    <= reset_dp;
1515
                                 ix_ctrl    <= reset_ix;
1516
                                 iy_ctrl    <= reset_iy;
1517
                       up_ctrl    <= reset_up;
1518
                       sp_ctrl    <= reset_sp;
1519
                       pc_ctrl    <= reset_pc;
1520
                            ea_ctrl    <= reset_ea;
1521
                                 md_ctrl    <= reset_md;
1522
                                 iv_ctrl    <= reset_iv;
1523
                                 nmi_ctrl   <= reset_nmi;
1524
                       next_state <= vect_hi_state;
1525
 
1526
                         --
1527
                         -- Jump via interrupt vector
1528
                         -- iv holds interrupt type
1529
                         -- fetch PC hi from vector location
1530
                         --
1531
          when vect_hi_state =>
1532
                                 -- fetch pc low interrupt vector
1533
                       pc_ctrl    <= pull_hi_pc;
1534
             addr_ctrl  <= int_hi_ad;
1535
                       next_state <= vect_lo_state;
1536
                         --
1537
                         -- jump via interrupt vector
1538
                         -- iv holds vector type
1539
                         -- fetch PC lo from vector location
1540
                         --
1541
          when vect_lo_state =>
1542
                                 -- fetch the vector low byte
1543
                       pc_ctrl    <= pull_lo_pc;
1544
             addr_ctrl  <= int_lo_ad;
1545
                       next_state <= fetch_state;
1546
                         --
1547
                         -- Here to fetch an instruction
1548
                         -- PC points to opcode
1549
                         -- Should service interrupt requests at this point
1550
                         -- either from the timer
1551
                         -- or from the external input.
1552
                         --
1553
          when fetch_state =>
1554
                                   -- fetch the op code
1555
                              op_ctrl    <= fetch_op;
1556
               pre_ctrl   <= fetch_pre;
1557
               ea_ctrl    <= reset_ea;
1558
                                   -- Fetch op code
1559
               addr_ctrl  <= fetch_ad;
1560
                                   --
1561
                                        case op_code(7 downto 6) is
1562
                                        when "10" => -- acca
1563
                                     case op_code(3 downto 0) is
1564
                                          when "0000" => -- suba
1565
                                            left_ctrl  <= acca_left;
1566
                                            right_ctrl <= md_right;
1567
                                            alu_ctrl   <= alu_sub8;
1568
                                                 cc_ctrl    <= load_cc;
1569
                                            acca_ctrl  <= load_acca;
1570
                                          when "0001" => -- cmpa
1571
                                            left_ctrl   <= acca_left;
1572
                                            right_ctrl  <= md_right;
1573
                                            alu_ctrl    <= alu_sub8;
1574
                                                 cc_ctrl     <= load_cc;
1575
                                          when "0010" => -- sbca
1576
                                            left_ctrl   <= acca_left;
1577
                                            right_ctrl  <= md_right;
1578
                                            alu_ctrl    <= alu_sbc;
1579
                                                 cc_ctrl     <= load_cc;
1580
                                            acca_ctrl   <= load_acca;
1581
                                          when "0011" =>
1582
                                            case pre_code is
1583
                                                 when "00010000" => -- page 2 -- cmpd
1584
                                              left_ctrl   <= accd_left;
1585
                                              right_ctrl  <= md_right;
1586
                                              alu_ctrl    <= alu_sub16;
1587
                                                   cc_ctrl     <= load_cc;
1588
                                                 when "00010001" => -- page 3 -- cmpu
1589
                                              left_ctrl   <= up_left;
1590
                                              right_ctrl  <= md_right;
1591
                                              alu_ctrl    <= alu_sub16;
1592
                                                   cc_ctrl     <= load_cc;
1593
                                                 when others => -- page 1 -- subd
1594
                                              left_ctrl   <= accd_left;
1595
                                              right_ctrl  <= md_right;
1596
                                              alu_ctrl    <= alu_sub16;
1597
                                                   cc_ctrl     <= load_cc;
1598
                                              acca_ctrl   <= load_hi_acca;
1599
                                                   accb_ctrl   <= load_accb;
1600
                                                 end case;
1601
                                          when "0100" => -- anda
1602
                                            left_ctrl   <= acca_left;
1603
                                            right_ctrl  <= md_right;
1604
                                            alu_ctrl    <= alu_and;
1605
                                                 cc_ctrl     <= load_cc;
1606
                                            acca_ctrl   <= load_acca;
1607
                                          when "0101" => -- bita
1608
                                            left_ctrl   <= acca_left;
1609
                                            right_ctrl  <= md_right;
1610
                                            alu_ctrl    <= alu_and;
1611
                                                 cc_ctrl     <= load_cc;
1612
                                          when "0110" => -- ldaa
1613
                                            left_ctrl   <= acca_left;
1614
                                            right_ctrl  <= md_right;
1615
                                            alu_ctrl    <= alu_ld8;
1616
                                                 cc_ctrl     <= load_cc;
1617
                                            acca_ctrl   <= load_acca;
1618
                                          when "0111" => -- staa
1619
                                            left_ctrl   <= acca_left;
1620
                                            right_ctrl  <= md_right;
1621
                                            alu_ctrl    <= alu_st8;
1622
                                                 cc_ctrl     <= load_cc;
1623
                                          when "1000" => -- eora
1624
                                            left_ctrl   <= acca_left;
1625
                                            right_ctrl  <= md_right;
1626
                                            alu_ctrl    <= alu_eor;
1627
                                                 cc_ctrl     <= load_cc;
1628
                                            acca_ctrl   <= load_acca;
1629
                                          when "1001" => -- adca
1630
                                            left_ctrl   <= acca_left;
1631
                                            right_ctrl  <= md_right;
1632
                                            alu_ctrl    <= alu_adc;
1633
                                                 cc_ctrl     <= load_cc;
1634
                                            acca_ctrl   <= load_acca;
1635
                                          when "1010" => -- oraa
1636
                                            left_ctrl   <= acca_left;
1637
                                            right_ctrl  <= md_right;
1638
                                            alu_ctrl    <= alu_ora;
1639
                                                 cc_ctrl     <= load_cc;
1640
                                            acca_ctrl   <= load_acca;
1641
                                          when "1011" => -- adda
1642
                                            left_ctrl   <= acca_left;
1643
                                            right_ctrl  <= md_right;
1644
                                            alu_ctrl    <= alu_add8;
1645
                                                 cc_ctrl     <= load_cc;
1646
                                            acca_ctrl   <= load_acca;
1647
                                          when "1100" =>
1648
                                            case pre_code is
1649
                                                 when "00010000" => -- page 2 -- cmpy
1650
                                              left_ctrl   <= iy_left;
1651
                                              right_ctrl  <= md_right;
1652
                                              alu_ctrl    <= alu_sub16;
1653
                                                   cc_ctrl     <= load_cc;
1654
                                                 when "00010001" => -- page 3 -- cmps
1655
                                              left_ctrl   <= sp_left;
1656
                                              right_ctrl  <= md_right;
1657
                                              alu_ctrl    <= alu_sub16;
1658
                                                   cc_ctrl     <= load_cc;
1659
                                                 when others => -- page 1 -- cmpx
1660
                                              left_ctrl   <= ix_left;
1661
                                              right_ctrl  <= md_right;
1662
                                              alu_ctrl    <= alu_sub16;
1663
                                                   cc_ctrl     <= load_cc;
1664
                                                 end case;
1665
                                          when "1101" => -- bsr / jsr
1666
                                            null;
1667
                                          when "1110" => -- ldx
1668
                                            case pre_code is
1669
                                                 when "00010000" => -- page 2 -- ldy
1670
                                              left_ctrl   <= iy_left;
1671
                                              right_ctrl  <= md_right;
1672
                                              alu_ctrl    <= alu_ld16;
1673
                                                   cc_ctrl     <= load_cc;
1674
                     iy_ctrl     <= load_iy;
1675
                                                 when others =>   -- page 1 -- ldx
1676
                                              left_ctrl   <= ix_left;
1677
                                              right_ctrl  <= md_right;
1678
                                              alu_ctrl    <= alu_ld16;
1679
                                                   cc_ctrl     <= load_cc;
1680
                     ix_ctrl     <= load_ix;
1681
                                                 end case;
1682
                                          when "1111" => -- stx
1683
                                            case pre_code is
1684
                                                 when "00010000" => -- page 2 -- sty
1685
                                              left_ctrl   <= iy_left;
1686
                                              right_ctrl  <= md_right;
1687
                                              alu_ctrl    <= alu_st16;
1688
                                                   cc_ctrl     <= load_cc;
1689
                                                 when others =>     -- page 1 -- stx
1690
                                              left_ctrl   <= ix_left;
1691
                                              right_ctrl  <= md_right;
1692
                                              alu_ctrl    <= alu_st16;
1693
                                                   cc_ctrl     <= load_cc;
1694
                                                 end case;
1695
                                          when others =>
1696
                                            null;
1697
                                          end case;
1698
                                        when "11" => -- accb dual op
1699
                                     case op_code(3 downto 0) is
1700
                                          when "0000" => -- subb
1701
                                            left_ctrl   <= accb_left;
1702
                                            right_ctrl  <= md_right;
1703
                                            alu_ctrl    <= alu_sub8;
1704
                                                 cc_ctrl     <= load_cc;
1705
                   accb_ctrl   <= load_accb;
1706
                                          when "0001" => -- cmpb
1707
                                            left_ctrl   <= accb_left;
1708
                                            right_ctrl  <= md_right;
1709
                                            alu_ctrl    <= alu_sub8;
1710
                                                 cc_ctrl     <= load_cc;
1711
                                          when "0010" => -- sbcb
1712
                                            left_ctrl   <= accb_left;
1713
                                            right_ctrl  <= md_right;
1714
                                            alu_ctrl    <= alu_sbc;
1715
                                                 cc_ctrl     <= load_cc;
1716
                   accb_ctrl   <= load_accb;
1717
                                          when "0011" => -- addd
1718
                                            left_ctrl   <= accd_left;
1719
                                            right_ctrl  <= md_right;
1720
                                            alu_ctrl    <= alu_add16;
1721
                                                 cc_ctrl     <= load_cc;
1722
                                            acca_ctrl   <= load_hi_acca;
1723
                                                 accb_ctrl   <= load_accb;
1724
                                          when "0100" => -- andb
1725
                                            left_ctrl   <= accb_left;
1726
                                            right_ctrl  <= md_right;
1727
                                            alu_ctrl    <= alu_and;
1728
                                                 cc_ctrl     <= load_cc;
1729
                   accb_ctrl   <= load_accb;
1730
                                          when "0101" => -- bitb
1731
                                            left_ctrl   <= accb_left;
1732
                                            right_ctrl  <= md_right;
1733
                                            alu_ctrl    <= alu_and;
1734
                                                 cc_ctrl     <= load_cc;
1735
                                          when "0110" => -- ldab
1736
                                            left_ctrl   <= accb_left;
1737
                                            right_ctrl  <= md_right;
1738
                                            alu_ctrl    <= alu_ld8;
1739
                                                 cc_ctrl     <= load_cc;
1740
                   accb_ctrl   <= load_accb;
1741
                                          when "0111" => -- stab
1742
                                            left_ctrl   <= accb_left;
1743
                                            right_ctrl  <= md_right;
1744
                                            alu_ctrl    <= alu_st8;
1745
                                                 cc_ctrl     <= load_cc;
1746
                                          when "1000" => -- eorb
1747
                                            left_ctrl   <= accb_left;
1748
                                            right_ctrl  <= md_right;
1749
                                            alu_ctrl    <= alu_eor;
1750
                                                 cc_ctrl     <= load_cc;
1751
                   accb_ctrl   <= load_accb;
1752
                                          when "1001" => -- adcb
1753
                                            left_ctrl   <= accb_left;
1754
                                            right_ctrl  <= md_right;
1755
                                            alu_ctrl    <= alu_adc;
1756
                                                 cc_ctrl     <= load_cc;
1757
                   accb_ctrl   <= load_accb;
1758
                                          when "1010" => -- orab
1759
                                            left_ctrl   <= accb_left;
1760
                                            right_ctrl  <= md_right;
1761
                                            alu_ctrl    <= alu_ora;
1762
                                                 cc_ctrl     <= load_cc;
1763
                   accb_ctrl   <= load_accb;
1764
                                          when "1011" => -- addb
1765
                                            left_ctrl   <= accb_left;
1766
                                            right_ctrl  <= md_right;
1767
                                            alu_ctrl    <= alu_add8;
1768
                                                 cc_ctrl     <= load_cc;
1769
                   accb_ctrl   <= load_accb;
1770
                                          when "1100" => -- ldd
1771
                                            left_ctrl   <= accd_left;
1772
                                            right_ctrl  <= md_right;
1773
                                            alu_ctrl    <= alu_ld16;
1774
                                                 cc_ctrl     <= load_cc;
1775
                                            acca_ctrl   <= load_hi_acca;
1776
                   accb_ctrl   <= load_accb;
1777
                                          when "1101" => -- std
1778
                                            left_ctrl   <= accd_left;
1779
                                            right_ctrl  <= md_right;
1780
                                            alu_ctrl    <= alu_st16;
1781
                                                 cc_ctrl     <= load_cc;
1782
                                          when "1110" => -- ldu
1783
                                            case pre_code is
1784
                                                 when "00010000" => -- page 2 -- lds
1785
                                              left_ctrl   <= sp_left;
1786
                                              right_ctrl  <= md_right;
1787
                                              alu_ctrl    <= alu_ld16;
1788
                                                   cc_ctrl     <= load_cc;
1789
                                                   sp_ctrl     <= load_sp;
1790
                                                 when others => -- page 1 -- ldu
1791
                                              left_ctrl   <= up_left;
1792
                                              right_ctrl  <= md_right;
1793
                                              alu_ctrl    <= alu_ld16;
1794
                                                   cc_ctrl     <= load_cc;
1795
                     up_ctrl     <= load_up;
1796
                                                 end case;
1797
                                          when "1111" =>
1798
                                            case pre_code is
1799
                                                 when "00010000" => -- page 2 -- sts
1800
                                              left_ctrl   <= sp_left;
1801
                                              right_ctrl  <= md_right;
1802
                                              alu_ctrl    <= alu_st16;
1803
                                                   cc_ctrl     <= load_cc;
1804
                                                 when others =>     -- page 1 -- stu
1805
                                              left_ctrl   <= up_left;
1806
                                              right_ctrl  <= md_right;
1807
                                              alu_ctrl    <= alu_st16;
1808
                                                   cc_ctrl     <= load_cc;
1809
                                                 end case;
1810
                                          when others =>
1811
                                            null;
1812
                                          end case;
1813
                                        when others =>
1814
                                          null;
1815
                                        end case;
1816
                                 if halt = '1' then
1817
                              iv_ctrl    <= reset_iv;
1818
                              next_state <= halt_state;
1819
                                 -- service non maskable interrupts
1820
                            elsif (nmi_req = '1') and (nmi_ack = '0') then
1821
                              iv_ctrl    <= nmi_iv;
1822
                                   nmi_ctrl   <= set_nmi;
1823
                              next_state <= int_nmiirq_state;
1824
                                 -- service maskable interrupts
1825
                            else
1826
                                   --
1827
                                        -- nmi request is not cleared until nmi input goes low
1828
                                        --
1829
                                   if(nmi_req = '0') and (nmi_ack='1') then
1830
                                     nmi_ctrl <= reset_nmi;
1831
                                        end if;
1832
                                        --
1833
                                        -- FIRQ & IRQ are level sensitive
1834
                                        --
1835
               if (firq = '1') and (cc(FBIT) = '0') then
1836
                                iv_ctrl    <= firq_iv;
1837
                                next_state <= int_firq_state;
1838
                                   elsif (irq = '1') and (cc(IBIT) = '0') then
1839
                                iv_ctrl    <= irq_iv;
1840
                                next_state <= int_nmiirq_state;
1841
               else
1842
                                     -- Advance the PC to fetch next instruction byte
1843
                                iv_ctrl    <= reset_iv; -- default to reset
1844
                 pc_ctrl    <= incr_pc;
1845
                                next_state <= decode1_state;
1846
               end if;
1847
                                 end if;
1848
                          --
1849
                          -- Here to decode instruction
1850
                          -- and fetch next byte of intruction
1851
                          -- whether it be necessary or not
1852
                          --
1853
           when decode1_state =>
1854
                                 -- fetch first byte of address or immediate data
1855
             ea_ctrl    <= fetch_first_ea;
1856
                                 md_ctrl    <= fetch_first_md;
1857
             addr_ctrl  <= fetch_ad;
1858
                            case op_code(7 downto 4) is
1859
                                 --
1860
                                 -- direct single op (2 bytes)
1861
                                 -- 6809 => 6 cycles
1862
                                 -- cpu09 => 5 cycles
1863
                            -- 1 op=(pc) / pc=pc+1
1864
                                 -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1865
                                 -- 3 md_lo=(ea) / pc=pc
1866
                                 -- 4 alu_left=md / md=alu_out / pc=pc
1867
                                 -- 5 (ea)=md_lo / pc=pc
1868
                                 --
1869
                                 -- Exception is JMP
1870
                            -- 6809 => 3 cycles
1871
                                 -- cpu09 => 3 cycles
1872
                                 -- 1 op=(pc) / pc=pc+1
1873
                                 -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1874
                                 -- 3 pc=ea
1875
                                 --
1876
                  when "0000" =>
1877
                                        -- advance the PC
1878
               pc_ctrl    <= incr_pc;
1879
                                        case op_code(3 downto 0) is
1880
                                   when "1110" => -- jmp
1881
                                     next_state <= jmp_state;
1882
                                        when "1111" => -- clr
1883
                                     next_state <= single_op_exec_state;
1884
                                        when others =>
1885
                                     next_state <= single_op_read_state;
1886
                                        end case;
1887
 
1888
                                 -- acca / accb inherent instructions
1889
                  when "0001" =>
1890
                    case op_code(3 downto 0) is
1891
                                        --
1892
                                        -- Page2 pre byte
1893
                                        -- pre=(pc) / pc=pc+1
1894
                                        -- op=(pc) / pc=pc+1
1895
                                        --
1896
                         when "0000" => -- page2
1897
                                op_ctrl    <= fetch_op;
1898
                                          -- advance pc
1899
                 pc_ctrl    <= incr_pc;
1900
                                          next_state <= decode2_state;
1901
 
1902
                                        --
1903
                                        -- Page3 pre byte
1904
                                        -- pre=(pc) / pc=pc+1
1905
                                        -- op=(pc) / pc=pc+1
1906
                                        --
1907
                         when "0001" => -- page3
1908
                                op_ctrl    <= fetch_op;
1909
                                          -- advance pc
1910
                 pc_ctrl    <= incr_pc;
1911
                                          next_state <= decode3_state;
1912
 
1913
                                        --
1914
                                        -- nop - No operation ( 1 byte )
1915
                                        -- 6809 => 2 cycles
1916
                                        -- cpu09 => 2 cycles
1917
                                        -- 1 op=(pc) / pc=pc+1
1918
                                        -- 2 decode
1919
                                        -- 
1920
                         when "0010" => -- nop
1921
                                          next_state   <= fetch_state;
1922
 
1923
                                        --
1924
                                        -- sync - halt execution until an interrupt is received
1925
                                        -- interrupt may be NMI, IRQ or FIRQ
1926
                                        -- program execution continues if the 
1927
                                        -- interrupt is asserted for 3 clock cycles
1928
                                        -- note that registers are not pushed onto the stack
1929
                                        -- CPU09 => Interrupts need only be asserted for one clock cycle
1930
                                        --
1931
                         when "0011" => -- sync
1932
                                          next_state   <= sync_state;
1933
 
1934
                                        --
1935
                                        -- lbra -- long branch (3 bytes)
1936
                                        -- 6809 => 5 cycles
1937
                                        -- cpu09 => 4 cycles
1938
                                        -- 1 op=(pc) / pc=pc+1
1939
                                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
1940
                                        -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1941
                                        -- 4 pc=pc+md
1942
                                        --
1943
                         when "0110" =>
1944
                                          -- increment the pc
1945
                 pc_ctrl    <= incr_pc;
1946
                                          next_state <= lbranch_state;
1947
 
1948
                                        --
1949
                                        -- lbsr - long branch to subroutine (3 bytes)
1950
                                        -- 6809 => 9 cycles
1951
                                        -- cpu09 => 6 cycles
1952
                                        -- 1 op=(pc) /pc=pc+1
1953
                                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
1954
                                        -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1955
                                        -- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
1956
                                        -- 5 (sp)=pc_hi / pc=pc
1957
                                        -- 6 pc=pc+md
1958
                                        --
1959
                         when "0111" =>
1960
                                          -- pre decrement sp
1961
                 left_ctrl  <= sp_left;
1962
                 right_ctrl <= one_right;
1963
                 alu_ctrl   <= alu_sub16;
1964
                 sp_ctrl    <= load_sp;
1965
                                          -- increment the pc
1966
                 pc_ctrl    <= incr_pc;
1967
                                          next_state <= lbranch_state;
1968
 
1969
                         when "1001" => -- daa
1970
                                          left_ctrl  <= acca_left;
1971
                      right_ctrl <= accb_right;
1972
                                          alu_ctrl   <= alu_daa;
1973
                 cc_ctrl    <= load_cc;
1974
                                          acca_ctrl  <= load_acca;
1975
                                          next_state <= fetch_state;
1976
 
1977
                         when "1010" => -- orcc
1978
                                          -- increment the pc
1979
                 pc_ctrl      <= incr_pc;
1980
                                     st_ctrl      <= push_st;
1981
                                     return_state <= fetch_state;
1982
                                          next_state   <= orcc_state;
1983
 
1984
                         when "1100" => -- andcc
1985
                                          -- increment the pc
1986
                 pc_ctrl      <= incr_pc;
1987
                                     st_ctrl      <= push_st;
1988
                                     return_state <= fetch_state;
1989
                                          next_state   <= andcc_state;
1990
 
1991
                         when "1101" => -- sex
1992
                                          -- have sex
1993
                 left_ctrl  <= accb_left;
1994
                 right_ctrl <= zero_right;
1995
                 alu_ctrl   <= alu_sex;
1996
                                          cc_ctrl    <= load_cc;
1997
                                          acca_ctrl  <= load_hi_acca;
1998
                                          next_state <= fetch_state;
1999
 
2000
                         when "1110" => -- exg
2001
                                          -- increment the pc
2002
                 pc_ctrl    <= incr_pc;
2003
                                          next_state <= exg_state;
2004
 
2005
                         when "1111" => -- tfr
2006
                                          -- increment the pc
2007
                 pc_ctrl      <= incr_pc;
2008
                                          -- call transfer as a subroutine
2009
                                     st_ctrl      <= push_st;
2010
                                     return_state <= fetch_state;
2011
                                          next_state   <= tfr_state;
2012
 
2013
                         when others =>
2014
                                          -- increment the pc
2015
                 pc_ctrl    <= incr_pc;
2016
                                          next_state <= fetch_state;
2017
                         end case;
2018
             --
2019
                                 -- Short branch conditional
2020
                                 -- 6809 => always 3 cycles
2021
                                 -- cpu09 => always = 3 cycles
2022
                                 -- 1 op=(pc) / pc=pc+1
2023
                                 -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
2024
                                 -- 3 if cc tru pc=pc+md else pc=pc
2025
                                 --
2026
                  when "0010" => -- branch conditional
2027
                                        -- increment the pc
2028
               pc_ctrl    <= incr_pc;
2029
               next_state <= sbranch_state;
2030
                                 --
2031
                                 -- Single byte stack operators
2032
                                 -- Do not advance PC
2033
                                 --
2034
                  when "0011" =>
2035
                                        --
2036
                                        -- lea - load effective address (2+ bytes)
2037
                                        -- 6809 => 4 cycles + addressing mode
2038
                                        -- cpu09 => 4 cycles + addressing mode
2039
                                        -- 1 op=(pc) / pc=pc+1
2040
                                        -- 2 md_lo=(pc) / pc=pc+1
2041
                                        -- 3 calculate ea
2042
                                        -- 4 ix/iy/sp/up = ea
2043
                                        --
2044
                    case op_code(3 downto 0) is
2045
                         when "0000" |  -- leax
2046
                              "0001" |  -- leay
2047
                              "0010" |  -- leas
2048
                              "0011" => -- leau
2049
                                                -- advance PC
2050
                  pc_ctrl      <= incr_pc;
2051
                                      st_ctrl      <= push_st;
2052
                                      return_state <= lea_state;
2053
                                                next_state   <= indexed_state;
2054
 
2055
                                        --
2056
                                        -- pshs - push registers onto sp stack
2057
                                        -- 6809 => 5 cycles + registers
2058
                                        -- cpu09 => 3 cycles + registers
2059
                                        --  1 op=(pc) / pc=pc+1
2060
                                        --  2 ea_lo=(pc) / pc=pc+1 
2061
                                        --  3 if ea(7 downto 0) != "00000000" then sp=sp-1
2062
                                        --  4 if ea(7) = 1 (sp)=pcl, sp=sp-1
2063
                                        --  5 if ea(7) = 1 (sp)=pch
2064
                                        --    if ea(6 downto 0) != "0000000" then sp=sp-1
2065
                                        --  6 if ea(6) = 1 (sp)=upl, sp=sp-1
2066
                                        --  7 if ea(6) = 1 (sp)=uph
2067
                                        --    if ea(5 downto 0) != "000000" then sp=sp-1
2068
                                        --  8 if ea(5) = 1 (sp)=iyl, sp=sp-1
2069
                                        --  9 if ea(5) = 1 (sp)=iyh
2070
                                        --    if ea(4 downto 0) != "00000" then sp=sp-1
2071
                                        -- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
2072
                                        -- 11 if ea(4) = 1 (sp)=ixh
2073
                                        --    if ea(3 downto 0) != "0000" then sp=sp-1
2074
                                        -- 12 if ea(3) = 1 (sp)=dp
2075
                                        --    if ea(2 downto 0) != "000" then sp=sp-1
2076
                                        -- 13 if ea(2) = 1 (sp)=accb
2077
                                        --    if ea(1 downto 0) != "00" then sp=sp-1
2078
                                        -- 14 if ea(1) = 1 (sp)=acca
2079
                                        --    if ea(0 downto 0) != "0" then sp=sp-1
2080
                                        -- 15 if ea(0) = 1 (sp)=cc
2081
                                        --
2082
                         when "0100" => -- pshs
2083
                                                -- advance PC
2084
                  pc_ctrl    <= incr_pc;
2085
                                                next_state <= pshs_state;
2086
 
2087
                                        --
2088
                                        -- puls - pull registers of sp stack
2089
                                        -- 6809 => 5 cycles + registers
2090
                                        -- cpu09 => 3 cycles + registers
2091
                                        --
2092
                         when "0101" => -- puls
2093
                                                -- advance PC
2094
                  pc_ctrl    <= incr_pc;
2095
                                                next_state <= puls_state;
2096
 
2097
                                        --
2098
                                        -- pshu - push registers onto up stack
2099
                                        -- 6809 => 5 cycles + registers
2100
                                        -- cpu09 => 3 cycles + registers
2101
                                        --
2102
                         when "0110" => -- pshu
2103
                                                -- advance PC
2104
                  pc_ctrl    <= incr_pc;
2105
                                                next_state <= pshu_state;
2106
 
2107
                                        --
2108
                                        -- pulu - pull registers of up stack
2109
                                        -- 6809 => 5 cycles + registers
2110
                                        -- cpu09 => 3 cycles + registers
2111
                                        --
2112
                         when "0111" => -- pulu
2113
                                                -- advance PC
2114
                  pc_ctrl    <= incr_pc;
2115
                                                next_state <= pulu_state;
2116
 
2117
                                        --
2118
                                        -- rts - return from subroutine
2119
                                        -- 6809 => 5 cycles
2120
                                        -- cpu09 => 4 cycles 
2121
                                        -- 1 op=(pc) / pc=pc+1
2122
                                        -- 2 decode op
2123
                                        -- 3 pc_hi = (sp) / sp=sp+1
2124
                                        -- 4 pc_lo = (sp) / sp=sp+1
2125
                                        --
2126
                         when "1001" =>
2127
                                      st_ctrl      <= push_st;
2128
                                      return_state <= fetch_state;
2129
                                                next_state   <= pull_return_hi_state;
2130
 
2131
                                        --
2132
                                        -- add accb to index register
2133
                                        -- *** Note: this is an unsigned addition.
2134
                                        --           does not affect any condition codes
2135
                                        -- 6809 => 3 cycles
2136
                                        -- cpu09 => 2 cycles
2137
                                        -- 1 op=(pc) / pc=pc+1
2138
                                        -- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
2139
                                        --
2140
                         when "1010" => -- abx
2141
                            left_ctrl  <= ix_left;
2142
                            right_ctrl <= accb_right;
2143
                                                alu_ctrl   <= alu_abx;
2144
                                                ix_ctrl    <= load_ix;
2145
                                                next_state <= fetch_state;
2146
 
2147
                         when "1011" => -- rti
2148
                                                next_state <= rti_cc_state;
2149
 
2150
                         when "1100" => -- cwai #$<cc_mask>
2151
                                           -- pre decrement sp
2152
                            left_ctrl    <= sp_left;
2153
                            right_ctrl   <= one_right;
2154
                                                alu_ctrl     <= alu_sub16;
2155
                                                sp_ctrl      <= load_sp;
2156
                  iv_ctrl      <= reset_iv;
2157
                                                --      increment pc
2158
                  pc_ctrl      <= incr_pc;
2159
                                      st_ctrl      <= push_st;
2160
                                      return_state <= int_entire_state; -- set entire flag
2161
                                                next_state   <= andcc_state;
2162
 
2163
                         when "1101" => -- mul
2164
                                                next_state <= mul_state;
2165
 
2166
                         when "1111" => -- swi
2167
                                           -- predecrement SP
2168
                            left_ctrl  <= sp_left;
2169
                            right_ctrl <= one_right;
2170
                                                alu_ctrl   <= alu_sub16;
2171
                                                sp_ctrl    <= load_sp;
2172
                  iv_ctrl    <= swi_iv;
2173
                                                next_state <= int_entire_state;
2174
 
2175
                         when others =>
2176
                                                next_state <= fetch_state;
2177
 
2178
                         end case;
2179
                                 --
2180
                                 -- Accumulator A Single operand
2181
                                 -- source = acca, dest = acca
2182
                                 -- Do not advance PC
2183
                                 -- Typically 2 cycles 1 bytes
2184
                                 -- 1 opcode fetch
2185
                                 -- 2 post byte fetch / instruction decode
2186
                                 -- Note that there is no post byte
2187
                                 -- so do not advance PC in decode cycle
2188
                                 -- Re-run opcode fetch cycle after decode
2189
                                 -- 
2190
                  when "0100" => -- acca single op
2191
                         left_ctrl  <= acca_left;
2192
                    case op_code(3 downto 0) is
2193
                         when "0000" => -- neg
2194
                                          right_ctrl <= zero_right;
2195
                                          alu_ctrl   <= alu_neg;
2196
                                          acca_ctrl  <= load_acca;
2197
                                          cc_ctrl    <= load_cc;
2198
                    when "0011" => -- com
2199
                           right_ctrl <= zero_right;
2200
                                          alu_ctrl   <= alu_com;
2201
                                          acca_ctrl  <= load_acca;
2202
                                          cc_ctrl    <= load_cc;
2203
                         when "0100" => -- lsr
2204
                           right_ctrl <= zero_right;
2205
                                          alu_ctrl   <= alu_lsr8;
2206
                                          acca_ctrl  <= load_acca;
2207
                                          cc_ctrl    <= load_cc;
2208
                         when "0110" => -- ror
2209
                           right_ctrl <= zero_right;
2210
                                          alu_ctrl   <= alu_ror8;
2211
                                          acca_ctrl  <= load_acca;
2212
                                          cc_ctrl    <= load_cc;
2213
                         when "0111" => -- asr
2214
                           right_ctrl <= zero_right;
2215
                                          alu_ctrl   <= alu_asr8;
2216
                                          acca_ctrl  <= load_acca;
2217
                                          cc_ctrl    <= load_cc;
2218
                         when "1000" => -- asl
2219
                           right_ctrl <= zero_right;
2220
                                          alu_ctrl   <= alu_asl8;
2221
                                          acca_ctrl  <= load_acca;
2222
                                          cc_ctrl    <= load_cc;
2223
                         when "1001" => -- rol
2224
                           right_ctrl <= zero_right;
2225
                                          alu_ctrl   <= alu_rol8;
2226
                                          acca_ctrl  <= load_acca;
2227
                                          cc_ctrl    <= load_cc;
2228
                         when "1010" => -- dec
2229
                           right_ctrl <= one_right;
2230
                                          alu_ctrl   <= alu_dec;
2231
                                          acca_ctrl  <= load_acca;
2232
                                          cc_ctrl    <= load_cc;
2233
                         when "1011" => -- undefined
2234
                           right_ctrl <= zero_right;
2235
                                          alu_ctrl   <= alu_nop;
2236
                                          acca_ctrl  <= latch_acca;
2237
                                          cc_ctrl    <= latch_cc;
2238
                         when "1100" => -- inc
2239
                           right_ctrl <= one_right;
2240
                                          alu_ctrl   <= alu_inc;
2241
                                          acca_ctrl  <= load_acca;
2242
                                          cc_ctrl    <= load_cc;
2243
                         when "1101" => -- tst
2244
                           right_ctrl <= zero_right;
2245
                                          alu_ctrl   <= alu_st8;
2246
                                          acca_ctrl  <= latch_acca;
2247
                                          cc_ctrl    <= load_cc;
2248
                         when "1110" => -- jmp (not defined)
2249
                           right_ctrl <= zero_right;
2250
                                          alu_ctrl   <= alu_nop;
2251
                                          acca_ctrl  <= latch_acca;
2252
                                          cc_ctrl    <= latch_cc;
2253
                         when "1111" => -- clr
2254
                           right_ctrl <= zero_right;
2255
                                          alu_ctrl   <= alu_clr;
2256
                                          acca_ctrl  <= load_acca;
2257
                                          cc_ctrl    <= load_cc;
2258
                         when others =>
2259
                           right_ctrl <= zero_right;
2260
                                          alu_ctrl   <= alu_nop;
2261
                                          acca_ctrl  <= latch_acca;
2262
                                          cc_ctrl    <= latch_cc;
2263
                         end case;
2264
                                   next_state <= fetch_state;
2265
                                 --
2266
                                 -- Single Operand accb
2267
                                 -- source = accb, dest = accb
2268
                                 -- Typically 2 cycles 1 bytes
2269
                                 -- 1 opcode fetch
2270
                                 -- 2 post byte fetch / instruction decode
2271
                                 -- Note that there is no post byte
2272
                                 -- so do not advance PC in decode cycle
2273
                                 -- Re-run opcode fetch cycle after decode
2274
                                 --
2275
                  when "0101" =>
2276
                         left_ctrl  <= accb_left;
2277
                    case op_code(3 downto 0) is
2278
                         when "0000" => -- neg
2279
                                          right_ctrl <= zero_right;
2280
                                          alu_ctrl   <= alu_neg;
2281
                                          accb_ctrl  <= load_accb;
2282
                                          cc_ctrl    <= load_cc;
2283
                    when "0011" => -- com
2284
                           right_ctrl <= zero_right;
2285
                                          alu_ctrl   <= alu_com;
2286
                                          accb_ctrl  <= load_accb;
2287
                                          cc_ctrl    <= load_cc;
2288
                         when "0100" => -- lsr
2289
                           right_ctrl <= zero_right;
2290
                                          alu_ctrl   <= alu_lsr8;
2291
                                          accb_ctrl  <= load_accb;
2292
                                          cc_ctrl    <= load_cc;
2293
                         when "0110" => -- ror
2294
                           right_ctrl <= zero_right;
2295
                                          alu_ctrl   <= alu_ror8;
2296
                                          accb_ctrl  <= load_accb;
2297
                                          cc_ctrl    <= load_cc;
2298
                         when "0111" => -- asr
2299
                           right_ctrl <= zero_right;
2300
                                          alu_ctrl   <= alu_asr8;
2301
                                          accb_ctrl  <= load_accb;
2302
                                          cc_ctrl    <= load_cc;
2303
                         when "1000" => -- asl
2304
                           right_ctrl <= zero_right;
2305
                                          alu_ctrl   <= alu_asl8;
2306
                                          accb_ctrl  <= load_accb;
2307
                                          cc_ctrl    <= load_cc;
2308
                         when "1001" => -- rol
2309
                           right_ctrl <= zero_right;
2310
                                          alu_ctrl   <= alu_rol8;
2311
                                          accb_ctrl  <= load_accb;
2312
                                          cc_ctrl    <= load_cc;
2313
                         when "1010" => -- dec
2314
                           right_ctrl <= one_right;
2315
                                          alu_ctrl   <= alu_dec;
2316
                                          accb_ctrl  <= load_accb;
2317
                                          cc_ctrl    <= load_cc;
2318
                         when "1011" => -- undefined
2319
                           right_ctrl <= zero_right;
2320
                                          alu_ctrl   <= alu_nop;
2321
                                          accb_ctrl  <= latch_accb;
2322
                                          cc_ctrl    <= latch_cc;
2323
                         when "1100" => -- inc
2324
                           right_ctrl <= one_right;
2325
                                          alu_ctrl   <= alu_inc;
2326
                                          accb_ctrl  <= load_accb;
2327
                                          cc_ctrl    <= load_cc;
2328
                         when "1101" => -- tst
2329
                           right_ctrl <= zero_right;
2330
                                          alu_ctrl   <= alu_st8;
2331
                                          accb_ctrl  <= latch_accb;
2332
                                          cc_ctrl    <= load_cc;
2333
                         when "1110" => -- jmp (undefined)
2334
                           right_ctrl <= zero_right;
2335
                                          alu_ctrl   <= alu_nop;
2336
                                          accb_ctrl  <= latch_accb;
2337
                                          cc_ctrl    <= latch_cc;
2338
                         when "1111" => -- clr
2339
                           right_ctrl <= zero_right;
2340
                                          alu_ctrl   <= alu_clr;
2341
                                          accb_ctrl  <= load_accb;
2342
                                          cc_ctrl    <= load_cc;
2343
                         when others =>
2344
                           right_ctrl <= zero_right;
2345
                                          alu_ctrl   <= alu_nop;
2346
                                          accb_ctrl  <= latch_accb;
2347
                                          cc_ctrl    <= latch_cc;
2348
                         end case;
2349
                                   next_state   <= fetch_state;
2350
                                 --
2351
                                 -- Single operand indexed
2352
                                 -- Two byte instruction so advance PC
2353
                                 -- EA should hold index offset
2354
                                 --
2355
                  when "0110" => -- indexed single op
2356
                                        -- increment the pc 
2357
               pc_ctrl    <= incr_pc;
2358
                                   st_ctrl    <= push_st;
2359
                                        case op_code(3 downto 0) is
2360
                                   when "1110" => -- jmp
2361
                                     return_state <= jmp_state;
2362
                                        when "1111" => -- clr
2363
                                     return_state <= single_op_exec_state;
2364
                                        when others =>
2365
                                     return_state <= single_op_read_state;
2366
                                        end case;
2367
                                   next_state <= indexed_state;
2368
             --
2369
                                 -- Single operand extended addressing
2370
                                 -- three byte instruction so advance the PC
2371
                                 -- Low order EA holds high order address
2372
                                 --
2373
                  when "0111" => -- extended single op
2374
                                        -- increment PC
2375
               pc_ctrl    <= incr_pc;
2376
                                   st_ctrl    <= push_st;
2377
                                        case op_code(3 downto 0) is
2378
                                   when "1110" => -- jmp
2379
                                     return_state <= jmp_state;
2380
                                        when "1111" => -- clr
2381
                                     return_state <= single_op_exec_state;
2382
                                        when others =>
2383
                                     return_state <= single_op_read_state;
2384
                                        end case;
2385
                                   next_state <= extended_state;
2386
 
2387
                  when "1000" => -- acca immediate
2388
                                   -- increment the pc
2389
               pc_ctrl    <= incr_pc;
2390
                                        case op_code(3 downto 0) is
2391
               when "0011" | -- subd #
2392
                                             "1100" | -- cmpx #
2393
                                             "1110" => -- ldx #
2394
                                     st_ctrl      <= push_st;
2395
                                     return_state <= fetch_state;
2396
                                          next_state   <= imm16_state;
2397
 
2398
                                        --
2399
                                        -- bsr offset - Branch to subroutine (2 bytes)
2400
                                        -- 6809 => 7 cycles
2401
                                        -- cpu09 => 5 cycles
2402
                                        -- 1 op=(pc) / pc=pc+1
2403
                                   -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
2404
                                        -- 3 (sp)=pc_lo / sp=sp-1
2405
                                        -- 4 (sp)=pc_hi
2406
                                        -- 5 pc=pc+md
2407
                                        --
2408
                                        when "1101" => -- bsr
2409
                                          -- pre decrement SP
2410
                 left_ctrl  <= sp_left;
2411
                 right_ctrl <= one_right;
2412
                 alu_ctrl   <= alu_sub16;
2413
                                     sp_ctrl    <= load_sp;
2414
                                          --
2415
                                     st_ctrl      <= push_st;
2416
                                     return_state <= sbranch_state;
2417
                                          next_state   <= push_return_lo_state;
2418
 
2419
                                        when others =>
2420
                                     next_state   <= fetch_state;
2421
               end case;
2422
 
2423
                  when "1001" => -- acca direct
2424
                                        -- increment the pc
2425
               pc_ctrl    <= incr_pc;
2426
                                        case op_code(3 downto 0) is
2427
               when "0011" | -- subd
2428
                                             "1100" | -- cmpx
2429
                                             "1110" => -- ldx
2430
                                     next_state   <= dual_op_read16_state;
2431
 
2432
                                        when "0111" =>  -- sta direct
2433
                                     next_state <= dual_op_write8_state;
2434
 
2435
                                        when "1111" => -- stx direct
2436
                                          -- idle ALU
2437
                 left_ctrl  <= ix_left;
2438
                 right_ctrl <= zero_right;
2439
                 alu_ctrl   <= alu_nop;
2440
                                          cc_ctrl    <= latch_cc;
2441
                                     sp_ctrl    <= latch_sp;
2442
                                     next_state <= dual_op_write16_state;
2443
 
2444
                                        --
2445
                                        -- jsr direct - Jump to subroutine in direct page (2 bytes)
2446
                                        -- 6809 => 7 cycles
2447
                                        -- cpu09 => 5 cycles
2448
                                        -- 1 op=(pc) / pc=pc+1
2449
                                   -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
2450
                                        -- 3 (sp)=pc_lo / sp=sp-1
2451
                                        -- 4 (sp)=pc_hi
2452
                                        -- 5 pc=ea
2453
                                        --
2454
                                        when "1101" => -- jsr direct
2455
                                          -- pre decrement sp
2456
                 left_ctrl  <= sp_left;
2457
                 right_ctrl <= one_right;
2458
                 alu_ctrl   <= alu_sub16;
2459
                                     sp_ctrl    <= load_sp;
2460
                                          --
2461
                                     st_ctrl      <= push_st;
2462
                                     return_state <= jmp_state;
2463
                                          next_state   <= push_return_lo_state;
2464
 
2465
                                        when others =>
2466
                                     next_state   <= dual_op_read8_state;
2467
               end case;
2468
 
2469
                  when "1010" => -- acca indexed
2470
                                        -- increment the pc
2471
               pc_ctrl    <= incr_pc;
2472
                                        case op_code(3 downto 0) is
2473
               when "0011" | -- subd
2474
                                             "1100" | -- cmpx
2475
                                             "1110" => -- ldx
2476
                                     st_ctrl      <= push_st;
2477
                                     return_state <= dual_op_read16_state;
2478
                                     next_state   <= indexed_state;
2479
 
2480
                                        when "0111" =>  -- staa ,x
2481
                                     st_ctrl      <= push_st;
2482
                                     return_state <= dual_op_write8_state;
2483
                                     next_state   <= indexed_state;
2484
 
2485
                                        when "1111" => -- stx ,x
2486
                                     st_ctrl      <= push_st;
2487
                                     return_state <= dual_op_write16_state;
2488
                                     next_state   <= indexed_state;
2489
 
2490
                                        when "1101" => -- jsr ,x
2491
                                          -- DO NOT pre decrement SP
2492
                                     st_ctrl      <= push_st;
2493
                                     return_state <= jsr_state;
2494
                                          next_state   <= indexed_state;
2495
 
2496
                                        when others =>
2497
                                     st_ctrl      <= push_st;
2498
                                     return_state <= dual_op_read8_state;
2499
                                     next_state   <= indexed_state;
2500
               end case;
2501
 
2502
             when "1011" => -- acca extended
2503
                                        -- increment the pc
2504
               pc_ctrl    <= incr_pc;
2505
                                        case op_code(3 downto 0) is
2506
               when "0011" | -- subd
2507
                                             "1100" | -- cmpx
2508
                                             "1110" => -- ldx
2509
                                     st_ctrl      <= push_st;
2510
                                     return_state <= dual_op_read16_state;
2511
                                     next_state   <= extended_state;
2512
 
2513
                                        when "0111" =>  -- staa >
2514
                                     st_ctrl      <= push_st;
2515
                                     return_state <= dual_op_write8_state;
2516
                                     next_state   <= extended_state;
2517
 
2518
                                        when "1111" => -- stx >
2519
                                     st_ctrl      <= push_st;
2520
                                     return_state <= dual_op_write16_state;
2521
                                     next_state   <= extended_state;
2522
 
2523
                                        when "1101" => -- jsr >extended
2524
                                          -- DO NOT pre decrement sp
2525
                                     st_ctrl      <= push_st;
2526
                                     return_state <= jsr_state;
2527
                                          next_state   <= extended_state;
2528
 
2529
                                        when others =>
2530
                                     st_ctrl      <= push_st;
2531
                                     return_state <= dual_op_read8_state;
2532
                                     next_state   <= extended_state;
2533
               end case;
2534
 
2535
                  when "1100" => -- accb immediate
2536
                                        -- increment the pc
2537
               pc_ctrl    <= incr_pc;
2538
                                        case op_code(3 downto 0) is
2539
               when "0011" | -- addd #
2540
                                             "1100" | -- ldd #
2541
                                             "1110" => -- ldu #
2542
                                     st_ctrl      <= push_st;
2543
                                     return_state <= fetch_state;
2544
                                          next_state   <= imm16_state;
2545
 
2546
                                        when others =>
2547
                                     next_state   <= fetch_state;
2548
 
2549
               end case;
2550
 
2551
 
2552
                  when "1101" => -- accb direct
2553
                                        -- increment the pc
2554
               pc_ctrl    <= incr_pc;
2555
                                        case op_code(3 downto 0) is
2556
               when "0011" | -- addd
2557
                                             "1100" | -- ldd
2558
                                             "1110" => -- ldu
2559
                                     next_state   <= dual_op_read16_state;
2560
 
2561
                                        when "0111" =>  -- stab direct
2562
                                     next_state   <= dual_op_write8_state;
2563
 
2564
                                        when "1101" =>  -- std direct
2565
                                     next_state   <= dual_op_write16_state;
2566
 
2567
                                        when "1111" => -- stu direct
2568
                                     next_state   <= dual_op_write16_state;
2569
 
2570
                                        when others =>
2571
                                     next_state   <= dual_op_read8_state;
2572
               end case;
2573
 
2574
                  when "1110" => -- accb indexed
2575
                                        -- increment the pc
2576
               pc_ctrl    <= incr_pc;
2577
                                        case op_code(3 downto 0) is
2578
               when "0011" | -- addd
2579
                                             "1100" | -- ldd
2580
                                             "1110" => -- ldu
2581
                                     st_ctrl      <= push_st;
2582
                                     return_state <= dual_op_read16_state;
2583
                                     next_state   <= indexed_state;
2584
 
2585
                                        when "0111" =>  -- stab indexed
2586
                                     st_ctrl      <= push_st;
2587
                                     return_state <= dual_op_write8_state;
2588
                                     next_state   <= indexed_state;
2589
 
2590
                                        when "1101" =>  -- std indexed
2591
                                     st_ctrl      <= push_st;
2592
                                     return_state <= dual_op_write16_state;
2593
                                     next_state   <= indexed_state;
2594
 
2595
                                        when "1111" => -- stu indexed
2596
                                     st_ctrl      <= push_st;
2597
                                     return_state <= dual_op_write16_state;
2598
                                     next_state   <= indexed_state;
2599
 
2600
                                        when others =>
2601
                                     st_ctrl      <= push_st;
2602
                                     return_state <= dual_op_read8_state;
2603
                                     next_state   <= indexed_state;
2604
               end case;
2605
 
2606
             when "1111" => -- accb extended
2607
                                        -- increment the pc
2608
               pc_ctrl    <= incr_pc;
2609
                                        case op_code(3 downto 0) is
2610
               when "0011" | -- addd
2611
                                             "1100" | -- ldd
2612
                                             "1110" => -- ldu
2613
                                     st_ctrl      <= push_st;
2614
                                     return_state <= dual_op_read16_state;
2615
                                     next_state   <= extended_state;
2616
 
2617
                                        when "0111" =>  -- stab extended
2618
                                     st_ctrl      <= push_st;
2619
                                     return_state <= dual_op_write8_state;
2620
                                     next_state   <= extended_state;
2621
 
2622
                                        when "1101" =>  -- std extended
2623
                                     st_ctrl      <= push_st;
2624
                                     return_state <= dual_op_write16_state;
2625
                                     next_state   <= extended_state;
2626
 
2627
                                        when "1111" => -- stu  extended
2628
                                     st_ctrl      <= push_st;
2629
                                     return_state <= dual_op_write16_state;
2630
                                     next_state   <= extended_state;
2631
 
2632
                                        when others =>
2633
                                     st_ctrl      <= push_st;
2634
                                     return_state <= dual_op_read8_state;
2635
                                     next_state   <= extended_state;
2636
               end case;
2637
 
2638
                  when others =>
2639
                                   null;
2640
             end case;
2641
 
2642
                         --
2643
                         -- Here to decode prefix 2 instruction
2644
                         -- and fetch next byte of intruction
2645
                         -- whether it be necessary or not
2646
                         --
2647
          when decode2_state =>
2648
                                 -- fetch first byte of address or immediate data
2649
             ea_ctrl    <= fetch_first_ea;
2650
                                 md_ctrl    <= fetch_first_md;
2651
             addr_ctrl  <= fetch_ad;
2652
                            case op_code(7 downto 4) is
2653
                                 --
2654
                                 -- lbcc -- long branch conditional
2655
                                 -- 6809 => branch 6 cycles, no branch 5 cycles
2656
                                 -- cpu09 => always 5 cycles
2657
                                 -- 1 pre=(pc) / pc=pc+1
2658
                                 -- 2 op=(pc) / pc=pc+1
2659
                                 -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
2660
             -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
2661
                                 -- 5 if cond pc=pc+md else pc=pc
2662
                                 --
2663
                  when "0010" =>
2664
                                        -- increment the pc
2665
               pc_ctrl    <= incr_pc;
2666
                                        next_state <= lbranch_state;
2667
 
2668
                                 --
2669
                                 -- Single byte stack operators
2670
                                 -- Do not advance PC
2671
                                 --
2672
                  when "0011" =>
2673
                    case op_code(3 downto 0) is
2674
                         when "1111" => -- swi 2
2675
                                           -- predecrement sp
2676
                            left_ctrl  <= sp_left;
2677
                            right_ctrl <= one_right;
2678
                                                alu_ctrl   <= alu_sub16;
2679
                                                sp_ctrl    <= load_sp;
2680
                  iv_ctrl    <= swi2_iv;
2681
                                                next_state <= int_entire_state;
2682
 
2683
                         when others =>
2684
                                                next_state   <= fetch_state;
2685
                         end case;
2686
 
2687
                  when "1000" => -- acca immediate
2688
                                   -- increment the pc
2689
               pc_ctrl    <= incr_pc;
2690
                                        case op_code(3 downto 0) is
2691
               when "0011" | -- cmpd #
2692
                                             "1100" | -- cmpy #
2693
                                             "1110" => -- ldy #
2694
                                     st_ctrl      <= push_st;
2695
                                     return_state <= fetch_state;
2696
                                          next_state   <= imm16_state;
2697
 
2698
                                        when others =>
2699
                                     next_state   <= fetch_state;
2700
 
2701
               end case;
2702
 
2703
                  when "1001" => -- acca direct
2704
                                        -- increment the pc
2705
               pc_ctrl    <= incr_pc;
2706
                                        case op_code(3 downto 0) is
2707
               when "0011" | -- cmpd <
2708
                                             "1100" | -- cmpy <
2709
                                             "1110" => -- ldy <
2710
                                          next_state   <= dual_op_read16_state;
2711
 
2712
                                        when "1111" => -- sty <
2713
                                     next_state   <= dual_op_write16_state;
2714
 
2715
                                        when others =>
2716
                                     next_state   <= fetch_state;
2717
 
2718
               end case;
2719
 
2720
                  when "1010" => -- acca indexed
2721
                                        -- increment the pc
2722
               pc_ctrl    <= incr_pc;
2723
                                        case op_code(3 downto 0) is
2724
               when "0011" | -- cmpd ,ind
2725
                                             "1100" | -- cmpy ,ind
2726
                                             "1110" => -- ldy ,ind
2727
                                     st_ctrl      <= push_st;
2728
                                     return_state <= dual_op_read16_state;
2729
                                          next_state   <= indexed_state;
2730
 
2731
                                        when "1111" => -- sty ,ind
2732
                                     st_ctrl      <= push_st;
2733
                                     return_state <= dual_op_write16_state;
2734
                                     next_state   <= indexed_state;
2735
 
2736
                                        when others =>
2737
                                     next_state   <= fetch_state;
2738
               end case;
2739
 
2740
             when "1011" => -- acca extended
2741
                                        -- increment the pc
2742
               pc_ctrl    <= incr_pc;
2743
                                        case op_code(3 downto 0) is
2744
               when "0011" | -- cmpd <
2745
                                             "1100" | -- cmpy <
2746
                                             "1110" => -- ldy <
2747
                                     st_ctrl      <= push_st;
2748
                                     return_state <= dual_op_read16_state;
2749
                                          next_state   <= extended_state;
2750
 
2751
                                        when "1111" => -- sty >
2752
                                     st_ctrl      <= push_st;
2753
                                     return_state <= dual_op_write16_state;
2754
                                     next_state   <= extended_state;
2755
 
2756
                                        when others =>
2757
                                     next_state   <= fetch_state;
2758
 
2759
               end case;
2760
 
2761
                  when "1100" => -- accb immediate
2762
                                        -- increment the pc
2763
               pc_ctrl    <= incr_pc;
2764
                                        case op_code(3 downto 0) is
2765
               when "0011" | -- undef #
2766
                                             "1100" | -- undef #
2767
                                             "1110" => -- lds #
2768
                                     st_ctrl      <= push_st;
2769
                                     return_state <= fetch_state;
2770
                                          next_state   <= imm16_state;
2771
 
2772
                                        when others =>
2773
                                     next_state   <= fetch_state;
2774
 
2775
               end case;
2776
 
2777
                  when "1101" => -- accb direct
2778
                                        -- increment the pc
2779
               pc_ctrl    <= incr_pc;
2780
                                        case op_code(3 downto 0) is
2781
               when "0011" | -- undef <
2782
                                             "1100" | -- undef <
2783
                                             "1110" => -- lds <
2784
                                          next_state   <= dual_op_read16_state;
2785
 
2786
                                        when "1111" => -- sts <
2787
                                     next_state   <= dual_op_write16_state;
2788
 
2789
                                        when others =>
2790
                                     next_state   <= fetch_state;
2791
 
2792
               end case;
2793
 
2794
                  when "1110" => -- accb indexed
2795
                                        -- increment the pc
2796
               pc_ctrl    <= incr_pc;
2797
                                        case op_code(3 downto 0) is
2798
               when "0011" | -- undef ,ind
2799
                                             "1100" | -- undef ,ind
2800
                                             "1110" => -- lds ,ind
2801
                                     st_ctrl      <= push_st;
2802
                                     return_state <= dual_op_read16_state;
2803
                                          next_state   <= indexed_state;
2804
 
2805
                                        when "1111" => -- sts ,ind
2806
                                     st_ctrl      <= push_st;
2807
                                     return_state <= dual_op_write16_state;
2808
                                     next_state   <= indexed_state;
2809
 
2810
                                        when others =>
2811
                                     next_state   <= fetch_state;
2812
 
2813
               end case;
2814
 
2815
             when "1111" => -- accb extended
2816
                                        -- increment the pc
2817
               pc_ctrl    <= incr_pc;
2818
                                        case op_code(3 downto 0) is
2819
               when "0011" | -- undef >
2820
                                             "1100" | -- undef >
2821
                                             "1110" => -- lds >
2822
                                     st_ctrl      <= push_st;
2823
                                     return_state <= dual_op_read16_state;
2824
                                          next_state   <= extended_state;
2825
 
2826
                                        when "1111" => -- sts >
2827
                                     st_ctrl      <= push_st;
2828
                                     return_state <= dual_op_write16_state;
2829
                                     next_state   <= extended_state;
2830
 
2831
                                        when others =>
2832
                                     next_state   <= fetch_state;
2833
               end case;
2834
 
2835
                  when others =>
2836
                         next_state   <= fetch_state;
2837
             end case;
2838
                         --
2839
                         -- Here to decode instruction
2840
                         -- and fetch next byte of intruction
2841
                         -- whether it be necessary or not
2842
                         --
2843
          when decode3_state =>
2844
             ea_ctrl    <= fetch_first_ea;
2845
                                 md_ctrl    <= fetch_first_md;
2846
             addr_ctrl  <= fetch_ad;
2847
             dout_ctrl  <= md_lo_dout;
2848
                            case op_code(7 downto 4) is
2849
                                 --
2850
                                 -- Single byte stack operators
2851
                                 -- Do not advance PC
2852
                                 --
2853
                  when "0011" =>
2854
                    case op_code(3 downto 0) is
2855
                         when "1111" => -- swi3
2856
                                           -- predecrement sp
2857
                            left_ctrl  <= sp_left;
2858
                            right_ctrl <= one_right;
2859
                                                alu_ctrl   <= alu_sub16;
2860
                                                sp_ctrl    <= load_sp;
2861
                  iv_ctrl    <= swi3_iv;
2862
                                                next_state <= int_entire_state;
2863
                         when others =>
2864
                                                next_state   <= fetch_state;
2865
                         end case;
2866
 
2867
                  when "1000" => -- acca immediate
2868
                                   -- increment the pc
2869
               pc_ctrl    <= incr_pc;
2870
                                        case op_code(3 downto 0) is
2871
               when "0011" | -- cmpu #
2872
                                             "1100" | -- cmps #
2873
                                             "1110" => -- undef #
2874
                                     st_ctrl      <= push_st;
2875
                                     return_state <= fetch_state;
2876
                                          next_state   <= imm16_state;
2877
                                        when others =>
2878
                                     next_state   <= fetch_state;
2879
               end case;
2880
 
2881
                  when "1001" => -- acca direct
2882
                                        -- increment the pc
2883
               pc_ctrl    <= incr_pc;
2884
                                        case op_code(3 downto 0) is
2885
               when "0011" | -- cmpu <
2886
                                             "1100" | -- cmps <
2887
                                             "1110" => -- undef <
2888
                                     st_ctrl      <= idle_st;
2889
                                     return_state <= fetch_state;
2890
                                          next_state   <= dual_op_read16_state;
2891
 
2892
                                        when others =>
2893
                                     next_state   <= fetch_state;
2894
 
2895
               end case;
2896
 
2897
                  when "1010" => -- acca indexed
2898
                                        -- increment the pc
2899
               pc_ctrl    <= incr_pc;
2900
                                        case op_code(3 downto 0) is
2901
               when "0011" | -- cmpu ,X
2902
                                             "1100" | -- cmps ,X
2903
                                             "1110" => -- undef ,X
2904
                                     st_ctrl      <= push_st;
2905
                                     return_state <= dual_op_read16_state;
2906
                                          next_state   <= indexed_state;
2907
 
2908
                                        when others =>
2909
                                     next_state   <= fetch_state;
2910
 
2911
               end case;
2912
 
2913
             when "1011" => -- acca extended
2914
                                        -- increment the pc
2915
               pc_ctrl    <= incr_pc;
2916
                                        case op_code(3 downto 0) is
2917
               when "0011" | -- cmpu >
2918
                                             "1100" | -- cmps >
2919
                                             "1110" => -- undef >
2920
                                     st_ctrl      <= push_st;
2921
                                     return_state <= dual_op_read16_state;
2922
                                          next_state   <= extended_state;
2923
                                        when others =>
2924
                                     next_state   <= fetch_state;
2925
               end case;
2926
 
2927
                  when others =>
2928
                         next_state   <= fetch_state;
2929
             end case;
2930
 
2931
           --
2932
                          -- here if ea holds low byte
2933
                          -- Direct
2934
                          -- Extended
2935
                          -- Indexed
2936
                          -- read memory location
2937
                          --
2938
                          when single_op_read_state =>
2939
                                        -- read memory into md
2940
                                   md_ctrl    <= fetch_first_md;
2941
               addr_ctrl  <= read_ad;
2942
                                        dout_ctrl  <= md_lo_dout;
2943
                                        next_state <= single_op_exec_state;
2944
 
2945
                when single_op_exec_state =>
2946
                    case op_code(3 downto 0) is
2947
                         when "0000" => -- neg
2948
                   left_ctrl  <= md_left;
2949
                                            right_ctrl <= zero_right;
2950
                                            alu_ctrl   <= alu_neg;
2951
                                            cc_ctrl    <= load_cc;
2952
                                       md_ctrl    <= load_md;
2953
                                       next_state <= single_op_write_state;
2954
                    when "0011" => -- com
2955
                   left_ctrl  <= md_left;
2956
                             right_ctrl <= zero_right;
2957
                                            alu_ctrl   <= alu_com;
2958
                                            cc_ctrl    <= load_cc;
2959
                                       md_ctrl    <= load_md;
2960
                                       next_state <= single_op_write_state;
2961
                         when "0100" => -- lsr
2962
                   left_ctrl  <= md_left;
2963
                                                 right_ctrl <= zero_right;
2964
                                            alu_ctrl   <= alu_lsr8;
2965
                                            cc_ctrl    <= load_cc;
2966
                                       md_ctrl    <= load_md;
2967
                                       next_state <= single_op_write_state;
2968
                         when "0110" => -- ror
2969
                   left_ctrl  <= md_left;
2970
                                                 right_ctrl <= zero_right;
2971
                                            alu_ctrl   <= alu_ror8;
2972
                                            cc_ctrl    <= load_cc;
2973
                                       md_ctrl    <= load_md;
2974
                                       next_state <= single_op_write_state;
2975
                         when "0111" => -- asr
2976
                   left_ctrl  <= md_left;
2977
                                                 right_ctrl <= zero_right;
2978
                                            alu_ctrl   <= alu_asr8;
2979
                                            cc_ctrl    <= load_cc;
2980
                                       md_ctrl    <= load_md;
2981
                                       next_state <= single_op_write_state;
2982
                         when "1000" => -- asl
2983
                   left_ctrl  <= md_left;
2984
                                                 right_ctrl <= zero_right;
2985
                                            alu_ctrl   <= alu_asl8;
2986
                                            cc_ctrl    <= load_cc;
2987
                                       md_ctrl    <= load_md;
2988
                                       next_state <= single_op_write_state;
2989
                         when "1001" => -- rol
2990
                   left_ctrl  <= md_left;
2991
                                                 right_ctrl <= zero_right;
2992
                                            alu_ctrl   <= alu_rol8;
2993
                                            cc_ctrl    <= load_cc;
2994
                                       md_ctrl    <= load_md;
2995
                                       next_state <= single_op_write_state;
2996
                         when "1010" => -- dec
2997
                   left_ctrl  <= md_left;
2998
                             right_ctrl <= one_right;
2999
                                            alu_ctrl   <= alu_dec;
3000
                                            cc_ctrl    <= load_cc;
3001
                                       md_ctrl    <= load_md;
3002
                                       next_state <= single_op_write_state;
3003
                         when "1011" => -- undefined
3004
                                       next_state <= fetch_state;
3005
                         when "1100" => -- inc
3006
                   left_ctrl  <= md_left;
3007
                             right_ctrl <= one_right;
3008
                                            alu_ctrl   <= alu_inc;
3009
                                            cc_ctrl    <= load_cc;
3010
                                       md_ctrl    <= load_md;
3011
                                       next_state <= single_op_write_state;
3012
                         when "1101" => -- tst
3013
                   left_ctrl  <= md_left;
3014
                             right_ctrl <= zero_right;
3015
                                            alu_ctrl   <= alu_st8;
3016
                                            cc_ctrl    <= load_cc;
3017
                                       next_state <= fetch_state;
3018
                         when "1110" => -- jmp
3019
                   left_ctrl  <= md_left;
3020
                                                 right_ctrl <= zero_right;
3021
                                            alu_ctrl   <= alu_ld16;
3022
                   pc_ctrl    <= load_pc;
3023
                                       next_state <= fetch_state;
3024
                         when "1111" => -- clr
3025
                   left_ctrl  <= md_left;
3026
                                                 right_ctrl <= zero_right;
3027
                                            alu_ctrl   <= alu_clr;
3028
                                            cc_ctrl    <= load_cc;
3029
                                       md_ctrl    <= load_md;
3030
                                       next_state <= single_op_write_state;
3031
                         when others =>
3032
                                       next_state <= fetch_state;
3033
                         end case;
3034
           --
3035
                          -- single operand 8 bit write
3036
                          -- Write low 8 bits of ALU output
3037
                          -- EA holds address
3038
                          -- MD holds data
3039
                          --
3040
                          when single_op_write_state =>
3041
                                 -- write ALU low byte output
3042
             addr_ctrl  <= write_ad;
3043
             dout_ctrl  <= md_lo_dout;
3044
                                 next_state <= fetch_state;
3045
 
3046
           --
3047
                          -- here if ea holds address of low byte
3048
                          -- read memory location
3049
                          --
3050
                          when dual_op_read8_state =>
3051
                                   -- read first data byte from ea
3052
                                   md_ctrl    <= fetch_first_md;
3053
               addr_ctrl  <= read_ad;
3054
                                        next_state <= fetch_state;
3055
 
3056
                                --
3057
                                -- Here to read a 16 bit value into MD
3058
                                -- pointed to by the EA register
3059
                                -- The first byte is read
3060
                                -- and the EA is incremented
3061
                                --
3062
                           when dual_op_read16_state =>
3063
                                        -- increment the effective address
3064
               left_ctrl  <= ea_left;
3065
               right_ctrl <= one_right;
3066
               alu_ctrl   <= alu_add16;
3067
               ea_ctrl    <= load_ea;
3068
                                        -- read the high byte of the 16 bit data
3069
                                   md_ctrl    <= fetch_first_md;
3070
               addr_ctrl  <= read_ad;
3071
                                        next_state <= dual_op_read16_2_state;
3072
 
3073
                                --
3074
                                -- here to read the second byte
3075
                           -- pointed to by EA into MD
3076
                                --
3077
                           when dual_op_read16_2_state =>
3078
                                        -- read the low byte of the 16 bit data
3079
                                   md_ctrl    <= fetch_next_md;
3080
               addr_ctrl  <= read_ad;
3081
                                        next_state <= fetch_state;
3082
 
3083
           --
3084
                          -- 16 bit Write state
3085
                          -- EA hold address of memory to write to
3086
                          -- Advance the effective address in ALU
3087
                          -- decode op_code to determine which
3088
                          -- register to write
3089
                          --
3090
                          when dual_op_write16_state =>
3091
                                 -- increment the effective address
3092
                                 left_ctrl  <= ea_left;
3093
                                 right_ctrl <= one_right;
3094
                                 alu_ctrl   <= alu_add16;
3095
                            ea_ctrl    <= load_ea;
3096
                                 -- write the ALU hi byte at ea
3097
             addr_ctrl  <= write_ad;
3098
                                 if op_code(6) = '0' then
3099
                                   case op_code(3 downto 0) is
3100
                              when "1111" => -- stx / sty
3101
                                          case pre_code is
3102
                                          when "00010000" => -- page 2 -- sty
3103
                        dout_ctrl  <= iy_hi_dout;
3104
                                     when others =>     -- page 1 -- stx
3105
                   dout_ctrl  <= ix_hi_dout;
3106
                                          end case;
3107
                                   when others =>
3108
                 dout_ctrl  <= md_hi_dout;
3109
                                   end case;
3110
             else
3111
                                   case op_code(3 downto 0) is
3112
                              when "1101" => -- std
3113
                 dout_ctrl  <= acca_dout; -- acca is high byte of ACCD
3114
                              when "1111" => -- stu / sts
3115
                                          case pre_code is
3116
                                          when "00010000" => -- page 2 -- sts
3117
                        dout_ctrl  <= sp_hi_dout;
3118
                                          when others =>     -- page 1 -- stu
3119
                        dout_ctrl  <= up_hi_dout;
3120
                                          end case;
3121
                                   when others =>
3122
                 dout_ctrl  <= md_hi_dout;
3123
                                   end case;
3124
             end if;
3125
                                 next_state   <= dual_op_write8_state;
3126
 
3127
           --
3128
                          -- Dual operand 8 bit write
3129
           -- Write 8 bit accumulator
3130
                          -- or low byte of 16 bit register
3131
                          -- EA holds address
3132
                          -- decode opcode to determine
3133
                          -- which register to apply to the bus
3134
                          -- Also set the condition codes here
3135
                          --
3136
                          when dual_op_write8_state =>
3137
                            if op_code(6) = '0' then
3138
                                   case op_code(3 downto 0) is
3139
                                        when "0111" => -- sta
3140
                 dout_ctrl  <= acca_dout;
3141
                                        when "1111" => -- stx / sty
3142
                                          case pre_code is
3143
                                          when "00010000" => -- page 2 -- sty
3144
                        dout_ctrl  <= iy_lo_dout;
3145
                                     when others =>     -- page 1 -- stx
3146
                   dout_ctrl  <= ix_lo_dout;
3147
                                          end case;
3148
                                        when others =>
3149
                 dout_ctrl  <= md_lo_dout;
3150
                                        end case;
3151
             else
3152
                                   case op_code(3 downto 0) is
3153
                                        when "0111" => -- stb
3154
                 dout_ctrl  <= accb_dout;
3155
                                        when "1101" => -- std
3156
                 dout_ctrl  <= accb_dout; -- accb is low byte of accd
3157
                                        when "1111" => -- stu / sts
3158
                                          case pre_code is
3159
                                          when "00010000" => -- page 2 -- sts
3160
                        dout_ctrl  <= sp_lo_dout;
3161
                                          when others =>     -- page 1 -- stu
3162
                        dout_ctrl  <= up_lo_dout;
3163
                                          end case;
3164
                                        when others =>
3165
                 dout_ctrl  <= md_lo_dout;
3166
                                        end case;
3167
             end if;
3168
                                 -- write ALU low byte output
3169
             addr_ctrl    <= write_ad;
3170
                                 next_state   <= fetch_state;
3171
 
3172
                          --
3173
                          -- 16 bit immediate addressing mode
3174
                          --
3175
                          when imm16_state =>
3176
                                   -- increment pc
3177
               pc_ctrl    <= incr_pc;
3178
                                   -- fetch next immediate byte
3179
                              md_ctrl    <= fetch_next_md;
3180
               addr_ctrl  <= fetch_ad;
3181
                                        st_ctrl    <= pull_st;
3182
                                        next_state <= saved_state;
3183
 
3184
           --
3185
                          -- md & ea holds 8 bit index offset
3186
                          -- calculate the effective memory address
3187
                          -- using the alu
3188
                          --
3189
           when indexed_state =>
3190
                                 --
3191
                                 -- decode indexing mode
3192
                                 --
3193
                                 if md(7) = '0' then
3194
                                   case md(6 downto 5) is
3195
                                        when "00" =>
3196
                                left_ctrl  <= ix_left;
3197
                                        when "01" =>
3198
                                left_ctrl  <= iy_left;
3199
                                        when "10" =>
3200
                                left_ctrl  <= up_left;
3201
                                        when others =>
3202
                                        -- when "11" =>
3203
                                left_ctrl  <= sp_left;
3204
                                        end case;
3205
                                   right_ctrl   <= md_sign5_right;
3206
                                   alu_ctrl     <= alu_add16;
3207
               ea_ctrl      <= load_ea;
3208
                                        st_ctrl      <= pull_st;
3209
                                        next_state   <= saved_state;
3210
 
3211
                                 else
3212
                                   case md(3 downto 0) is
3213
                                        when "0000" =>     -- ,R+
3214
                                     case md(6 downto 5) is
3215
                                          when "00" =>
3216
                                  left_ctrl  <= ix_left;
3217
                                          when "01" =>
3218
                                  left_ctrl  <= iy_left;
3219
                                          when "10" =>
3220
                                  left_ctrl  <= up_left;
3221
                                          when others =>
3222
                                  left_ctrl  <= sp_left;
3223
                                          end case;
3224
                                          --
3225
                                     right_ctrl <= zero_right;
3226
                                     alu_ctrl   <= alu_add16;
3227
                 ea_ctrl    <= load_ea;
3228
                 next_state <= postincr1_state;
3229
 
3230
                                        when "0001" =>     -- ,R++
3231
                                     case md(6 downto 5) is
3232
                                          when "00" =>
3233
                                  left_ctrl  <= ix_left;
3234
                                          when "01" =>
3235
                                  left_ctrl  <= iy_left;
3236
                                          when "10" =>
3237
                                  left_ctrl  <= up_left;
3238
                                          when others =>
3239
                                          -- when "11" =>
3240
                                  left_ctrl  <= sp_left;
3241
                                          end case;
3242
                                     right_ctrl <= zero_right;
3243
                                     alu_ctrl   <= alu_add16;
3244
                 ea_ctrl    <= load_ea;
3245
                 next_state <= postincr2_state;
3246
 
3247
                                        when "0010" =>     -- ,-R
3248
                                     case md(6 downto 5) is
3249
                                          when "00" =>
3250
                                  left_ctrl  <= ix_left;
3251
                   ix_ctrl    <= load_ix;
3252
                                          when "01" =>
3253
                                  left_ctrl  <= iy_left;
3254
                   iy_ctrl    <= load_iy;
3255
                                          when "10" =>
3256
                                  left_ctrl  <= up_left;
3257
                   up_ctrl    <= load_up;
3258
                                          when others =>
3259
                                          -- when "11" =>
3260
                                  left_ctrl  <= sp_left;
3261
                   sp_ctrl    <= load_sp;
3262
                                          end case;
3263
                                     right_ctrl   <= one_right;
3264
                                     alu_ctrl     <= alu_sub16;
3265
                 ea_ctrl      <= load_ea;
3266
                                          st_ctrl      <= pull_st;
3267
                                          next_state   <= saved_state;
3268
 
3269
                                        when "0011" =>     -- ,--R
3270
                                     case md(6 downto 5) is
3271
                                          when "00" =>
3272
                                  left_ctrl  <= ix_left;
3273
                   ix_ctrl    <= load_ix;
3274
                                          when "01" =>
3275
                                  left_ctrl  <= iy_left;
3276
                   iy_ctrl    <= load_iy;
3277
                                          when "10" =>
3278
                                  left_ctrl  <= up_left;
3279
                   up_ctrl    <= load_up;
3280
                                          when others =>
3281
                                          -- when "11" =>
3282
                                  left_ctrl  <= sp_left;
3283
                   sp_ctrl    <= load_sp;
3284
                                          end case;
3285
                                     right_ctrl <= two_right;
3286
                                     alu_ctrl   <= alu_sub16;
3287
                 ea_ctrl    <= load_ea;
3288
                                          if md(4) = '0' then
3289
                                            st_ctrl      <= pull_st;
3290
                                            next_state   <= saved_state;
3291
                                          else
3292
                                            next_state   <= indirect_state;
3293
                                          end if;
3294
 
3295
                                        when "0100" =>     -- ,R (zero offset)
3296
                                     case md(6 downto 5) is
3297
                                          when "00" =>
3298
                                  left_ctrl  <= ix_left;
3299
                                          when "01" =>
3300
                                  left_ctrl  <= iy_left;
3301
                                          when "10" =>
3302
                                  left_ctrl  <= up_left;
3303
                                          when others =>
3304
                                          -- when "11" =>
3305
                                  left_ctrl  <= sp_left;
3306
                                          end case;
3307
                                     right_ctrl <= zero_right;
3308
                                     alu_ctrl   <= alu_add16;
3309
                 ea_ctrl    <= load_ea;
3310
                                          if md(4) = '0' then
3311
                                            st_ctrl      <= pull_st;
3312
                                            next_state   <= saved_state;
3313
                                          else
3314
                                            next_state   <= indirect_state;
3315
                                          end if;
3316
 
3317
                                        when "0101" =>     -- ACCB,R
3318
                                     case md(6 downto 5) is
3319
                                          when "00" =>
3320
                                  left_ctrl  <= ix_left;
3321
                                          when "01" =>
3322
                                  left_ctrl  <= iy_left;
3323
                                          when "10" =>
3324
                                  left_ctrl  <= up_left;
3325
                                          when others =>
3326
                                          -- when "11" =>
3327
                                  left_ctrl  <= sp_left;
3328
                                          end case;
3329
                                     right_ctrl <= accb_right;
3330
                                     alu_ctrl   <= alu_add16;
3331
                 ea_ctrl    <= load_ea;
3332
                                          if md(4) = '0' then
3333
                                            st_ctrl      <= pull_st;
3334
                                            next_state   <= saved_state;
3335
                                          else
3336
                                            next_state   <= indirect_state;
3337
                                          end if;
3338
 
3339
                                        when "0110" =>     -- ACCA,R
3340
                                     case md(6 downto 5) is
3341
                                          when "00" =>
3342
                                  left_ctrl  <= ix_left;
3343
                                          when "01" =>
3344
                                  left_ctrl  <= iy_left;
3345
                                          when "10" =>
3346
                                  left_ctrl  <= up_left;
3347
                                          when others =>
3348
                                          -- when "11" =>
3349
                                  left_ctrl  <= sp_left;
3350
                                          end case;
3351
                                     right_ctrl <= acca_right;
3352
                                     alu_ctrl   <= alu_add16;
3353
                 ea_ctrl    <= load_ea;
3354
                                          if md(4) = '0' then
3355
                                            st_ctrl      <= pull_st;
3356
                                            next_state   <= saved_state;
3357
                                          else
3358
                                            next_state   <= indirect_state;
3359
                                          end if;
3360
 
3361
                                        when "0111" =>     -- undefined
3362
                                     case md(6 downto 5) is
3363
                                          when "00" =>
3364
                                  left_ctrl  <= ix_left;
3365
                                          when "01" =>
3366
                                  left_ctrl  <= iy_left;
3367
                                          when "10" =>
3368
                                  left_ctrl  <= up_left;
3369
                                          when others =>
3370
                                          -- when "11" =>
3371
                                  left_ctrl  <= sp_left;
3372
                                          end case;
3373
                                     right_ctrl <= zero_right;
3374
                                     alu_ctrl   <= alu_add16;
3375
                 ea_ctrl    <= load_ea;
3376
                                          if md(4) = '0' then
3377
                                            st_ctrl      <= pull_st;
3378
                                            next_state   <= saved_state;
3379
                                          else
3380
                                            next_state   <= indirect_state;
3381
                                          end if;
3382
 
3383
                                        when "1000" =>     -- offset8,R
3384
                 md_ctrl    <= fetch_first_md; -- pick up 8 bit offset
3385
                 addr_ctrl  <= fetch_ad;
3386
                 pc_ctrl    <= incr_pc;
3387
                 next_state <= index8_state;
3388
 
3389
                                        when "1001" =>     -- offset16,R
3390
                 md_ctrl    <= fetch_first_md; -- pick up first byte of 16 bit offset
3391
                 addr_ctrl  <= fetch_ad;
3392
                 pc_ctrl    <= incr_pc;
3393
                 next_state <= index16_state;
3394
 
3395
                                        when "1010" =>     -- undefined
3396
                                     case md(6 downto 5) is
3397
                                          when "00" =>
3398
                                  left_ctrl  <= ix_left;
3399
                                          when "01" =>
3400
                                  left_ctrl  <= iy_left;
3401
                                          when "10" =>
3402
                                  left_ctrl  <= up_left;
3403
                                          when others =>
3404
                                          -- when "11" =>
3405
                                  left_ctrl  <= sp_left;
3406
                                          end case;
3407
                                     right_ctrl <= zero_right;
3408
                                     alu_ctrl   <= alu_add16;
3409
                 ea_ctrl    <= load_ea;
3410
                                          --
3411
                                          if md(4) = '0' then
3412
                                            st_ctrl      <= pull_st;
3413
                                            next_state   <= saved_state;
3414
                                          else
3415
                                            next_state   <= indirect_state;
3416
                                          end if;
3417
 
3418
                                        when "1011" =>     -- ACCD,R
3419
                                     case md(6 downto 5) is
3420
                                          when "00" =>
3421
                                  left_ctrl  <= ix_left;
3422
                                          when "01" =>
3423
                                  left_ctrl  <= iy_left;
3424
                                          when "10" =>
3425
                                  left_ctrl  <= up_left;
3426
                                          when others =>
3427
                                          -- when "11" =>
3428
                                  left_ctrl  <= sp_left;
3429
                                          end case;
3430
                                     right_ctrl <= accd_right;
3431
                                     alu_ctrl   <= alu_add16;
3432
                 ea_ctrl    <= load_ea;
3433
                                          if md(4) = '0' then
3434
                                            st_ctrl      <= pull_st;
3435
                                            next_state   <= saved_state;
3436
                                          else
3437
                                            next_state   <= indirect_state;
3438
                                          end if;
3439
 
3440
                                        when "1100" =>     -- offset8,PC
3441
                                          -- fetch 8 bit offset
3442
                 md_ctrl    <= fetch_first_md;
3443
                 addr_ctrl  <= fetch_ad;
3444
                 pc_ctrl    <= incr_pc;
3445
                 next_state <= pcrel8_state;
3446
 
3447
                                        when "1101" =>     -- offset16,PC
3448
                                          -- fetch offset
3449
                 md_ctrl    <= fetch_first_md;
3450
                 addr_ctrl  <= fetch_ad;
3451
                 pc_ctrl    <= incr_pc;
3452
                 next_state <= pcrel16_state;
3453
 
3454
                                        when "1110" =>     -- undefined
3455
                                     case md(6 downto 5) is
3456
                                          when "00" =>
3457
                                  left_ctrl  <= ix_left;
3458
                                          when "01" =>
3459
                                  left_ctrl  <= iy_left;
3460
                                          when "10" =>
3461
                                  left_ctrl  <= up_left;
3462
                                          when others =>
3463
                                          -- when "11" =>
3464
                                  left_ctrl  <= sp_left;
3465
                                          end case;
3466
                                     right_ctrl <= zero_right;
3467
                                     alu_ctrl   <= alu_add16;
3468
                 ea_ctrl    <= load_ea;
3469
                                          if md(4) = '0' then
3470
                                            st_ctrl      <= pull_st;
3471
                                            next_state   <= saved_state;
3472
                                          else
3473
                                            next_state   <= indirect_state;
3474
                                          end if;
3475
 
3476
               when others =>
3477
--                      when "1111" =>     -- [,address]
3478
                                          -- advance PC to pick up address
3479
                 md_ctrl    <= fetch_first_md;
3480
                 addr_ctrl  <= fetch_ad;
3481
                                          pc_ctrl    <= incr_pc;
3482
                 next_state <= indexaddr_state;
3483
                                        end case;
3484
                                 end if;
3485
 
3486
                          -- load index register with ea plus one
3487
                          when postincr1_state =>
3488
                            left_ctrl  <= ea_left;
3489
                            right_ctrl <= one_right;
3490
                            alu_ctrl   <= alu_add16;
3491
                                 case md(6 downto 5) is
3492
                            when "00" =>
3493
               ix_ctrl    <= load_ix;
3494
                                 when "01" =>
3495
               iy_ctrl    <= load_iy;
3496
                                 when "10" =>
3497
               up_ctrl    <= load_up;
3498
                                 when others =>
3499
                                 -- when "11" =>
3500
               sp_ctrl    <= load_sp;
3501
                            end case;
3502
                                 -- return to previous state
3503
                            if md(4) = '0' then
3504
                                         st_ctrl      <= pull_st;
3505
                                         next_state   <= saved_state;
3506
                                 else
3507
                                         next_state   <= indirect_state;
3508
                                 end if;
3509
 
3510
                          -- load index register with ea plus two
3511
                          when postincr2_state =>
3512
                                 -- increment register by two (address)
3513
                            left_ctrl  <= ea_left;
3514
                            right_ctrl <= two_right;
3515
                            alu_ctrl   <= alu_add16;
3516
                                 case md(6 downto 5) is
3517
                            when "00" =>
3518
               ix_ctrl    <= load_ix;
3519
                                 when "01" =>
3520
               iy_ctrl    <= load_iy;
3521
                                 when "10" =>
3522
               up_ctrl    <= load_up;
3523
                                 when others =>
3524
                                 -- when "11" =>
3525
               sp_ctrl    <= load_sp;
3526
                            end case;
3527
                                 -- return to previous state
3528
                            if md(4) = '0' then
3529
                                         st_ctrl      <= pull_st;
3530
                                         next_state   <= saved_state;
3531
                                 else
3532
                                         next_state   <= indirect_state;
3533
                                 end if;
3534
           --
3535
                          -- ea = index register + md (8 bit signed offset)
3536
                          -- ea holds post byte
3537
                          --
3538
                          when index8_state =>
3539
                                 case ea(6 downto 5) is
3540
                            when "00" =>
3541
                              left_ctrl  <= ix_left;
3542
                            when "01" =>
3543
                              left_ctrl  <= iy_left;
3544
                                 when "10" =>
3545
                              left_ctrl  <= up_left;
3546
                                 when others =>
3547
                                 -- when "11" =>
3548
                              left_ctrl  <= sp_left;
3549
                                 end case;
3550
                                 -- ea = index reg + md
3551
                            right_ctrl <= md_sign8_right;
3552
                            alu_ctrl   <= alu_add16;
3553
             ea_ctrl    <= load_ea;
3554
                                 -- return to previous state
3555
                            if ea(4) = '0' then
3556
                                         st_ctrl      <= pull_st;
3557
                                         next_state   <= saved_state;
3558
                                 else
3559
                                         next_state   <= indirect_state;
3560
                                 end if;
3561
 
3562
                          -- fetch low byte of 16 bit indexed offset
3563
                          when index16_state =>
3564
                                 -- advance pc
3565
             pc_ctrl    <= incr_pc;
3566
                                 -- fetch low byte
3567
             md_ctrl    <= fetch_next_md;
3568
             addr_ctrl  <= fetch_ad;
3569
                                 next_state <= index16_2_state;
3570
 
3571
                          -- ea = index register + md (16 bit offset)
3572
                          -- ea holds post byte
3573
                          when index16_2_state =>
3574
                                 case ea(6 downto 5) is
3575
                            when "00" =>
3576
                              left_ctrl  <= ix_left;
3577
                            when "01" =>
3578
                              left_ctrl  <= iy_left;
3579
                                 when "10" =>
3580
                              left_ctrl  <= up_left;
3581
                                 when others =>
3582
                                 -- when "11" =>
3583
                              left_ctrl  <= sp_left;
3584
                                 end case;
3585
                                 -- ea = index reg + md
3586
                            right_ctrl <= md_right;
3587
                            alu_ctrl   <= alu_add16;
3588
             ea_ctrl    <= load_ea;
3589
                                 -- return to previous state
3590
                            if ea(4) = '0' then
3591
                                         st_ctrl      <= pull_st;
3592
                                         next_state   <= saved_state;
3593
                                 else
3594
                                         next_state   <= indirect_state;
3595
                                 end if;
3596
           --
3597
                          -- pc relative with 8 bit signed offest
3598
                          -- md holds signed offset
3599
                          --
3600
                          when pcrel8_state =>
3601
                                 -- ea = pc + signed md
3602
                            left_ctrl  <= pc_left;
3603
                            right_ctrl <= md_sign8_right;
3604
                            alu_ctrl   <= alu_add16;
3605
             ea_ctrl    <= load_ea;
3606
                                 -- return to previous state
3607
                            if ea(4) = '0' then
3608
                                         st_ctrl      <= pull_st;
3609
                                         next_state   <= saved_state;
3610
                                 else
3611
                                         next_state   <= indirect_state;
3612
                                 end if;
3613
 
3614
                          -- pc relative addressing with 16 bit offset
3615
                          -- pick up the low byte of the offset in md
3616
                          -- advance the pc
3617
                          when pcrel16_state =>
3618
                                 -- advance pc
3619
             pc_ctrl    <= incr_pc;
3620
                                 -- fetch low byte
3621
             md_ctrl    <= fetch_next_md;
3622
             addr_ctrl  <= fetch_ad;
3623
                                 next_state <= pcrel16_2_state;
3624
 
3625
                          -- pc relative with16 bit signed offest
3626
                          -- md holds signed offset
3627
                          when pcrel16_2_state =>
3628
                                 -- ea = pc +  md
3629
                            left_ctrl  <= pc_left;
3630
                            right_ctrl <= md_right;
3631
                            alu_ctrl   <= alu_add16;
3632
             ea_ctrl    <= load_ea;
3633
                                 -- return to previous state
3634
                            if ea(4) = '0' then
3635
                                         st_ctrl      <= pull_st;
3636
                                         next_state   <= saved_state;
3637
                                 else
3638
                                         next_state   <= indirect_state;
3639
                                 end if;
3640
 
3641
                          -- indexed to address
3642
                          -- pick up the low byte of the address
3643
                          -- advance the pc
3644
                          when indexaddr_state =>
3645
                                 -- advance pc
3646
             pc_ctrl    <= incr_pc;
3647
                                 -- fetch low byte
3648
             md_ctrl    <= fetch_next_md;
3649
             addr_ctrl  <= fetch_ad;
3650
                                 next_state <= indexaddr2_state;
3651
 
3652
                          -- indexed to absolute address
3653
                          -- md holds address
3654
                          -- ea hold indexing mode byte
3655
                          when indexaddr2_state =>
3656
                                 -- ea = md
3657
                            left_ctrl  <= pc_left;
3658
                            right_ctrl <= md_right;
3659
                            alu_ctrl   <= alu_ld16;
3660
             ea_ctrl    <= load_ea;
3661
                                 -- return to previous state
3662
                            if ea(4) = '0' then
3663
                                         st_ctrl      <= pull_st;
3664
                                         next_state   <= saved_state;
3665
                                 else
3666
                                         next_state   <= indirect_state;
3667
                                 end if;
3668
 
3669
           --
3670
                          -- load md with high byte of indirect address
3671
                          -- pointed to by ea
3672
                          -- increment ea
3673
                          --
3674
                          when indirect_state =>
3675
                                 -- increment ea
3676
                            left_ctrl  <= ea_left;
3677
                            right_ctrl <= one_right;
3678
                            alu_ctrl   <= alu_add16;
3679
             ea_ctrl    <= load_ea;
3680
                                 -- fetch high byte
3681
             md_ctrl    <= fetch_first_md;
3682
             addr_ctrl  <= read_ad;
3683
                                 next_state <= indirect2_state;
3684
           --
3685
                          -- load md with low byte of indirect address
3686
                          -- pointed to by ea
3687
                          -- ea has previously been incremented
3688
                          --
3689
                          when indirect2_state =>
3690
                                 -- fetch high byte
3691
             md_ctrl    <= fetch_next_md;
3692
             addr_ctrl  <= read_ad;
3693
             dout_ctrl  <= md_lo_dout;
3694
                                 next_state <= indirect3_state;
3695
                          --
3696
                          -- complete idirect addressing
3697
                          -- by loading ea with md
3698
                          --
3699
                          when indirect3_state =>
3700
                                 -- load ea with md
3701
                            left_ctrl  <= ea_left;
3702
                            right_ctrl <= md_right;
3703
                            alu_ctrl   <= alu_ld16;
3704
             ea_ctrl    <= load_ea;
3705
                                 -- return to previous state
3706
                                 st_ctrl      <= pull_st;
3707
                                 next_state   <= saved_state;
3708
 
3709
           --
3710
                          -- ea holds the low byte of the absolute address
3711
                          -- Move ea low byte into ea high byte
3712
                          -- load new ea low byte to for absolute 16 bit address
3713
                          -- advance the program counter
3714
                          --
3715
                          when extended_state => -- fetch ea low byte
3716
                                        -- increment pc
3717
               pc_ctrl      <= incr_pc;
3718
                                        -- fetch next effective address bytes
3719
                                        ea_ctrl      <= fetch_next_ea;
3720
               addr_ctrl    <= fetch_ad;
3721
                                   -- return to previous state
3722
                                   st_ctrl      <= pull_st;
3723
                                   next_state   <= saved_state;
3724
 
3725
                                when lea_state => -- here on load effective address
3726
                                        -- load index register with effective address
3727
               left_ctrl  <= pc_left;
3728
                                        right_ctrl <= ea_right;
3729
                                   alu_ctrl   <= alu_lea;
3730
                                        case op_code(3 downto 0) is
3731
                                        when "0000" => -- leax
3732
                   cc_ctrl    <= load_cc;
3733
                   ix_ctrl    <= load_ix;
3734
                                        when "0001" => -- leay
3735
                   cc_ctrl    <= load_cc;
3736
                   iy_ctrl    <= load_iy;
3737
                                        when "0010" => -- leas
3738
                   sp_ctrl    <= load_sp;
3739
                                        when "0011" => -- leau
3740
                   up_ctrl    <= load_up;
3741
                                        when others =>
3742
                                            null;
3743
                                        end case;
3744
               next_state   <= fetch_state;
3745
 
3746
                                --
3747
                                -- jump to subroutine
3748
                                -- sp=sp-1
3749
                                -- call push_return_lo_state to save pc
3750
                                -- return to jmp_state
3751
                                --
3752
                                when jsr_state =>
3753
                                        -- decrement sp
3754
               left_ctrl    <= sp_left;
3755
                                        right_ctrl   <= one_right;
3756
                                   alu_ctrl     <= alu_sub16;
3757
               sp_ctrl      <= load_sp;
3758
                                        -- call push_return_state
3759
                                        st_ctrl      <= push_st;
3760
                                        return_state <= jmp_state;
3761
               next_state   <= push_return_lo_state;
3762
 
3763
                                --
3764
                                -- Load pc with ea
3765
                                -- (JMP)
3766
                                --
3767
                                when jmp_state =>
3768
                                        -- load PC with effective address
3769
               left_ctrl  <= pc_left;
3770
                                        right_ctrl <= ea_right;
3771
                                   alu_ctrl   <= alu_ld16;
3772
                                        pc_ctrl    <= load_pc;
3773
               next_state <= fetch_state;
3774
 
3775
                                --
3776
                                -- long branch or branch to subroutine
3777
                                -- pick up next md byte
3778
                                -- md_hi = md_lo
3779
                                -- md_lo = (pc)
3780
                                -- pc=pc+1
3781
                                -- if a lbsr push return address
3782
                                -- continue to sbranch_state
3783
                                -- to evaluate conditional branches
3784
                                --
3785
                                when lbranch_state =>
3786
                                        pc_ctrl    <= incr_pc;
3787
                                        -- fetch the next byte into md_lo
3788
               md_ctrl    <= fetch_next_md;
3789
               addr_ctrl  <= fetch_ad;
3790
                                        -- if lbsr - push return address
3791
                                        -- then continue on to short branch
3792
                                        if op_code = "00010111" then
3793
                                          st_ctrl      <= push_st;
3794
                                          return_state <= sbranch_state;
3795
                 next_state   <= push_return_lo_state;
3796
                                        else
3797
                 next_state   <= sbranch_state;
3798
                                        end if;
3799
 
3800
                                 --
3801
                                 -- here to execute conditional branch
3802
                                 -- short conditional branch md = signed 8 bit offset
3803
                                 -- long branch md = 16 bit offset
3804
                                 -- 
3805
                  when sbranch_state =>
3806
               left_ctrl  <= pc_left;
3807
                                        right_ctrl <= md_right;
3808
                                   alu_ctrl   <= alu_add16;
3809
                                        -- Test condition for branch
3810
                              if op_code(7 downto 4) = "0010" then -- conditional branch
3811
                 case op_code(3 downto 0) is
3812
                           when "0000" => -- bra
3813
                                            cond_true := (1 = 1);
3814
                           when "0001" => -- brn
3815
                                            cond_true := (1 = 0);
3816
                           when "0010" => -- bhi
3817
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
3818
                           when "0011" => -- bls
3819
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
3820
                           when "0100" => -- bcc/bhs
3821
                                            cond_true := (cc(CBIT) = '0');
3822
                           when "0101" => -- bcs/blo
3823
                                            cond_true := (cc(CBIT) = '1');
3824
                           when "0110" => -- bne
3825
                             cond_true := (cc(ZBIT) = '0');
3826
                           when "0111" => -- beq
3827
                                            cond_true := (cc(ZBIT) = '1');
3828
                           when "1000" => -- bvc
3829
                                            cond_true := (cc(VBIT) = '0');
3830
                           when "1001" => -- bvs
3831
                                            cond_true := (cc(VBIT) = '1');
3832
                           when "1010" => -- bpl
3833
                                            cond_true := (cc(NBIT) = '0');
3834
                           when "1011" => -- bmi
3835
                                            cond_true := (cc(NBIT) = '1');
3836
                           when "1100" => -- bge
3837
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
3838
                           when "1101" => -- blt
3839
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
3840
                           when "1110" => -- bgt
3841
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
3842
                           when "1111" => -- ble
3843
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
3844
                           when others =>
3845
                                            null;
3846
                           end case;
3847
                                        else
3848
                                          cond_true := (1 = 1); -- lbra, lbsr, bsr
3849
                                   end if;
3850
                                        if cond_true then
3851
                                          pc_ctrl    <= load_pc;
3852
               end if;
3853
                                        next_state   <= fetch_state;
3854
 
3855
                                 --
3856
                                 -- push return address onto the S stack
3857
                                 --
3858
                                 -- (sp) = pc_lo
3859
                                 -- sp = sp - 1
3860
                                 --
3861
                                 when push_return_lo_state =>
3862
                                          -- decrement the sp
3863
                 left_ctrl  <= sp_left;
3864
                 right_ctrl <= one_right;
3865
                 alu_ctrl   <= alu_sub16;
3866
                 sp_ctrl    <= load_sp;
3867
                 -- write PC low
3868
                 addr_ctrl  <= pushs_ad;
3869
                 dout_ctrl  <= pc_lo_dout;
3870
                 next_state <= push_return_hi_state;
3871
 
3872
                                --
3873
                                -- push program counter hi byte onto the stack
3874
                                -- (sp) = pc_hi
3875
                                -- sp = sp
3876
                                -- return to originating state
3877
                                --
3878
                                when push_return_hi_state =>
3879
                                          -- write pc hi bytes
3880
                 addr_ctrl    <= pushs_ad;
3881
                 dout_ctrl    <= pc_hi_dout;
3882
                                          st_ctrl      <= pull_st;
3883
                 next_state   <= saved_state;
3884
 
3885
                                 when pull_return_hi_state =>
3886
                                          -- increment the sp
3887
                 left_ctrl  <= sp_left;
3888
                 right_ctrl <= one_right;
3889
                 alu_ctrl   <= alu_add16;
3890
                 sp_ctrl    <= load_sp;
3891
                 -- read pc hi
3892
                                          pc_ctrl    <= pull_hi_pc;
3893
                 addr_ctrl  <= pulls_ad;
3894
                 next_state <= pull_return_lo_state;
3895
 
3896
                                when pull_return_lo_state =>
3897
                                          -- increment the SP
3898
                 left_ctrl  <= sp_left;
3899
                 right_ctrl <= one_right;
3900
                 alu_ctrl   <= alu_add16;
3901
                 sp_ctrl    <= load_sp;
3902
                                          -- read pc low
3903
                                          pc_ctrl    <= pull_lo_pc;
3904
                 addr_ctrl  <= pulls_ad;
3905
                 dout_ctrl  <= pc_lo_dout;
3906
                                          --
3907
                                          st_ctrl      <= pull_st;
3908
                 next_state   <= saved_state;
3909
 
3910
                                 when andcc_state =>
3911
                                          -- AND CC with md
3912
                 left_ctrl  <= md_left;
3913
                 right_ctrl <= zero_right;
3914
                 alu_ctrl   <= alu_andcc;
3915
                 cc_ctrl    <= load_cc;
3916
                                          --
3917
                                          st_ctrl    <= pull_st;
3918
                                     next_state <= saved_state;
3919
 
3920
                                 when orcc_state =>
3921
                                          -- OR CC with md
3922
                 left_ctrl  <= md_left;
3923
                 right_ctrl <= zero_right;
3924
                 alu_ctrl   <= alu_orcc;
3925
                 cc_ctrl    <= load_cc;
3926
                                          --
3927
                                          st_ctrl    <= pull_st;
3928
                                     next_state <= saved_state;
3929
 
3930
                                 when tfr_state =>
3931
                                          -- select source register
3932
                                          case md(7 downto 4) is
3933
                                          when "0000" =>
3934
                                            left_ctrl <= accd_left;
3935
                                          when "0001" =>
3936
                                            left_ctrl <= ix_left;
3937
                                          when "0010" =>
3938
                                            left_ctrl <= iy_left;
3939
                                          when "0011" =>
3940
                                            left_ctrl <= up_left;
3941
                                          when "0100" =>
3942
                                            left_ctrl <= sp_left;
3943
                                          when "0101" =>
3944
                                            left_ctrl <= pc_left;
3945
                                          when "1000" =>
3946
                                            left_ctrl <= acca_left;
3947
                                          when "1001" =>
3948
                                            left_ctrl <= accb_left;
3949
                                          when "1010" =>
3950
                                            left_ctrl <= cc_left;
3951
                                          when "1011" =>
3952
                                            left_ctrl <= dp_left;
3953
                                          when others =>
3954
                   left_ctrl  <= md_left;
3955
                                          end case;
3956
                 right_ctrl <= zero_right;
3957
                 alu_ctrl   <= alu_tfr;
3958
                                          -- select destination register
3959
                                          case md(3 downto 0) is
3960
                                          when "0000" => -- accd
3961
                   acca_ctrl  <= load_hi_acca;
3962
                   accb_ctrl  <= load_accb;
3963
                                          when "0001" => -- ix
3964
                   ix_ctrl    <= load_ix;
3965
                                          when "0010" => -- iy
3966
                   iy_ctrl    <= load_iy;
3967
                                          when "0011" => -- up
3968
                   up_ctrl    <= load_up;
3969
                                          when "0100" => -- sp
3970
                   sp_ctrl    <= load_sp;
3971
                                          when "0101" => -- pc
3972
                   pc_ctrl    <= load_pc;
3973
                                          when "1000" => -- acca
3974
                   acca_ctrl  <= load_acca;
3975
                                          when "1001" => -- accb
3976
                   accb_ctrl  <= load_accb;
3977
                                          when "1010" => -- cc
3978
                   cc_ctrl    <= load_cc;
3979
                                          when "1011" => --dp
3980
                   dp_ctrl    <= load_dp;
3981
                                          when others =>
3982
                                            null;
3983
                                          end case;
3984
                                          --
3985
                                          st_ctrl      <= pull_st;
3986
                                     next_state   <= saved_state;
3987
 
3988
                                 when exg_state =>
3989
                                          -- save destination register
3990
                                          case md(3 downto 0) is
3991
                                          when "0000" =>
3992
                                            left_ctrl <= accd_left;
3993
                                          when "0001" =>
3994
                                            left_ctrl <= ix_left;
3995
                                          when "0010" =>
3996
                                            left_ctrl <= iy_left;
3997
                                          when "0011" =>
3998
                                            left_ctrl <= up_left;
3999
                                          when "0100" =>
4000
                                            left_ctrl <= sp_left;
4001
                                          when "0101" =>
4002
                                            left_ctrl <= pc_left;
4003
                                          when "1000" =>
4004
                                            left_ctrl <= acca_left;
4005
                                          when "1001" =>
4006
                                            left_ctrl <= accb_left;
4007
                                          when "1010" =>
4008
                                            left_ctrl <= cc_left;
4009
                                          when "1011" =>
4010
                                            left_ctrl <= dp_left;
4011
                                          when others =>
4012
                   left_ctrl  <= md_left;
4013
                                          end case;
4014
                 right_ctrl <= zero_right;
4015
                 alu_ctrl   <= alu_tfr;
4016
                 ea_ctrl    <= load_ea;
4017
                                          -- call tranfer microcode
4018
                                          st_ctrl      <= push_st;
4019
                                          return_state <= exg1_state;
4020
                                     next_state   <= tfr_state;
4021
 
4022
                                 when exg1_state =>
4023
                                          -- restore destination
4024
                 left_ctrl  <= ea_left;
4025
                 right_ctrl <= zero_right;
4026
                 alu_ctrl   <= alu_tfr;
4027
                                          -- save as source register
4028
                                          case md(7 downto 4) is
4029
                                          when "0000" => -- accd
4030
                   acca_ctrl  <= load_hi_acca;
4031
                   accb_ctrl  <= load_accb;
4032
                                          when "0001" => -- ix
4033
                   ix_ctrl    <= load_ix;
4034
                                          when "0010" => -- iy
4035
                   iy_ctrl    <= load_iy;
4036
                                          when "0011" => -- up
4037
                   up_ctrl    <= load_up;
4038
                                          when "0100" => -- sp
4039
                   sp_ctrl    <= load_sp;
4040
                                          when "0101" => -- pc
4041
                   pc_ctrl    <= load_pc;
4042
                                          when "1000" => -- acca
4043
                   acca_ctrl  <= load_acca;
4044
                                          when "1001" => -- accb
4045
                   accb_ctrl  <= load_accb;
4046
                                          when "1010" => -- cc
4047
                   cc_ctrl    <= load_cc;
4048
                                          when "1011" => --dp
4049
                   dp_ctrl    <= load_dp;
4050
                                          when others =>
4051
                                            null;
4052
                                          end case;
4053
                                     next_state   <= fetch_state;
4054
 
4055
                                 when mul_state =>
4056
                                          -- move acca to md
4057
                 left_ctrl  <= acca_left;
4058
                 right_ctrl <= zero_right;
4059
                 alu_ctrl   <= alu_st16;
4060
                 md_ctrl    <= load_md;
4061
                                     next_state <= mulea_state;
4062
 
4063
                                 when mulea_state =>
4064
                                          -- move accb to ea
4065
                 left_ctrl  <= accb_left;
4066
                 right_ctrl <= zero_right;
4067
                 alu_ctrl   <= alu_st16;
4068
                 ea_ctrl    <= load_ea;
4069
                                     next_state <= muld_state;
4070
 
4071
                                 when muld_state =>
4072
                                          -- clear accd
4073
                 left_ctrl  <= acca_left;
4074
                 right_ctrl <= zero_right;
4075
                 alu_ctrl   <= alu_ld8;
4076
                 acca_ctrl  <= load_hi_acca;
4077
                 accb_ctrl  <= load_accb;
4078
                                     next_state <= mul0_state;
4079
 
4080
                                 when mul0_state =>
4081
                                          -- if bit 0 of ea set, add accd to md
4082
                 left_ctrl  <= accd_left;
4083
                                          if ea(0) = '1' then
4084
                   right_ctrl <= md_right;
4085
                                          else
4086
                   right_ctrl <= zero_right;
4087
                                          end if;
4088
                 alu_ctrl   <= alu_mul;
4089
                 cc_ctrl    <= load_cc;
4090
                 acca_ctrl  <= load_hi_acca;
4091
                 accb_ctrl  <= load_accb;
4092
                 md_ctrl    <= shiftl_md;
4093
                                     next_state <= mul1_state;
4094
 
4095
                                 when mul1_state =>
4096
                                          -- if bit 1 of ea set, add accd to md
4097
                 left_ctrl  <= accd_left;
4098
                                          if ea(1) = '1' then
4099
                   right_ctrl <= md_right;
4100
                                          else
4101
                   right_ctrl <= zero_right;
4102
                                          end if;
4103
                 alu_ctrl   <= alu_mul;
4104
                 cc_ctrl    <= load_cc;
4105
                 acca_ctrl  <= load_hi_acca;
4106
                 accb_ctrl  <= load_accb;
4107
                 md_ctrl    <= shiftl_md;
4108
                                     next_state <= mul2_state;
4109
 
4110
                                 when mul2_state =>
4111
                                          -- if bit 2 of ea set, add accd to md
4112
                 left_ctrl  <= accd_left;
4113
                                          if ea(2) = '1' then
4114
                   right_ctrl <= md_right;
4115
                                          else
4116
                   right_ctrl <= zero_right;
4117
                                          end if;
4118
                 alu_ctrl   <= alu_mul;
4119
                 cc_ctrl    <= load_cc;
4120
                 acca_ctrl  <= load_hi_acca;
4121
                 accb_ctrl  <= load_accb;
4122
                 md_ctrl    <= shiftl_md;
4123
                                     next_state <= mul3_state;
4124
 
4125
                                 when mul3_state =>
4126
                                          -- if bit 3 of ea set, add accd to md
4127
                 left_ctrl  <= accd_left;
4128
                                          if ea(3) = '1' then
4129
                   right_ctrl <= md_right;
4130
                                          else
4131
                   right_ctrl <= zero_right;
4132
                                          end if;
4133
                 alu_ctrl   <= alu_mul;
4134
                 cc_ctrl    <= load_cc;
4135
                 acca_ctrl  <= load_hi_acca;
4136
                 accb_ctrl  <= load_accb;
4137
                 md_ctrl    <= shiftl_md;
4138
                                     next_state <= mul4_state;
4139
 
4140
                                 when mul4_state =>
4141
                                          -- if bit 4 of ea set, add accd to md
4142
                 left_ctrl  <= accd_left;
4143
                                          if ea(4) = '1' then
4144
                   right_ctrl <= md_right;
4145
                                          else
4146
                   right_ctrl <= zero_right;
4147
                                          end if;
4148
                 alu_ctrl   <= alu_mul;
4149
                 cc_ctrl    <= load_cc;
4150
                 acca_ctrl  <= load_hi_acca;
4151
                 accb_ctrl  <= load_accb;
4152
                 md_ctrl    <= shiftl_md;
4153
                                     next_state <= mul5_state;
4154
 
4155
                                 when mul5_state =>
4156
                                          -- if bit 5 of ea set, add accd to md
4157
                 left_ctrl  <= accd_left;
4158
                                          if ea(5) = '1' then
4159
                   right_ctrl <= md_right;
4160
                                          else
4161
                   right_ctrl <= zero_right;
4162
                                          end if;
4163
                 alu_ctrl   <= alu_mul;
4164
                 cc_ctrl    <= load_cc;
4165
                 acca_ctrl  <= load_hi_acca;
4166
                 accb_ctrl  <= load_accb;
4167
                 md_ctrl    <= shiftl_md;
4168
                                     next_state <= mul6_state;
4169
 
4170
                                 when mul6_state =>
4171
                                          -- if bit 6 of ea set, add accd to md
4172
                 left_ctrl  <= accd_left;
4173
                                          if ea(6) = '1' then
4174
                   right_ctrl <= md_right;
4175
                                          else
4176
                   right_ctrl <= zero_right;
4177
                                          end if;
4178
                 alu_ctrl   <= alu_mul;
4179
                 cc_ctrl    <= load_cc;
4180
                 acca_ctrl  <= load_hi_acca;
4181
                 accb_ctrl  <= load_accb;
4182
                 md_ctrl    <= shiftl_md;
4183
                                     next_state <= mul7_state;
4184
 
4185
                                 when mul7_state =>
4186
                                          -- if bit 7 of ea set, add accd to md
4187
                 left_ctrl  <= accd_left;
4188
                                          if ea(7) = '1' then
4189
                   right_ctrl <= md_right;
4190
                                          else
4191
                   right_ctrl <= zero_right;
4192
                                          end if;
4193
                 alu_ctrl   <= alu_mul;
4194
                 cc_ctrl    <= load_cc;
4195
                 acca_ctrl  <= load_hi_acca;
4196
                 accb_ctrl  <= load_accb;
4197
                 md_ctrl    <= shiftl_md;
4198
                                     next_state <= fetch_state;
4199
 
4200
                          --
4201
                          -- Enter here on pushs
4202
                          -- ea holds post byte
4203
                          --
4204
                          when pshs_state =>
4205
             -- decrement sp if any registers to be pushed
4206
             left_ctrl  <= sp_left;
4207
             right_ctrl <= one_right;
4208
             alu_ctrl   <= alu_sub16;
4209
                                 -- idle        address
4210
             addr_ctrl  <= idle_ad;
4211
                            dout_ctrl  <= cc_dout;
4212
                                 if ea(7 downto 0) = "00000000" then
4213
               sp_ctrl    <= latch_sp;
4214
                                 else
4215
               sp_ctrl    <= load_sp;
4216
                                 end if;
4217
                                 if ea(7) = '1' then
4218
               next_state <= pshs_pcl_state;
4219
                                 elsif ea(6) = '1' then
4220
               next_state <= pshs_upl_state;
4221
                                 elsif ea(5) = '1' then
4222
                                   next_state <= pshs_iyl_state;
4223
                                 elsif ea(4) = '1' then
4224
                                   next_state <= pshs_ixl_state;
4225
                                 elsif ea(3) = '1' then
4226
                                   next_state <= pshs_dp_state;
4227
                                 elsif ea(2) = '1' then
4228
                                   next_state <= pshs_accb_state;
4229
                                 elsif ea(1) = '1' then
4230
                                   next_state <= pshs_acca_state;
4231
                                 elsif ea(0) = '1' then
4232
                                   next_state <= pshs_cc_state;
4233
                                 else
4234
                                   next_state <= fetch_state;
4235
                                 end if;
4236
 
4237
                          when pshs_pcl_state =>
4238
             -- decrement sp
4239
             left_ctrl  <= sp_left;
4240
             right_ctrl <= one_right;
4241
             alu_ctrl   <= alu_sub16;
4242
             sp_ctrl    <= load_sp;
4243
                                 -- write pc low
4244
             addr_ctrl  <= pushs_ad;
4245
                            dout_ctrl  <= pc_lo_dout;
4246
             next_state <= pshs_pch_state;
4247
 
4248
                          when pshs_pch_state =>
4249
             -- decrement sp
4250
             left_ctrl  <= sp_left;
4251
             right_ctrl <= one_right;
4252
             alu_ctrl   <= alu_sub16;
4253
                                 if ea(6 downto 0) = "0000000" then
4254
               sp_ctrl    <= latch_sp;
4255
                                 else
4256
               sp_ctrl    <= load_sp;
4257
                                 end if;
4258
                                 -- write pc hi
4259
             addr_ctrl  <= pushs_ad;
4260
                            dout_ctrl  <= pc_hi_dout;
4261
                                 if ea(6) = '1' then
4262
               next_state <= pshs_upl_state;
4263
                                 elsif ea(5) = '1' then
4264
                                   next_state <= pshs_iyl_state;
4265
                                 elsif ea(4) = '1' then
4266
                                   next_state <= pshs_ixl_state;
4267
                                 elsif ea(3) = '1' then
4268
                                   next_state <= pshs_dp_state;
4269
                                 elsif ea(2) = '1' then
4270
                                   next_state <= pshs_accb_state;
4271
                                 elsif ea(1) = '1' then
4272
                                   next_state <= pshs_acca_state;
4273
                                 elsif ea(0) = '1' then
4274
                                   next_state <= pshs_cc_state;
4275
                                 else
4276
                                   next_state <= fetch_state;
4277
                                 end if;
4278
 
4279
 
4280
                          when pshs_upl_state =>
4281
             -- decrement sp
4282
             left_ctrl  <= sp_left;
4283
             right_ctrl <= one_right;
4284
             alu_ctrl   <= alu_sub16;
4285
             sp_ctrl    <= load_sp;
4286
                                 -- write pc low
4287
             addr_ctrl  <= pushs_ad;
4288
                            dout_ctrl  <= up_lo_dout;
4289
             next_state <= pshs_uph_state;
4290
 
4291
                          when pshs_uph_state =>
4292
             -- decrement sp
4293
             left_ctrl  <= sp_left;
4294
             right_ctrl <= one_right;
4295
             alu_ctrl   <= alu_sub16;
4296
                                 if ea(5 downto 0) = "000000" then
4297
               sp_ctrl    <= latch_sp;
4298
                                 else
4299
               sp_ctrl    <= load_sp;
4300
                                 end if;
4301
                                 -- write pc hi
4302
             addr_ctrl  <= pushs_ad;
4303
                            dout_ctrl  <= up_hi_dout;
4304
                                 if ea(5) = '1' then
4305
                                   next_state   <= pshs_iyl_state;
4306
                                 elsif ea(4) = '1' then
4307
                                   next_state   <= pshs_ixl_state;
4308
                                 elsif ea(3) = '1' then
4309
                                   next_state   <= pshs_dp_state;
4310
                                 elsif ea(2) = '1' then
4311
                                   next_state   <= pshs_accb_state;
4312
                                 elsif ea(1) = '1' then
4313
                                   next_state   <= pshs_acca_state;
4314
                                 elsif ea(0) = '1' then
4315
                                   next_state   <= pshs_cc_state;
4316
                                 else
4317
                                   next_state   <= fetch_state;
4318
                                 end if;
4319
 
4320
                          when pshs_iyl_state =>
4321
             -- decrement sp
4322
             left_ctrl  <= sp_left;
4323
             right_ctrl <= one_right;
4324
             alu_ctrl   <= alu_sub16;
4325
             sp_ctrl    <= load_sp;
4326
                                 -- write iy low
4327
             addr_ctrl  <= pushs_ad;
4328
                            dout_ctrl  <= iy_lo_dout;
4329
             next_state <= pshs_iyh_state;
4330
 
4331
                          when pshs_iyh_state =>
4332
             -- decrement sp
4333
             left_ctrl  <= sp_left;
4334
             right_ctrl <= one_right;
4335
             alu_ctrl   <= alu_sub16;
4336
                                 if ea(4 downto 0) = "00000" then
4337
               sp_ctrl    <= latch_sp;
4338
                                 else
4339
               sp_ctrl    <= load_sp;
4340
                                 end if;
4341
                                 -- write iy hi
4342
             addr_ctrl  <= pushs_ad;
4343
                            dout_ctrl  <= iy_hi_dout;
4344
                                 if ea(4) = '1' then
4345
                                   next_state   <= pshs_ixl_state;
4346
                                 elsif ea(3) = '1' then
4347
                                   next_state   <= pshs_dp_state;
4348
                                 elsif ea(2) = '1' then
4349
                                   next_state   <= pshs_accb_state;
4350
                                 elsif ea(1) = '1' then
4351
                                   next_state   <= pshs_acca_state;
4352
                                 elsif ea(0) = '1' then
4353
                                   next_state   <= pshs_cc_state;
4354
                                 else
4355
                                   next_state   <= fetch_state;
4356
                                 end if;
4357
 
4358
                          when pshs_ixl_state =>
4359
             -- decrement sp
4360
             left_ctrl  <= sp_left;
4361
             right_ctrl <= one_right;
4362
             alu_ctrl   <= alu_sub16;
4363
             sp_ctrl    <= load_sp;
4364
                                 -- write ix low
4365
             addr_ctrl  <= pushs_ad;
4366
                            dout_ctrl  <= ix_lo_dout;
4367
             next_state <= pshs_ixh_state;
4368
 
4369
                          when pshs_ixh_state =>
4370
             -- decrement sp
4371
             left_ctrl  <= sp_left;
4372
             right_ctrl <= one_right;
4373
             alu_ctrl   <= alu_sub16;
4374
                                 if ea(3 downto 0) = "0000" then
4375
               sp_ctrl    <= latch_sp;
4376
                                 else
4377
               sp_ctrl    <= load_sp;
4378
                                 end if;
4379
                                 -- write ix hi
4380
             addr_ctrl  <= pushs_ad;
4381
                            dout_ctrl  <= ix_hi_dout;
4382
                                 if ea(3) = '1' then
4383
                                   next_state   <= pshs_dp_state;
4384
                                 elsif ea(2) = '1' then
4385
                                   next_state   <= pshs_accb_state;
4386
                                 elsif ea(1) = '1' then
4387
                                   next_state   <= pshs_acca_state;
4388
                                 elsif ea(0) = '1' then
4389
                                   next_state   <= pshs_cc_state;
4390
                                 else
4391
                                   next_state   <= fetch_state;
4392
                                 end if;
4393
 
4394
                          when pshs_dp_state =>
4395
             -- decrement sp
4396
             left_ctrl  <= sp_left;
4397
             right_ctrl <= one_right;
4398
             alu_ctrl   <= alu_sub16;
4399
                                 if ea(2 downto 0) = "000" then
4400
               sp_ctrl    <= latch_sp;
4401
                                 else
4402
               sp_ctrl    <= load_sp;
4403
                                 end if;
4404
                                 -- write dp
4405
             addr_ctrl  <= pushs_ad;
4406
                            dout_ctrl  <= dp_dout;
4407
                                 if ea(2) = '1' then
4408
                                   next_state   <= pshs_accb_state;
4409
                                 elsif ea(1) = '1' then
4410
                                   next_state   <= pshs_acca_state;
4411
                                 elsif ea(0) = '1' then
4412
                                   next_state   <= pshs_cc_state;
4413
                                 else
4414
                                   next_state   <= fetch_state;
4415
                                 end if;
4416
 
4417
                          when pshs_accb_state =>
4418
             -- decrement sp
4419
             left_ctrl  <= sp_left;
4420
             right_ctrl <= one_right;
4421
             alu_ctrl   <= alu_sub16;
4422
                                 if ea(1 downto 0) = "00" then
4423
               sp_ctrl    <= latch_sp;
4424
                                 else
4425
               sp_ctrl    <= load_sp;
4426
                                 end if;
4427
                                 -- write accb
4428
             addr_ctrl  <= pushs_ad;
4429
                            dout_ctrl  <= accb_dout;
4430
                                 if ea(1) = '1' then
4431
                                   next_state   <= pshs_acca_state;
4432
                                 elsif ea(0) = '1' then
4433
                                   next_state   <= pshs_cc_state;
4434
                                 else
4435
                                   next_state   <= fetch_state;
4436
                                 end if;
4437
 
4438
                          when pshs_acca_state =>
4439
             -- decrement sp
4440
             left_ctrl  <= sp_left;
4441
             right_ctrl <= one_right;
4442
             alu_ctrl   <= alu_sub16;
4443
                                 if ea(0) = '1' then
4444
               sp_ctrl    <= load_sp;
4445
                                 else
4446
               sp_ctrl    <= latch_sp;
4447
                                 end if;
4448
                                 -- write acca
4449
             addr_ctrl  <= pushs_ad;
4450
                            dout_ctrl  <= acca_dout;
4451
                                 if ea(0) = '1' then
4452
                                   next_state   <= pshs_cc_state;
4453
                                 else
4454
                                   next_state   <= fetch_state;
4455
                                 end if;
4456
 
4457
                          when pshs_cc_state =>
4458
             -- idle sp
4459
                                 -- write cc
4460
             addr_ctrl  <= pushs_ad;
4461
                            dout_ctrl  <= cc_dout;
4462
             next_state <= fetch_state;
4463
 
4464
                          --
4465
                          -- enter here on PULS
4466
                          -- ea hold register mask
4467
                          --
4468
                          when puls_state =>
4469
                                 if ea(0) = '1' then
4470
                                   next_state <= puls_cc_state;
4471
                                 elsif ea(1) = '1' then
4472
                                   next_state <= puls_acca_state;
4473
                                 elsif ea(2) = '1' then
4474
                                   next_state <= puls_accb_state;
4475
                                 elsif ea(3) = '1' then
4476
                                   next_state <= puls_dp_state;
4477
                                 elsif ea(4) = '1' then
4478
                                   next_state <= puls_ixh_state;
4479
                                 elsif ea(5) = '1' then
4480
                                   next_state <= puls_iyh_state;
4481
                                 elsif ea(6) = '1' then
4482
               next_state <= puls_uph_state;
4483
                                 elsif ea(7) = '1' then
4484
               next_state <= puls_pch_state;
4485
                                 else
4486
                                   next_state <= fetch_state;
4487
                                 end if;
4488
 
4489
                          when puls_cc_state =>
4490
                                 -- increment sp
4491
             left_ctrl  <= sp_left;
4492
             right_ctrl <= one_right;
4493
             alu_ctrl   <= alu_add16;
4494
             sp_ctrl    <= load_sp;
4495
                                 -- read cc
4496
             cc_ctrl    <= pull_cc;
4497
             addr_ctrl  <= pulls_ad;
4498
                                 if ea(1) = '1' then
4499
                                   next_state <= puls_acca_state;
4500
                                 elsif ea(2) = '1' then
4501
                                   next_state <= puls_accb_state;
4502
                                 elsif ea(3) = '1' then
4503
                                   next_state <= puls_dp_state;
4504
                                 elsif ea(4) = '1' then
4505
                                   next_state <= puls_ixh_state;
4506
                                 elsif ea(5) = '1' then
4507
                                   next_state <= puls_iyh_state;
4508
                                 elsif ea(6) = '1' then
4509
               next_state <= puls_uph_state;
4510
                                 elsif ea(7) = '1' then
4511
               next_state <= puls_pch_state;
4512
                                 else
4513
                                   next_state <= fetch_state;
4514
                                 end if;
4515
 
4516
                          when puls_acca_state =>
4517
                                 -- increment sp
4518
             left_ctrl  <= sp_left;
4519
             right_ctrl <= one_right;
4520
             alu_ctrl   <= alu_add16;
4521
             sp_ctrl    <= load_sp;
4522
                                 -- read acca
4523
                                 acca_ctrl  <= pull_acca;
4524
             addr_ctrl  <= pulls_ad;
4525
                                 if ea(2) = '1' then
4526
                                   next_state <= puls_accb_state;
4527
                                 elsif ea(3) = '1' then
4528
                                   next_state <= puls_dp_state;
4529
                                 elsif ea(4) = '1' then
4530
                                   next_state <= puls_ixh_state;
4531
                                 elsif ea(5) = '1' then
4532
                                   next_state <= puls_iyh_state;
4533
                                 elsif ea(6) = '1' then
4534
               next_state <= puls_uph_state;
4535
                                 elsif ea(7) = '1' then
4536
               next_state <= puls_pch_state;
4537
                                 else
4538
                                   next_state <= fetch_state;
4539
                                 end if;
4540
 
4541
                          when puls_accb_state =>
4542
                                 -- increment sp
4543
             left_ctrl  <= sp_left;
4544
             right_ctrl <= one_right;
4545
             alu_ctrl   <= alu_add16;
4546
             sp_ctrl    <= load_sp;
4547
                                 -- read accb
4548
                                 accb_ctrl  <= pull_accb;
4549
             addr_ctrl  <= pulls_ad;
4550
                                 if ea(3) = '1' then
4551
                                   next_state <= puls_dp_state;
4552
                                 elsif ea(4) = '1' then
4553
                                   next_state <= puls_ixh_state;
4554
                                 elsif ea(5) = '1' then
4555
                                   next_state <= puls_iyh_state;
4556
                                 elsif ea(6) = '1' then
4557
               next_state <= puls_uph_state;
4558
                                 elsif ea(7) = '1' then
4559
               next_state <= puls_pch_state;
4560
                                 else
4561
                                   next_state <= fetch_state;
4562
                                 end if;
4563
 
4564
                          when puls_dp_state =>
4565
                                 -- increment sp
4566
             left_ctrl  <= sp_left;
4567
             right_ctrl <= one_right;
4568
             alu_ctrl   <= alu_add16;
4569
             sp_ctrl    <= load_sp;
4570
                                 -- read dp
4571
                                 dp_ctrl    <= pull_dp;
4572
             addr_ctrl  <= pulls_ad;
4573
                                 if ea(4) = '1' then
4574
                                   next_state <= puls_ixh_state;
4575
                                 elsif ea(5) = '1' then
4576
                                   next_state <= puls_iyh_state;
4577
                                 elsif ea(6) = '1' then
4578
               next_state <= puls_uph_state;
4579
                                 elsif ea(7) = '1' then
4580
               next_state <= puls_pch_state;
4581
                                 else
4582
                                   next_state <= fetch_state;
4583
                                 end if;
4584
 
4585
                          when puls_ixh_state =>
4586
             -- increment sp
4587
             left_ctrl  <= sp_left;
4588
             right_ctrl <= one_right;
4589
             alu_ctrl   <= alu_add16;
4590
             sp_ctrl    <= load_sp;
4591
                                 -- pull ix hi
4592
                                 ix_ctrl    <= pull_hi_ix;
4593
             addr_ctrl  <= pulls_ad;
4594
             next_state <= puls_ixl_state;
4595
 
4596
                          when puls_ixl_state =>
4597
                                 -- increment sp
4598
             left_ctrl  <= sp_left;
4599
             right_ctrl <= one_right;
4600
             alu_ctrl   <= alu_add16;
4601
             sp_ctrl    <= load_sp;
4602
                                 -- read ix low
4603
                                 ix_ctrl    <= pull_lo_ix;
4604
             addr_ctrl  <= pulls_ad;
4605
                                 if ea(5) = '1' then
4606
                                   next_state <= puls_iyh_state;
4607
                                 elsif ea(6) = '1' then
4608
               next_state <= puls_uph_state;
4609
                                 elsif ea(7) = '1' then
4610
               next_state <= puls_pch_state;
4611
                                 else
4612
                                   next_state <= fetch_state;
4613
                                 end if;
4614
 
4615
                          when puls_iyh_state =>
4616
             -- increment sp
4617
             left_ctrl  <= sp_left;
4618
             right_ctrl <= one_right;
4619
             alu_ctrl   <= alu_add16;
4620
             sp_ctrl    <= load_sp;
4621
                                 -- pull iy hi
4622
                                 iy_ctrl    <= pull_hi_iy;
4623
             addr_ctrl  <= pulls_ad;
4624
             next_state   <= puls_iyl_state;
4625
 
4626
                          when puls_iyl_state =>
4627
             -- increment sp
4628
             left_ctrl  <= sp_left;
4629
             right_ctrl <= one_right;
4630
             alu_ctrl   <= alu_add16;
4631
             sp_ctrl    <= load_sp;
4632
                                 -- read iy low
4633
                                 iy_ctrl    <= pull_lo_iy;
4634
             addr_ctrl  <= pulls_ad;
4635
                                 if ea(6) = '1' then
4636
               next_state <= puls_uph_state;
4637
                                 elsif ea(7) = '1' then
4638
               next_state <= puls_pch_state;
4639
                                 else
4640
                                   next_state <= fetch_state;
4641
                                 end if;
4642
 
4643
                          when puls_uph_state =>
4644
             -- increment sp
4645
             left_ctrl  <= sp_left;
4646
             right_ctrl <= one_right;
4647
             alu_ctrl   <= alu_add16;
4648
             sp_ctrl    <= load_sp;
4649
                                 -- pull up hi
4650
                                 up_ctrl    <= pull_hi_up;
4651
             addr_ctrl  <= pulls_ad;
4652
             next_state <= puls_upl_state;
4653
 
4654
                          when puls_upl_state =>
4655
                                 -- increment sp
4656
             left_ctrl  <= sp_left;
4657
             right_ctrl <= one_right;
4658
             alu_ctrl   <= alu_add16;
4659
             sp_ctrl    <= load_sp;
4660
                                 -- read up low
4661
                                 up_ctrl    <= pull_lo_up;
4662
             addr_ctrl  <= pulls_ad;
4663
                                 if ea(7) = '1' then
4664
               next_state <= puls_pch_state;
4665
                                 else
4666
                                   next_state <= fetch_state;
4667
                                 end if;
4668
 
4669
                          when puls_pch_state =>
4670
             -- increment sp
4671
             left_ctrl  <= sp_left;
4672
             right_ctrl <= one_right;
4673
             alu_ctrl   <= alu_add16;
4674
             sp_ctrl    <= load_sp;
4675
                                 -- pull pc hi
4676
                                 pc_ctrl    <= pull_hi_pc;
4677
             addr_ctrl  <= pulls_ad;
4678
             next_state <= puls_pcl_state;
4679
 
4680
                          when puls_pcl_state =>
4681
                                 -- increment sp
4682
             left_ctrl  <= sp_left;
4683
             right_ctrl <= one_right;
4684
             alu_ctrl   <= alu_add16;
4685
             sp_ctrl    <= load_sp;
4686
                                 -- read pc low
4687
                                 pc_ctrl    <= pull_lo_pc;
4688
             addr_ctrl  <= pulls_ad;
4689
             next_state <= fetch_state;
4690
 
4691
                          --
4692
                          -- Enter here on pshu
4693
                          -- ea holds post byte
4694
                          --
4695
                          when pshu_state =>
4696
             -- decrement up if any registers to be pushed
4697
             left_ctrl  <= up_left;
4698
             right_ctrl <= one_right;
4699
             alu_ctrl   <= alu_sub16;
4700
                                 if ea(7 downto 0) = "00000000" then
4701
               up_ctrl    <= latch_up;
4702
                                 else
4703
               up_ctrl    <= load_up;
4704
                                 end if;
4705
                                 -- write idle bus
4706
                                 if ea(7) = '1' then
4707
               next_state   <= pshu_pcl_state;
4708
                                 elsif ea(6) = '1' then
4709
               next_state   <= pshu_spl_state;
4710
                                 elsif ea(5) = '1' then
4711
                                   next_state   <= pshu_iyl_state;
4712
                                 elsif ea(4) = '1' then
4713
                                   next_state   <= pshu_ixl_state;
4714
                                 elsif ea(3) = '1' then
4715
                                   next_state   <= pshu_dp_state;
4716
                                 elsif ea(2) = '1' then
4717
                                   next_state   <= pshu_accb_state;
4718
                                 elsif ea(1) = '1' then
4719
                                   next_state   <= pshu_acca_state;
4720
                                 elsif ea(0) = '1' then
4721
                                   next_state   <= pshu_cc_state;
4722
                                 else
4723
                                   next_state   <= fetch_state;
4724
                                 end if;
4725
                          --
4726
                          -- push PC onto U stack
4727
                          --
4728
                          when pshu_pcl_state =>
4729
             -- decrement up
4730
             left_ctrl  <= up_left;
4731
             right_ctrl <= one_right;
4732
             alu_ctrl   <= alu_sub16;
4733
             up_ctrl    <= load_up;
4734
                                 -- write pc low
4735
             addr_ctrl  <= pushu_ad;
4736
                            dout_ctrl  <= pc_lo_dout;
4737
             next_state <= pshu_pch_state;
4738
 
4739
                          when pshu_pch_state =>
4740
             -- decrement up
4741
             left_ctrl  <= up_left;
4742
             right_ctrl <= one_right;
4743
             alu_ctrl   <= alu_sub16;
4744
                                 if ea(6 downto 0) = "0000000" then
4745
               up_ctrl    <= latch_up;
4746
                                 else
4747
               up_ctrl    <= load_up;
4748
                                 end if;
4749
                                 -- write pc hi
4750
             addr_ctrl  <= pushu_ad;
4751
                            dout_ctrl  <= pc_hi_dout;
4752
                                 if ea(6) = '1' then
4753
               next_state   <= pshu_spl_state;
4754
                                 elsif ea(5) = '1' then
4755
                                   next_state   <= pshu_iyl_state;
4756
                                 elsif ea(4) = '1' then
4757
                                   next_state   <= pshu_ixl_state;
4758
                                 elsif ea(3) = '1' then
4759
                                   next_state   <= pshu_dp_state;
4760
                                 elsif ea(2) = '1' then
4761
                                   next_state   <= pshu_accb_state;
4762
                                 elsif ea(1) = '1' then
4763
                                   next_state   <= pshu_acca_state;
4764
                                 elsif ea(0) = '1' then
4765
                                   next_state   <= pshu_cc_state;
4766
                                 else
4767
                                   next_state   <= fetch_state;
4768
                                 end if;
4769
 
4770
                          when pshu_spl_state =>
4771
             -- decrement up
4772
             left_ctrl  <= up_left;
4773
             right_ctrl <= one_right;
4774
             alu_ctrl   <= alu_sub16;
4775
             up_ctrl    <= load_up;
4776
                                 -- write sp low
4777
             addr_ctrl  <= pushu_ad;
4778
                            dout_ctrl  <= sp_lo_dout;
4779
             next_state <= pshu_sph_state;
4780
 
4781
                          when pshu_sph_state =>
4782
             -- decrement up
4783
             left_ctrl  <= up_left;
4784
             right_ctrl <= one_right;
4785
             alu_ctrl   <= alu_sub16;
4786
                                 if ea(5 downto 0) = "000000" then
4787
               up_ctrl    <= latch_up;
4788
                                 else
4789
               up_ctrl    <= load_up;
4790
                                 end if;
4791
                                 -- write sp hi
4792
             addr_ctrl  <= pushu_ad;
4793
                            dout_ctrl  <= sp_hi_dout;
4794
                                 if ea(5) = '1' then
4795
                                   next_state   <= pshu_iyl_state;
4796
                                 elsif ea(4) = '1' then
4797
                                   next_state   <= pshu_ixl_state;
4798
                                 elsif ea(3) = '1' then
4799
                                   next_state   <= pshu_dp_state;
4800
                                 elsif ea(2) = '1' then
4801
                                   next_state   <= pshu_accb_state;
4802
                                 elsif ea(1) = '1' then
4803
                                   next_state   <= pshu_acca_state;
4804
                                 elsif ea(0) = '1' then
4805
                                   next_state   <= pshu_cc_state;
4806
                                 else
4807
                                   next_state   <= fetch_state;
4808
                                 end if;
4809
 
4810
                          when pshu_iyl_state =>
4811
             -- decrement up
4812
             left_ctrl  <= up_left;
4813
             right_ctrl <= one_right;
4814
             alu_ctrl   <= alu_sub16;
4815
             up_ctrl    <= load_up;
4816
                                 -- write iy low
4817
             addr_ctrl  <= pushu_ad;
4818
                            dout_ctrl  <= iy_lo_dout;
4819
             next_state <= pshu_iyh_state;
4820
 
4821
                          when pshu_iyh_state =>
4822
             -- decrement up
4823
             left_ctrl  <= up_left;
4824
             right_ctrl <= one_right;
4825
             alu_ctrl   <= alu_sub16;
4826
                                 if ea(4 downto 0) = "00000" then
4827
               up_ctrl    <= latch_up;
4828
                                 else
4829
               up_ctrl    <= load_up;
4830
                                 end if;
4831
                                 -- write iy hi
4832
             addr_ctrl  <= pushu_ad;
4833
                            dout_ctrl  <= iy_hi_dout;
4834
                                 if ea(4) = '1' then
4835
                                   next_state   <= pshu_ixl_state;
4836
                                 elsif ea(3) = '1' then
4837
                                   next_state   <= pshu_dp_state;
4838
                                 elsif ea(2) = '1' then
4839
                                   next_state   <= pshu_accb_state;
4840
                                 elsif ea(1) = '1' then
4841
                                   next_state   <= pshu_acca_state;
4842
                                 elsif ea(0) = '1' then
4843
                                   next_state   <= pshu_cc_state;
4844
                                 else
4845
                                   next_state   <= fetch_state;
4846
                                 end if;
4847
 
4848
                          when pshu_ixl_state =>
4849
             -- decrement up
4850
             left_ctrl  <= up_left;
4851
             right_ctrl <= one_right;
4852
             alu_ctrl   <= alu_sub16;
4853
             up_ctrl    <= load_up;
4854
                                 -- write ix low
4855
             addr_ctrl  <= pushu_ad;
4856
                            dout_ctrl  <= ix_lo_dout;
4857
             next_state <= pshu_ixh_state;
4858
 
4859
                          when pshu_ixh_state =>
4860
             -- decrement up
4861
             left_ctrl  <= up_left;
4862
             right_ctrl <= one_right;
4863
             alu_ctrl   <= alu_sub16;
4864
                                 if ea(3 downto 0) = "0000" then
4865
               up_ctrl    <= latch_up;
4866
                                 else
4867
               up_ctrl    <= load_up;
4868
                                 end if;
4869
                                 -- write ix hi
4870
             addr_ctrl  <= pushu_ad;
4871
                            dout_ctrl  <= ix_hi_dout;
4872
                                 if ea(3) = '1' then
4873
                                   next_state   <= pshu_dp_state;
4874
                                 elsif ea(2) = '1' then
4875
                                   next_state   <= pshu_accb_state;
4876
                                 elsif ea(1) = '1' then
4877
                                   next_state   <= pshu_acca_state;
4878
                                 elsif ea(0) = '1' then
4879
                                   next_state   <= pshu_cc_state;
4880
                                 else
4881
                                   next_state   <= fetch_state;
4882
                                 end if;
4883
 
4884
                          when pshu_dp_state =>
4885
             -- decrement up
4886
             left_ctrl  <= up_left;
4887
             right_ctrl <= one_right;
4888
             alu_ctrl   <= alu_sub16;
4889
                                 if ea(2 downto 0) = "000" then
4890
               up_ctrl    <= latch_up;
4891
                                 else
4892
               up_ctrl    <= load_up;
4893
                                 end if;
4894
                                 -- write dp
4895
             addr_ctrl  <= pushu_ad;
4896
                            dout_ctrl  <= dp_dout;
4897
                                 if ea(2) = '1' then
4898
                                   next_state   <= pshu_accb_state;
4899
                                 elsif ea(1) = '1' then
4900
                                   next_state   <= pshu_acca_state;
4901
                                 elsif ea(0) = '1' then
4902
                                   next_state   <= pshu_cc_state;
4903
                                 else
4904
                                   next_state   <= fetch_state;
4905
                                 end if;
4906
 
4907
                          when pshu_accb_state =>
4908
             -- decrement up
4909
             left_ctrl  <= up_left;
4910
             right_ctrl <= one_right;
4911
             alu_ctrl   <= alu_sub16;
4912
                                 if ea(1 downto 0) = "00" then
4913
               up_ctrl    <= latch_up;
4914
                                 else
4915
               up_ctrl    <= load_up;
4916
                                 end if;
4917
                                 -- write accb
4918
             addr_ctrl  <= pushu_ad;
4919
                            dout_ctrl  <= accb_dout;
4920
                                 if ea(1) = '1' then
4921
                                   next_state   <= pshu_acca_state;
4922
                                 elsif ea(0) = '1' then
4923
                                   next_state   <= pshu_cc_state;
4924
                                 else
4925
                                   next_state   <= fetch_state;
4926
                                 end if;
4927
 
4928
                          when pshu_acca_state =>
4929
             -- decrement up
4930
             left_ctrl  <= up_left;
4931
             right_ctrl <= one_right;
4932
             alu_ctrl   <= alu_sub16;
4933
                                 if ea(0) = '0' then
4934
               up_ctrl    <= latch_up;
4935
                                 else
4936
               up_ctrl    <= load_up;
4937
                                 end if;
4938
                                 -- write acca
4939
             addr_ctrl  <= pushu_ad;
4940
                            dout_ctrl  <= acca_dout;
4941
                                 if ea(0) = '1' then
4942
                                   next_state   <= pshu_cc_state;
4943
                                 else
4944
                                   next_state   <= fetch_state;
4945
                                 end if;
4946
 
4947
                          when pshu_cc_state =>
4948
             -- idle up
4949
                                 -- write cc
4950
             addr_ctrl  <= pushu_ad;
4951
                            dout_ctrl  <= cc_dout;
4952
             next_state <= fetch_state;
4953
 
4954
                          --
4955
                          -- enter here on PULU
4956
                          -- ea hold register mask
4957
                          --
4958
                          when pulu_state =>
4959
                                 -- idle UP
4960
                                 -- idle bus
4961
                                 if ea(0) = '1' then
4962
                                   next_state <= pulu_cc_state;
4963
                                 elsif ea(1) = '1' then
4964
                                   next_state <= pulu_acca_state;
4965
                                 elsif ea(2) = '1' then
4966
                                   next_state <= pulu_accb_state;
4967
                                 elsif ea(3) = '1' then
4968
                                   next_state <= pulu_dp_state;
4969
                                 elsif ea(4) = '1' then
4970
                                   next_state <= pulu_ixh_state;
4971
                                 elsif ea(5) = '1' then
4972
                                   next_state <= pulu_iyh_state;
4973
                                 elsif ea(6) = '1' then
4974
               next_state <= pulu_sph_state;
4975
                                 elsif ea(7) = '1' then
4976
               next_state <= pulu_pch_state;
4977
                                 else
4978
                                   next_state <= fetch_state;
4979
                                 end if;
4980
 
4981
                          when pulu_cc_state =>
4982
                                 -- increment up
4983
             left_ctrl  <= up_left;
4984
             right_ctrl <= one_right;
4985
             alu_ctrl   <= alu_add16;
4986
             up_ctrl    <= load_up;
4987
                                 -- read cc
4988
             cc_ctrl    <= pull_cc;
4989
             addr_ctrl  <= pullu_ad;
4990
                                 if ea(1) = '1' then
4991
                                   next_state <= pulu_acca_state;
4992
                                 elsif ea(2) = '1' then
4993
                                   next_state <= pulu_accb_state;
4994
                                 elsif ea(3) = '1' then
4995
                                   next_state <= pulu_dp_state;
4996
                                 elsif ea(4) = '1' then
4997
                                   next_state <= pulu_ixh_state;
4998
                                 elsif ea(5) = '1' then
4999
                                   next_state <= pulu_iyh_state;
5000
                                 elsif ea(6) = '1' then
5001
               next_state <= pulu_sph_state;
5002
                                 elsif ea(7) = '1' then
5003
               next_state <= pulu_pch_state;
5004
                                 else
5005
                                   next_state <= fetch_state;
5006
                                 end if;
5007
 
5008
                          when pulu_acca_state =>
5009
                                 -- increment up
5010
             left_ctrl  <= up_left;
5011
             right_ctrl <= one_right;
5012
             alu_ctrl   <= alu_add16;
5013
             up_ctrl    <= load_up;
5014
                                 -- read acca
5015
                                 acca_ctrl  <= pull_acca;
5016
             addr_ctrl  <= pullu_ad;
5017
                                 if ea(2) = '1' then
5018
                                   next_state <= pulu_accb_state;
5019
                                 elsif ea(3) = '1' then
5020
                                   next_state <= pulu_dp_state;
5021
                                 elsif ea(4) = '1' then
5022
                                   next_state <= pulu_ixh_state;
5023
                                 elsif ea(5) = '1' then
5024
                                   next_state <= pulu_iyh_state;
5025
                                 elsif ea(6) = '1' then
5026
               next_state <= pulu_sph_state;
5027
                                 elsif ea(7) = '1' then
5028
               next_state <= pulu_pch_state;
5029
                                 else
5030
                                   next_state <= fetch_state;
5031
                                 end if;
5032
 
5033
                          when pulu_accb_state =>
5034
                                 -- increment up
5035
             left_ctrl  <= up_left;
5036
             right_ctrl <= one_right;
5037
             alu_ctrl   <= alu_add16;
5038
             up_ctrl    <= load_up;
5039
                                 -- read accb
5040
                                 accb_ctrl  <= pull_accb;
5041
             addr_ctrl  <= pullu_ad;
5042
                                 if ea(3) = '1' then
5043
                                   next_state <= pulu_dp_state;
5044
                                 elsif ea(4) = '1' then
5045
                                   next_state <= pulu_ixh_state;
5046
                                 elsif ea(5) = '1' then
5047
                                   next_state <= pulu_iyh_state;
5048
                                 elsif ea(6) = '1' then
5049
               next_state <= pulu_sph_state;
5050
                                 elsif ea(7) = '1' then
5051
               next_state <= pulu_pch_state;
5052
                                 else
5053
                                   next_state <= fetch_state;
5054
                                 end if;
5055
 
5056
                          when pulu_dp_state =>
5057
                                 -- increment up
5058
             left_ctrl  <= up_left;
5059
             right_ctrl <= one_right;
5060
             alu_ctrl   <= alu_add16;
5061
             up_ctrl    <= load_up;
5062
                                 -- read dp
5063
                                 dp_ctrl    <= pull_dp;
5064
             addr_ctrl  <= pullu_ad;
5065
                                 if ea(4) = '1' then
5066
                                   next_state <= pulu_ixh_state;
5067
                                 elsif ea(5) = '1' then
5068
                                   next_state <= pulu_iyh_state;
5069
                                 elsif ea(6) = '1' then
5070
               next_state <= pulu_sph_state;
5071
                                 elsif ea(7) = '1' then
5072
               next_state <= pulu_pch_state;
5073
                                 else
5074
                                   next_state <= fetch_state;
5075
                                 end if;
5076
 
5077
                          when pulu_ixh_state =>
5078
             -- increment up
5079
             left_ctrl  <= up_left;
5080
             right_ctrl <= one_right;
5081
             alu_ctrl   <= alu_add16;
5082
             up_ctrl    <= load_up;
5083
                                 -- read ix hi
5084
                                 ix_ctrl    <= pull_hi_ix;
5085
             addr_ctrl  <= pullu_ad;
5086
             next_state <= pulu_ixl_state;
5087
 
5088
                          when pulu_ixl_state =>
5089
                                 -- increment up
5090
             left_ctrl  <= up_left;
5091
             right_ctrl <= one_right;
5092
             alu_ctrl   <= alu_add16;
5093
             up_ctrl    <= load_up;
5094
                                 -- read ix low
5095
                                 ix_ctrl    <= pull_lo_ix;
5096
             addr_ctrl  <= pullu_ad;
5097
                                 if ea(5) = '1' then
5098
                                   next_state <= pulu_iyh_state;
5099
                                 elsif ea(6) = '1' then
5100
               next_state <= pulu_sph_state;
5101
                                 elsif ea(7) = '1' then
5102
               next_state <= pulu_pch_state;
5103
                                 else
5104
                                   next_state <= fetch_state;
5105
                                 end if;
5106
 
5107
                          when pulu_iyh_state =>
5108
             -- increment up
5109
             left_ctrl  <= up_left;
5110
             right_ctrl <= one_right;
5111
             alu_ctrl   <= alu_add16;
5112
             up_ctrl    <= load_up;
5113
                                 -- read iy hi
5114
                                 iy_ctrl    <= pull_hi_iy;
5115
             addr_ctrl  <= pullu_ad;
5116
             next_state <= pulu_iyl_state;
5117
 
5118
                          when pulu_iyl_state =>
5119
             -- increment up
5120
             left_ctrl  <= up_left;
5121
             right_ctrl <= one_right;
5122
             alu_ctrl   <= alu_add16;
5123
             up_ctrl    <= load_up;
5124
                                 -- read iy low
5125
                                 iy_ctrl    <= pull_lo_iy;
5126
             addr_ctrl  <= pullu_ad;
5127
                                 if ea(6) = '1' then
5128
               next_state <= pulu_sph_state;
5129
                                 elsif ea(7) = '1' then
5130
               next_state <= pulu_pch_state;
5131
                                 else
5132
                                   next_state <= fetch_state;
5133
                                 end if;
5134
 
5135
                          when pulu_sph_state =>
5136
             -- increment up
5137
             left_ctrl  <= up_left;
5138
             right_ctrl <= one_right;
5139
             alu_ctrl   <= alu_add16;
5140
             up_ctrl    <= load_up;
5141
                                 -- read sp hi
5142
                                 sp_ctrl    <= pull_hi_sp;
5143
             addr_ctrl  <= pullu_ad;
5144
             next_state <= pulu_spl_state;
5145
 
5146
                          when pulu_spl_state =>
5147
                                 -- increment up
5148
             left_ctrl  <= up_left;
5149
             right_ctrl <= one_right;
5150
             alu_ctrl   <= alu_add16;
5151
             up_ctrl    <= load_up;
5152
                                 -- read sp low
5153
                                 sp_ctrl    <= pull_lo_sp;
5154
             addr_ctrl  <= pullu_ad;
5155
                                 if ea(7) = '1' then
5156
               next_state <= pulu_pch_state;
5157
                                 else
5158
                                   next_state <= fetch_state;
5159
                                 end if;
5160
 
5161
                          when pulu_pch_state =>
5162
             -- increment up
5163
             left_ctrl  <= up_left;
5164
             right_ctrl <= one_right;
5165
             alu_ctrl   <= alu_add16;
5166
             up_ctrl    <= load_up;
5167
                                 -- pull pc hi
5168
                                 pc_ctrl    <= pull_hi_pc;
5169
             addr_ctrl  <= pullu_ad;
5170
             next_state <= pulu_pcl_state;
5171
 
5172
                          when pulu_pcl_state =>
5173
                                 -- increment up
5174
             left_ctrl  <= up_left;
5175
             right_ctrl <= one_right;
5176
             alu_ctrl   <= alu_add16;
5177
             up_ctrl    <= load_up;
5178
                                 -- read pc low
5179
                                 pc_ctrl    <= pull_lo_pc;
5180
             addr_ctrl  <= pullu_ad;
5181
             next_state <= fetch_state;
5182
 
5183
                          --
5184
                          -- pop the Condition codes
5185
                          --
5186
                          when rti_cc_state =>
5187
                                 -- increment sp
5188
             left_ctrl  <= sp_left;
5189
             right_ctrl <= one_right;
5190
             alu_ctrl   <= alu_add16;
5191
             sp_ctrl    <= load_sp;
5192
                                 -- read cc
5193
             cc_ctrl    <= pull_cc;
5194
             addr_ctrl  <= pulls_ad;
5195
             next_state <= rti_entire_state;
5196
 
5197
                          --
5198
                          -- Added RTI cycle 11th July 2006 John Kent.
5199
                          -- test the "Entire" Flag
5200
                          -- that has just been popped off the stack
5201
                          --
5202
                          when rti_entire_state =>
5203
                                 --
5204
                                 -- The Entire flag must be recovered from the stack
5205
                                 -- before testing.
5206
                                 --
5207
                                 if cc(EBIT) = '1' then
5208
               next_state   <= rti_acca_state;
5209
                                 else
5210
               next_state   <= rti_pch_state;
5211
                                 end if;
5212
 
5213
                          when rti_acca_state =>
5214
                                 -- increment sp
5215
             left_ctrl  <= sp_left;
5216
             right_ctrl <= one_right;
5217
             alu_ctrl   <= alu_add16;
5218
             sp_ctrl    <= load_sp;
5219
                                 -- read acca
5220
                                 acca_ctrl  <= pull_acca;
5221
             addr_ctrl  <= pulls_ad;
5222
             next_state <= rti_accb_state;
5223
 
5224
                          when rti_accb_state =>
5225
                                 -- increment sp
5226
             left_ctrl  <= sp_left;
5227
             right_ctrl <= one_right;
5228
             alu_ctrl   <= alu_add16;
5229
             sp_ctrl    <= load_sp;
5230
                                 -- read accb
5231
                                 accb_ctrl  <= pull_accb;
5232
             addr_ctrl  <= pulls_ad;
5233
             next_state <= rti_dp_state;
5234
 
5235
                          when rti_dp_state =>
5236
                                 -- increment sp
5237
             left_ctrl  <= sp_left;
5238
             right_ctrl <= one_right;
5239
             alu_ctrl   <= alu_add16;
5240
             sp_ctrl    <= load_sp;
5241
                                 -- read dp
5242
                                 dp_ctrl    <= pull_dp;
5243
             addr_ctrl  <= pulls_ad;
5244
             next_state <= rti_ixh_state;
5245
 
5246
                          when rti_ixh_state =>
5247
                                 -- increment sp
5248
             left_ctrl  <= sp_left;
5249
             right_ctrl <= one_right;
5250
             alu_ctrl   <= alu_add16;
5251
             sp_ctrl    <= load_sp;
5252
                                 -- read ix hi
5253
                                 ix_ctrl    <= pull_hi_ix;
5254
             addr_ctrl  <= pulls_ad;
5255
             next_state <= rti_ixl_state;
5256
 
5257
                          when rti_ixl_state =>
5258
                                 -- increment sp
5259
             left_ctrl  <= sp_left;
5260
             right_ctrl <= one_right;
5261
             alu_ctrl   <= alu_add16;
5262
             sp_ctrl    <= load_sp;
5263
                                 -- read ix low
5264
                                 ix_ctrl    <= pull_lo_ix;
5265
             addr_ctrl  <= pulls_ad;
5266
             next_state <= rti_iyh_state;
5267
 
5268
                          when rti_iyh_state =>
5269
                                 -- increment sp
5270
             left_ctrl  <= sp_left;
5271
             right_ctrl <= one_right;
5272
             alu_ctrl   <= alu_add16;
5273
             sp_ctrl    <= load_sp;
5274
                                 -- read iy hi
5275
                                 iy_ctrl    <= pull_hi_iy;
5276
             addr_ctrl  <= pulls_ad;
5277
             next_state <= rti_iyl_state;
5278
 
5279
                          when rti_iyl_state =>
5280
                                 -- increment sp
5281
             left_ctrl  <= sp_left;
5282
             right_ctrl <= one_right;
5283
             alu_ctrl   <= alu_add16;
5284
             sp_ctrl    <= load_sp;
5285
                                 -- read iy low
5286
                                 iy_ctrl    <= pull_lo_iy;
5287
             addr_ctrl  <= pulls_ad;
5288
             next_state <= rti_uph_state;
5289
 
5290
 
5291
                          when rti_uph_state =>
5292
                                 -- increment sp
5293
             left_ctrl  <= sp_left;
5294
             right_ctrl <= one_right;
5295
             alu_ctrl   <= alu_add16;
5296
             sp_ctrl    <= load_sp;
5297
                                 -- read up hi
5298
                                 up_ctrl    <= pull_hi_up;
5299
             addr_ctrl  <= pulls_ad;
5300
             next_state <= rti_upl_state;
5301
 
5302
                          when rti_upl_state =>
5303
                                 -- increment sp
5304
             left_ctrl  <= sp_left;
5305
             right_ctrl <= one_right;
5306
             alu_ctrl   <= alu_add16;
5307
             sp_ctrl    <= load_sp;
5308
                                 -- read up low
5309
             up_ctrl    <= pull_lo_up;
5310
             addr_ctrl  <= pulls_ad;
5311
             next_state <= rti_pch_state;
5312
 
5313
                          when rti_pch_state =>
5314
                  -- increment sp
5315
             left_ctrl  <= sp_left;
5316
             right_ctrl <= one_right;
5317
             alu_ctrl   <= alu_add16;
5318
             sp_ctrl    <= load_sp;
5319
                                 -- pull pc hi
5320
                                 pc_ctrl    <= pull_hi_pc;
5321
             addr_ctrl  <= pulls_ad;
5322
             next_state <= rti_pcl_state;
5323
 
5324
                          when rti_pcl_state =>
5325
                                 -- increment sp
5326
             left_ctrl  <= sp_left;
5327
             right_ctrl <= one_right;
5328
             alu_ctrl   <= alu_add16;
5329
             sp_ctrl    <= load_sp;
5330
                  -- pull pc low
5331
                                 pc_ctrl    <= pull_lo_pc;
5332
             addr_ctrl  <= pulls_ad;
5333
             next_state <= fetch_state;
5334
 
5335
                          --
5336
                          -- here on IRQ or NMI interrupt
5337
                          -- pre decrement the sp
5338
                          -- Idle bus cycle
5339
                          --
5340
                          when int_nmiirq_state =>
5341
             -- decrement sp
5342
             left_ctrl  <= sp_left;
5343
             right_ctrl <= one_right;
5344
             alu_ctrl   <= alu_sub16;
5345
             sp_ctrl    <= load_sp;
5346
             next_state <= int_entire_state;
5347
 
5348
                          --
5349
                          -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
5350
                          -- clear Entire Flag on FIRQ
5351
                          -- before stacking all registers
5352
                          --
5353
                          when int_entire_state =>
5354
             -- set entire flag
5355
             alu_ctrl   <= alu_see;
5356
             cc_ctrl    <= load_cc;
5357
             next_state <= int_pcl_state;
5358
 
5359
                          --
5360
                          -- here on FIRQ interrupt
5361
                          -- pre decrement the sp
5362
                          -- Idle bus cycle
5363
                          --
5364
                          when int_firq_state =>
5365
             -- decrement sp
5366
             left_ctrl  <= sp_left;
5367
             right_ctrl <= one_right;
5368
             alu_ctrl   <= alu_sub16;
5369
             sp_ctrl    <= load_sp;
5370
             next_state <= int_fast_state;
5371
                          --
5372
                          -- clear Entire Flag on FIRQ
5373
                          -- before stacking all registers
5374
                          --
5375
                          when int_fast_state =>
5376
             -- clear entire flag
5377
             alu_ctrl   <= alu_cle;
5378
             cc_ctrl    <= load_cc;
5379
             next_state <= int_pcl_state;
5380
 
5381
                          when int_pcl_state =>
5382
             -- decrement sp
5383
             left_ctrl  <= sp_left;
5384
             right_ctrl <= one_right;
5385
             alu_ctrl   <= alu_sub16;
5386
             sp_ctrl    <= load_sp;
5387
                                 -- write pc low
5388
             addr_ctrl  <= pushs_ad;
5389
                            dout_ctrl  <= pc_lo_dout;
5390
             next_state <= int_pch_state;
5391
 
5392
                          when int_pch_state =>
5393
             -- decrement sp
5394
             left_ctrl  <= sp_left;
5395
             right_ctrl <= one_right;
5396
             alu_ctrl   <= alu_sub16;
5397
             sp_ctrl    <= load_sp;
5398
                                 -- write pc hi
5399
             addr_ctrl  <= pushs_ad;
5400
                            dout_ctrl  <= pc_hi_dout;
5401
                                 if cc(EBIT) = '1' then
5402
               next_state   <= int_upl_state;
5403
                                 else
5404
               next_state   <= int_cc_state;
5405
                                 end if;
5406
 
5407
                          when int_upl_state =>
5408
             -- decrement sp
5409
             left_ctrl  <= sp_left;
5410
             right_ctrl <= one_right;
5411
             alu_ctrl   <= alu_sub16;
5412
             sp_ctrl    <= load_sp;
5413
                                 -- write up low
5414
             addr_ctrl  <= pushs_ad;
5415
                            dout_ctrl  <= up_lo_dout;
5416
             next_state <= int_uph_state;
5417
 
5418
                          when int_uph_state =>
5419
             -- decrement sp
5420
             left_ctrl  <= sp_left;
5421
             right_ctrl <= one_right;
5422
             alu_ctrl   <= alu_sub16;
5423
             sp_ctrl    <= load_sp;
5424
                                 -- write ix hi
5425
             addr_ctrl  <= pushs_ad;
5426
                            dout_ctrl  <= up_hi_dout;
5427
             next_state <= int_iyl_state;
5428
 
5429
                          when int_iyl_state =>
5430
             -- decrement sp
5431
             left_ctrl  <= sp_left;
5432
             right_ctrl <= one_right;
5433
             alu_ctrl   <= alu_sub16;
5434
             sp_ctrl    <= load_sp;
5435
                                 -- write ix low
5436
             addr_ctrl  <= pushs_ad;
5437
                            dout_ctrl  <= iy_lo_dout;
5438
             next_state <= int_iyh_state;
5439
 
5440
                          when int_iyh_state =>
5441
             -- decrement sp
5442
             left_ctrl  <= sp_left;
5443
             right_ctrl <= one_right;
5444
             alu_ctrl   <= alu_sub16;
5445
             sp_ctrl    <= load_sp;
5446
                                 -- write ix hi
5447
             addr_ctrl  <= pushs_ad;
5448
                            dout_ctrl  <= iy_hi_dout;
5449
             next_state <= int_ixl_state;
5450
 
5451
                          when int_ixl_state =>
5452
             -- decrement sp
5453
             left_ctrl  <= sp_left;
5454
             right_ctrl <= one_right;
5455
             alu_ctrl   <= alu_sub16;
5456
             sp_ctrl    <= load_sp;
5457
                                 -- write ix low
5458
             addr_ctrl  <= pushs_ad;
5459
                            dout_ctrl  <= ix_lo_dout;
5460
             next_state <= int_ixh_state;
5461
 
5462
                          when int_ixh_state =>
5463
             -- decrement sp
5464
             left_ctrl  <= sp_left;
5465
             right_ctrl <= one_right;
5466
             alu_ctrl   <= alu_sub16;
5467
             sp_ctrl    <= load_sp;
5468
                                 -- write ix hi
5469
             addr_ctrl  <= pushs_ad;
5470
                            dout_ctrl  <= ix_hi_dout;
5471
             next_state <= int_dp_state;
5472
 
5473
                          when int_dp_state =>
5474
             -- decrement sp
5475
             left_ctrl  <= sp_left;
5476
             right_ctrl <= one_right;
5477
             alu_ctrl   <= alu_sub16;
5478
             sp_ctrl    <= load_sp;
5479
                                 -- write accb
5480
             addr_ctrl  <= pushs_ad;
5481
                            dout_ctrl  <= dp_dout;
5482
             next_state <= int_accb_state;
5483
 
5484
                          when int_accb_state =>
5485
             -- decrement sp
5486
             left_ctrl  <= sp_left;
5487
             right_ctrl <= one_right;
5488
             alu_ctrl   <= alu_sub16;
5489
             sp_ctrl    <= load_sp;
5490
                                 -- write accb
5491
             addr_ctrl  <= pushs_ad;
5492
                            dout_ctrl  <= accb_dout;
5493
             next_state <= int_acca_state;
5494
 
5495
                          when int_acca_state =>
5496
             -- decrement sp
5497
             left_ctrl  <= sp_left;
5498
             right_ctrl <= one_right;
5499
             alu_ctrl   <= alu_sub16;
5500
             sp_ctrl    <= load_sp;
5501
                                 -- write acca
5502
             addr_ctrl  <= pushs_ad;
5503
                            dout_ctrl  <= acca_dout;
5504
             next_state <= int_cc_state;
5505
 
5506
                          when int_cc_state =>
5507
                                 -- write cc
5508
             addr_ctrl  <= pushs_ad;
5509
                            dout_ctrl  <= cc_dout;
5510
                                 case iv is
5511
                                 when NMI_VEC =>
5512
                              next_state <= int_maskif_state;
5513
                                 when SWI_VEC =>
5514
                              next_state <= int_maskif_state;
5515
                                 when FIRQ_VEC =>
5516
                              next_state <= int_maskif_state;
5517
                                 when IRQ_VEC =>
5518
                              next_state <= int_maski_state;
5519
                                 when SWI2_VEC =>
5520
                    next_state <= vect_hi_state;
5521
                                 when SWI3_VEC =>
5522
                    next_state <= vect_hi_state;
5523
                                 when others =>
5524
                                   if op_code = "00111100" then -- CWAI
5525
                                          next_state <= int_cwai_state;
5526
                                        else
5527
                      next_state <= rti_cc_state; -- spurious interrupt, do a RTI
5528
                                        end if;
5529
                                 end case;
5530
 
5531
                          --
5532
                          -- wait here for an inteerupt
5533
                          --
5534
                          when int_cwai_state =>
5535
                            if (nmi_req = '1') and (nmi_ack='0') then
5536
                                        iv_ctrl    <= nmi_iv;
5537
                                   nmi_ctrl   <= set_nmi;
5538
                              next_state <= int_maskif_state;
5539
                            else
5540
                                   --
5541
                                        -- nmi request is not cleared until nmi input goes low
5542
                                        --
5543
                                   if (nmi_req = '0') and (nmi_ack='1') then
5544
                                     nmi_ctrl <= reset_nmi;
5545
                                        end if;
5546
                                        --
5547
                                        -- FIRQ is level sensitive
5548
                                        --
5549
               if (firq = '1') and (cc(FBIT) = '0') then
5550
                                          iv_ctrl    <= firq_iv;
5551
                                next_state <= int_maskif_state;
5552
                                        --
5553
                                        -- IRQ is level sensitive
5554
                                        --
5555
                                   elsif (irq = '1') and (cc(IBIT) = '0') then
5556
                                          iv_ctrl    <= irq_iv;
5557
                                next_state <= int_maski_state;
5558
               else
5559
                 iv_ctrl    <= reset_iv;
5560
                      next_state <= int_cwai_state;
5561
                                        end if;
5562
                                 end if;
5563
 
5564
                          when int_maski_state =>
5565
                                 alu_ctrl   <= alu_sei;
5566
                                 cc_ctrl    <= load_cc;
5567
             next_state <= vect_hi_state;
5568
 
5569
                          when int_maskif_state =>
5570
                            alu_ctrl   <= alu_seif;
5571
                                 cc_ctrl    <= load_cc;
5572
             next_state <= vect_hi_state;
5573
 
5574
                          --
5575
                          -- According to the 6809 programming manual:
5576
                          -- If an interrupt is received and is masked 
5577
                          -- or lasts for less than three cycles, the PC 
5578
                          -- will advance to the next instruction.
5579
                          -- If an interrupt is unmasked and lasts
5580
                          -- for more than three cycles, an interrupt
5581
                          -- will be generated.
5582
                          -- Note that I don't wait 3 clock cycles.
5583
                          -- John Kent 11th July 2006
5584
                          --
5585
                          when sync_state =>
5586
                            if (nmi_req = '1') and (nmi_ack='0') then
5587
                                        iv_ctrl    <= nmi_iv;
5588
                                   nmi_ctrl   <= set_nmi;
5589
               next_state <= int_nmiirq_state;
5590
                            else
5591
                                   --
5592
                                        -- nmi request is not cleared until nmi input goes low
5593
                                        --
5594
                                   if (nmi_req = '0') and (nmi_ack='1') then
5595
                                          iv_ctrl  <= reset_iv;
5596
                                     nmi_ctrl <= reset_nmi;
5597
                                        end if;
5598
                                        --
5599
                                        -- FIRQ is level sensitive
5600
                                        --
5601
               if (firq = '1') then
5602
                                          if (cc(FBIT) = '0') then
5603
                   iv_ctrl    <= firq_iv;
5604
                   next_state <= int_firq_state;
5605
                                          else
5606
                   iv_ctrl    <= reset_iv;
5607
                                  next_state <= fetch_state;
5608
                                          end if;
5609
                                        --
5610
                                        -- IRQ is level sensitive
5611
                                        --
5612
                                   elsif (irq = '1') then
5613
                                          if (cc(IBIT) = '0') then
5614
                   iv_ctrl    <= irq_iv;
5615
                   next_state <= int_nmiirq_state;
5616
                                          else
5617
                   iv_ctrl    <= reset_iv;
5618
                                  next_state <= fetch_state;
5619
                                          end if;
5620
               else
5621
                 iv_ctrl    <= reset_iv;
5622
                      next_state <= sync_state;
5623
                                        end if;
5624
                                 end if;
5625
 
5626
 
5627
                          when halt_state =>
5628
                                 if halt = '1' then
5629
               next_state   <= halt_state;
5630
                                 else
5631
                                   next_state   <= fetch_state;
5632
                                 end if;
5633
 
5634
                          when others => -- halt on undefine states
5635
                            next_state <= error_state;
5636
                  end case;
5637
end process;
5638
 
5639
end rtl;
5640
 

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