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[/] [System09/] [trunk/] [rtl/] [VHDL/] [vdu8_mono.vhd] - Blame information for rev 99

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Line No. Rev Author Line
1 99 davidgb
--===========================================================================--
2
--                                                                           --
3
--  vdu8_mono.vhd - Synthesizable Monochrome Video Display Unit for System09 --
4
--                                                                           --
5
--===========================================================================--
6 19 dilbert57
--
7 99 davidgb
--  File name      : vdu8.vhd
8 19 dilbert57
--
9 99 davidgb
--  Purpose        : Implements a text based Monochrome Video Display Unit for System09
10
--                   Supports 2KByte Text buffer.
11
--                   Displays 80 characters across by 25 character rows
12
--                   Characters are 8 pixels across x 16 lines down.
13
--                   Uses Generic arguments for setting the video synchronization timing.
14
--                  
15
--  Dependencies   : ieee.Std_Logic_1164
16
--                   ieee.std_logic_unsigned
17
--                   ieee.std_logic_arith
18
--                   ieee.numeric_std
19 19 dilbert57
--
20 99 davidgb
--  Uses           : ram_2k (ram2k_b16.vhd)             2KByte Character Buffer
21
--                   char_rom (char_rom2k_b16.vhd)      2KByte Character Generator 
22
--
23
--  Author         : John E. Kent
24
--
25
--  Email          : dilbert57@opencores.org      
26
--
27
--  Web            : http://opencores.org/project,system09
28
--
29
--  Description    : Display Timing:
30
--                       800 pixels / line
31
--                       446 lines / frame
32
--                       None interlaced
33
--                       25MHz pixel clock implies 
34
--                       31.25 KHz line rate
35
--                       70.067 Hz frame rate   
36
--                       Timing settable by generics.
37
--
38
--                   Display Size:
39
--                       80 characters across
40
--                       25 characters down.
41
--
42
--                   Character Size:
43
--                        8 horizontal pixels across
44
--                       16 vertical scan lines down (2 scan lines/row)
45
--
46
--                   Registers:
47
--                   Base + 0 ASCII character register
48
--                            Writing to this register writes an 8 bit byte 
49
--                            into the text buffer at the specified cursor position
50
--                            Text Mode: ASCII Character (0 to 127)
51
--                            Chunky Graphics Mode: B0 B1 (0 to 255)
52
--                                                  B2 B3
53
--                                                  B4 B5
54
--                                                  B6 B7
55
--                   Base + 1 Reserved Attibute bit (0 to 255)
56
--                   Base + 2 Cursor Horizontal Position (0 to 79)
57
--                   Base + 3 Cusror Vertical Position (0 to 24)
58
--                   Base + 4 Vertical Scroll Offset (0 to 24)
59
--                            Scrolls the display up by the specified number of character rows
60
--  Video Timing :
61
--
62
--  Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
63
--  /--------------------------\_____________/---------------\______________/
64
--      640 Pixels Display       16 Pixel FP    96 Pixel HS     48 Pixel BP
65
--    
66
--      VGA_CLK_FREQ           : integer := 25000000; -- HZ
67
--           VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
68
--           VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
69
--           VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
70
--           VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS 0.32us
71
--           VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
72
--
73
--  Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency  
74
--  /---------------------------\____________/---------------\______________/
75
--      400 Line Display          10 Line FP     2 Line VS      34 Line BP
76
--
77
--           VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
78
--           VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
79
--           VGA_VER_BACK_PORCH     : integer := 34; -- LINES 1.088ms
80
--           VGA_LIN_PER_CHAR       : integer := 16; -- LINES 0.512ms
81
--           VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
82
--
83
--  Copyright (C) 2003 - 2010 John Kent
84
--
85
--  This program is free software: you can redistribute it and/or modify
86
--  it under the terms of the GNU General Public License as published by
87
--  the Free Software Foundation, either version 3 of the License, or
88
--  (at your option) any later version.
89
--
90
--  This program is distributed in the hope that it will be useful,
91
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
92
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
93
--  GNU General Public License for more details.
94
--
95
--  You should have received a copy of the GNU General Public License
96
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
97
--
98
--===========================================================================--
99
--                                                                           --
100
--                              Revision  History                            --
101
--                                                                           --
102
--===========================================================================--
103
--
104
-- Version Author      Date        Changes
105 19 dilbert57
--
106 99 davidgb
-- 0.1     John Kent   2004-09-03  Initial release
107
--
108
-- 0.2     Bert Cuzeau 2007-01-16  Modified by for compliance and code cleanliness
109
--                                 The effort is not over.
110
--                                 There are still signal initialized, which is BAD.
111
--
112
-- 0.3     John Kent   2007-02-03  Changed vdu_clk to be derived externally from cpu_clk.
113
--                                 Removed attibute memory for monochrome character only version.
114
--                                 This was done to reduce Bock RAM allocation
115
--
116
-- 0.4     John Kent   2007-07-01  Added generics for VGA timing specification
117
--
118
-- 0.5     John Kent   2010-07-03  Added GPL notice. 
119
--                                 Updated description
120 19 dilbert57
--
121
 
122
Library IEEE;
123
  use IEEE.std_logic_1164.all;
124
  use IEEE.numeric_std.all;
125
library unisim;
126
  use unisim.vcomponents.all;
127
 
128
Entity vdu8_mono is
129
  generic(
130 99 davidgb
        VGA_CLK_FREQ           : integer := 25000000; -- HZ
131
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
132
             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
133
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
134
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
135
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
136
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
137
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
138
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
139
             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
140
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
141 19 dilbert57
  );
142
  port(
143
    -- control register interface
144
    vdu_clk      : in  std_logic;       -- 12.5/25 MHz CPU Clock
145
    vdu_rst      : in  std_logic;
146
    vdu_cs       : in  std_logic;
147
    vdu_rw       : in  std_logic;
148
    vdu_addr     : in  std_logic_vector(2 downto 0);
149
    vdu_data_in  : in  std_logic_vector(7 downto 0);
150
    vdu_data_out : out std_logic_vector(7 downto 0);
151
 
152
    -- vga port connections
153
    vga_clk      : in  std_logic;       -- 25MHz clock
154
    vga_red_o    : out std_logic;
155
    vga_green_o  : out std_logic;
156
    vga_blue_o   : out std_logic;
157
    vga_hsync_o  : out std_logic;
158
    vga_vsync_o  : out std_logic
159
    );
160
end vdu8_mono;
161
 
162
Architecture RTL of vdu8_mono is
163
 
164
  --
165
  -- Synchronisation constants
166
  --
167
  -- Displayed Characters per row
168
  constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
169
  -- Last horizontal pixel displayed
170 99 davidgb
  constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS) - 1;
171 19 dilbert57
  -- Start of horizontal synch pulse
172 99 davidgb
  constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
173 19 dilbert57
  -- End of Horizontal Synch pulse
174
  constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
175
  -- Last pixel in scan line
176 99 davidgb
  constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
177 19 dilbert57
 
178
  -- Displayed Characters per Column
179
  constant VER_DISP_CHR : integer := VGA_VER_CHARS;
180
  -- last row displayed
181 99 davidgb
  constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_VER_CHAR_LINES) - 1;
182 19 dilbert57
  -- start of vertical synch pulse
183 99 davidgb
  constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
184 19 dilbert57
  -- end of vertical synch pulse
185
  constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
186
  -- Last scan row in the frame
187 99 davidgb
  constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
188 19 dilbert57
 
189
  signal horiz_sync    : std_logic := '1';
190
  signal vert_sync     : std_logic := '1';
191
  signal cursor_on_v   : std_logic;
192
  signal cursor_on_h   : std_logic;
193
  signal video_on_v    : std_logic := '0';
194
  signal video_on_h    : std_logic := '0';
195
  signal h_count       : std_logic_vector(9 downto 0) := (others=>'0');
196
  signal v_count       : std_logic_vector(8 downto 0) := (others=>'0');  -- 0 to VER_SCAN_END
197
  signal blink_count   : std_logic_vector(22 downto 0):= (others=>'1');
198
  --
199
  -- Character generator ROM
200
  --
201
  signal char_addr     : std_logic_vector(10 downto 0);
202
  signal char_data_out : std_logic_vector(7 downto 0);
203
 
204
  --
205
  -- Control Registers
206
  --
207
  signal reg_character : std_logic_vector(7 downto 0);
208
  signal reg_colour    : std_logic_vector(7 downto 0);
209
  signal reg_hcursor   : std_logic_vector(6 downto 0);   -- 80 columns
210
  signal reg_vcursor   : std_logic_vector(4 downto 0);   -- 25 rows
211
  signal reg_voffset   : std_logic_vector(4 downto 0);   -- 25 rows
212
  --
213
  -- Video Shift register
214
  --
215
  signal vga_shift     : std_logic_vector(7 downto 0);
216
  signal cursor_on     : std_logic;
217
  signal cursor_on1    : std_logic;
218
  signal video_on      : std_logic := '0';
219
  signal video_on1     : std_logic := '0';
220
  signal video_on2     : std_logic := '0';
221
  --
222
  -- vga character ram access bus
223
  --
224
  signal col_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
225
  signal row_addr      : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 -1)
226
  signal col1_addr     : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
227
  signal row1_addr     : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 - 1)
228
  signal hor_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
229
  signal ver_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 124
230
  signal vga0_cs       : std_logic;
231
  signal vga0_rw       : std_logic;
232
  signal vga1_cs       : std_logic;
233
  signal vga1_rw       : std_logic;
234
  signal vga2_cs       : std_logic;
235
  signal vga2_rw       : std_logic;
236
  signal vga_cs        : std_logic;
237
  signal vga_rw        : std_logic;
238
  signal vga_addr      : std_logic_vector(10 downto 0) := (others=>'0');  -- 2K byte character buffer
239
  signal vga_data_out  : std_logic_vector(7 downto 0);
240
  --
241
  -- Character write handshake signals
242
  --
243
  signal req_write     : std_logic;     -- request character write
244
  signal ack_write     : std_logic;
245
 
246
  --
247
  -- Block Ram Character gen
248
  --
249
  component char_rom
250
    port (
251
      clk   : in  std_logic;
252
      rst   : in  std_logic;
253
      cs    : in  std_logic;
254
      rw    : in  std_logic;
255
      addr  : in  std_logic_vector (10 downto 0);
256 99 davidgb
      data_in : in std_logic_vector (7 downto 0);
257
      data_out : out std_logic_vector (7 downto 0)
258 19 dilbert57
      );
259
  end component;
260
 
261
  component ram_2k
262
    port (
263
      clk   : in  std_logic;
264
      rst   : in  std_logic;
265
      cs    : in  std_logic;
266
      rw    : in  std_logic;
267
      addr  : in  std_logic_vector (10 downto 0);
268 99 davidgb
      data_in : in  std_logic_vector (7 downto 0);
269
      data_out : out std_logic_vector (7 downto 0)
270 19 dilbert57
      );
271
  end component;
272
 
273
begin
274
 
275
--
276
-- instantiate Character generator ROM
277
--
278
vdu_char_rom : char_rom port map(
279
    clk   => vga_clk,
280
         rst   => vdu_rst,
281
         cs    => '1',
282
         rw    => '1',
283
    addr  => char_addr,
284 99 davidgb
    data_in  => "00000000",
285
    data_out => char_data_out
286 19 dilbert57
    );
287
 
288
--
289
-- Character buffer RAM
290
--
291
char_buff_ram : ram_2k port map(
292
    clk   => vga_clk,
293
    rst   => vdu_rst,
294
    cs    => vga_cs,
295
    rw    => vga_rw,
296
    addr  => vga_addr,
297 99 davidgb
    data_in  => reg_character,
298
    data_out => vga_data_out
299 19 dilbert57
    );
300
 
301
--
302
-- CPU Write interface
303
--
304
  vga_cpu_write : process(vdu_clk, vdu_rst)
305
  begin
306
    if vdu_rst = '1' then
307
      reg_character <= "00000000";
308
      reg_colour    <= "00000111";
309
      reg_hcursor   <= "0000000";
310
      reg_vcursor   <= "00000";
311
      reg_voffset   <= "00000";
312
      req_write     <= '0';
313
 
314
    elsif vdu_clk'event and vdu_clk = '0' then
315
      if (vdu_cs = '1') and (vdu_rw = '0') then
316
        case vdu_addr is
317
          when "000" =>
318
            reg_character <= vdu_data_in;
319
            req_write     <= '1';
320
          when "001" =>
321
            reg_colour    <= vdu_data_in;
322
          when "010" =>
323
            reg_hcursor   <= vdu_data_in(6 downto 0);
324
          when "011" =>
325
            reg_vcursor   <= vdu_data_in(4 downto 0);
326
          when others =>
327
            reg_voffset   <= vdu_data_in(4 downto 0);
328
        end case;
329
      else
330
 
331
        if (req_write = '1') and (ack_write = '1') then
332
          req_write <= '0';
333
        else
334
          req_write <= req_write;
335
        end if;
336
 
337
      end if;
338
    end if;
339
  end process;
340
--
341
-- CPU Read interface
342
--
343
  vga_cpu_read : process(vdu_addr, vdu_cs,
344
                          reg_character, reg_colour,
345
                          reg_hcursor, reg_vcursor, reg_voffset)
346
  begin
347
    case vdu_addr is
348
      when "000" =>
349
        vdu_data_out <= reg_character;
350
      when "001" =>
351
        vdu_data_out <= reg_colour;
352
      when "010" =>
353
        vdu_data_out <= "0" & reg_hcursor;
354
      when "011" =>
355
        vdu_data_out <= "000" & reg_vcursor;
356
      when others =>
357
        vdu_data_out <= "000" & reg_voffset;
358
    end case;
359
  end process;
360
 
361
--
362
-- Video memory access
363
--
364
  vga_addr_proc : process(vga_clk, vdu_rst)
365
  begin
366
 
367
    if vdu_rst = '1' then
368
      vga0_cs   <= '0';
369
      vga0_rw   <= '1';
370
      row_addr  <= "000000";
371
      col_addr  <= "0000000";
372
      --
373
      vga1_cs   <= '0';
374
      vga1_rw   <= '1';
375
      row1_addr <= "000000";
376
      col1_addr <= "0000000";
377
      --
378
      vga2_cs   <= '0';
379
      vga2_rw   <= '1';
380
      ver_addr  <= "0000000";
381
      hor_addr  <= "0000000";
382
      --
383
      vga_cs    <= '0';
384
      vga_rw    <= '1';
385
      vga_addr  <= "00000000000";
386
 
387
    elsif vga_clk'event and vga_clk = '0' then
388
      --
389
      -- on h_count = 0 initiate character write.
390
      -- all other cycles are reads.
391
      --
392
      case h_count(2 downto 0) is
393
        when "000" =>                   -- pipeline character write
394
          vga0_cs  <= req_write;
395
          vga0_rw  <= '0';
396
          col_addr <= reg_hcursor(6 downto 0);
397
          row_addr <= unsigned("0" & reg_vcursor(4 downto 0)) + unsigned("0" & reg_voffset(4 downto 0));
398
        when others =>                  -- other 6 cycles free
399
          vga0_cs  <= '1';
400
          vga0_rw  <= '1';
401
          col_addr <= h_count(9 downto 3);
402
          row_addr <= unsigned("0" & v_count(8 downto 4)) + unsigned("0" & reg_voffset(4 downto 0));
403
      end case;
404
      --
405
      -- on vga_clk + 1 round off row address
406
      --
407
      vga1_cs <= vga0_cs;
408
      vga1_rw <= vga0_rw;
409
      if row_addr < VER_DISP_CHR then
410
        row1_addr <= row_addr;
411
      else
412
        row1_addr <= row_addr - VER_DISP_CHR;
413
      end if;
414
      col1_addr <= col_addr;
415
      --
416
      -- on vga_clk + 2 calculate vertical address
417
      --
418
      vga2_cs   <= vga1_cs;
419
      vga2_rw   <= vga1_rw;
420
      ver_addr  <= std_logic_vector(unsigned("00" & row1_addr(4 downto 0)) + unsigned(row1_addr(4 downto 0) & "00"));
421
      hor_addr  <= col1_addr;
422
      --
423
      -- on vga_clk + 3 calculate memory address
424
      --
425
      vga_cs    <= vga2_cs;
426
      vga_rw    <= vga2_rw;
427
      vga_addr  <= std_logic_vector(unsigned("0000" & hor_addr) + unsigned(ver_addr & "0000"));
428
    end if;
429
  end process;
430
--
431
-- Video shift register
432
--
433
  vga_shift_proc : process( vga_clk, vdu_rst)
434
  begin
435
    if vdu_rst = '1' then
436
      ack_write     <= '0';
437
      video_on2     <= '0';
438
      video_on      <= '0';
439
      cursor_on     <= '0';
440
      vga_shift     <= "00000000";
441
      vga_red_o     <= '0';
442
      vga_green_o   <= '0';
443
      vga_blue_o    <= '0';
444
      -- Put all video signals through DFFs to elminate any delays that cause a blurry image
445
 
446
    elsif vga_clk'event and vga_clk = '0' then
447
      -- Character Data valid on 1 count
448
      if h_count(2 downto 0) = "000" then
449
        if (req_write = '1') and (ack_write = '0') then
450
          ack_write <= '1';
451
        elsif (req_write = '0') and (ack_write = '1') then
452
          ack_write <= '0';
453
        else
454
          ack_write <= ack_write;
455
        end if;
456
        video_on2     <= video_on1;
457
        video_on      <= video_on2;
458
        cursor_on     <= cursor_on1 and blink_count(22);
459
        vga_shift     <= char_data_out;
460
      else
461
        vga_shift     <= vga_shift(6 downto 0) & '0';
462
      end if;
463
 
464
      --
465
      -- Colour mask is
466
      --  7  6  5  4  3  2  1  0
467
      --  X BG BB BR  X FG FB FR
468
      --
469
      if vga_shift(7) = (not cursor_on) then
470
        vga_red_o   <= video_on;
471
        vga_green_o <= video_on;
472
        vga_blue_o  <= video_on;
473
      else
474
        vga_red_o   <= '0';
475
        vga_green_o <= '0';
476
        vga_blue_o  <= '0';
477
      end if;
478
    end if;
479
  end process;
480
 
481
 
482
--
483
-- Sync generator & timing process
484
-- Generate Horizontal and Vertical Timing Signals for Video Signal
485
--
486
  vga_sync : process(vga_clk)
487
  begin
488
    if vga_clk'event and vga_clk = '0' then
489
      --
490
      -- H_count counts pixels (640 + extra time for sync signals)
491
      --
492
      --  Horiz_sync  -----------------------------__________--------
493
      --  H_count       0                640      659       755    799
494
      --
495
      if unsigned(h_count) = HOR_SCAN_END then
496
        h_count <= (others=>'0');
497
      else
498
        h_count <= std_logic_vector(unsigned(h_count) + 1);
499
      end if;
500
--
501
-- Generate Horizontal Sync Signal using H_count
502
--
503
      if unsigned(h_count) = HOR_SYNC_BEG then
504
        horiz_sync <= '0';
505
      elsif unsigned(h_count) = HOR_SYNC_END then
506
        horiz_sync <= '1';
507
      else
508
        horiz_sync <= horiz_sync;
509
      end if;
510
--
511
-- V_count counts rows of pixels
512
-- 400 lines + extra time for sync signals
513
-- 25 rows * 16 scan lines
514
--
515
--  Vert_sync      ---------------------------------_______------------
516
--  V_count         0                       400    413     414        444
517
--
518
      if (unsigned(v_count) = VER_SCAN_END) and (unsigned(h_count) = HOR_SCAN_END) then
519
        v_count <= "000000000";
520
      elsif unsigned(h_count) = HOR_SYNC_END then
521
        v_count <= std_logic_vector(unsigned(v_count) + 1);
522
      end if;
523
--
524
-- Generate Vertical Sync Signal using V_count
525
--
526
      if unsigned(v_count) = VER_SYNC_BEG then
527
        vert_sync <= '0';
528
      elsif unsigned(v_count) = VER_SYNC_END then
529
        vert_sync <= '1';
530
      else
531
        vert_sync <= vert_sync;
532
      end if;
533
 
534
-- Generate Video on Screen Signals for Pixel Data
535
      if unsigned(h_count) = HOR_SCAN_END then
536
        video_on_h <= '1';
537
      elsif unsigned(h_count) = HOR_DISP_END then
538
        video_on_h <= '0';
539
      else
540
        video_on_h <= video_on_h;
541
      end if;
542
 
543
      if unsigned(v_count) = VER_SCAN_END then
544
        video_on_v <= '1';
545
      elsif unsigned(v_count) = VER_DISP_END then
546
        video_on_v <= '0';
547
      else
548
        video_on_v <= video_on_v;
549
      end if;
550
 
551
 
552
      if h_count(9 downto 3) = reg_hcursor(6 downto 0) then
553
        cursor_on_h <= '1';
554
      else
555
        cursor_on_h <= '0';
556
      end if;
557
 
558
      if (v_count(8 downto 4) = reg_vcursor(4 downto 0)) then
559
        cursor_on_v <= '1';
560
      else
561
        cursor_on_v <= '0';
562
      end if;
563
 
564
      -- cursor_on is only active when on selected character
565
      blink_count <= std_logic_vector(unsigned(blink_count) + 1);
566
    end if;
567
 
568
  end process;
569
 
570
  -- video_on is high only when RGB data is displayed
571
  vga_hsync_o <= horiz_sync;
572
  vga_vsync_o <= vert_sync;
573
  video_on1   <= video_on_H and video_on_V;
574
  cursor_on1  <= cursor_on_h and cursor_on_v;
575
 
576
--
577
-- Here to look up character ROM
578
-- This will take one clock cycle
579
-- and should be performed on h_count = "111"
580
--
581
  char_addr(10 downto 4) <= vga_data_out(6 downto 0);
582
  char_addr(3 downto 0)  <= v_count(3 downto 0);
583
 
584
end RTL;

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