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[/] [System09/] [trunk/] [rtl/] [XilinxRAMs/] [block_spram.vhd] - Blame information for rev 203

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1 203 davidgb
--===========================================================================--
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--                                                                           --
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--            Generic Single-Port Block RAM for Xilinx                       --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : block_spram.vhd
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--
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--  Entity name    : block_spram
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--
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--  Purpose        : Implements generic block memory of arbitrary size
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--
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.std_logic_arith
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--
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--  Uses           : infers family-specific block memory as required
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--
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--  Author         : David Burnette
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--
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--  Email          :       
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--
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--  Web            : 
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--
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--  Description    : Generic Block RAM 
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--
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version Date        Author     Changes
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--
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-- 0.1     2021-02-19  David Burnette  Initial verison 
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--
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library IEEE;
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  use IEEE.STD_LOGIC_1164.ALL;
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  use IEEE.Numeric_Std.ALL;
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library unisim;
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        use unisim.vcomponents.all;
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entity block_spram is
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  generic (
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    dwidth : integer := 8;     -- parameterized data width
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         awidth : integer := 16     -- parameterized address width
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         );
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  port (
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    clk         : in std_logic;
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         cs          : in std_logic; -- chip-select/enable
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         addr        : in std_logic_vector(awidth-1 downto 0);
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         rw          : in std_logic;
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         data_in     : in std_logic_vector(dwidth-1 downto 0);
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         data_out    : out std_logic_vector(dwidth-1 downto 0)
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         );
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end block_spram;
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architecture rtl of block_spram is
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  type ram_t is array ( (2**awidth)-1 downto 0) of std_logic_vector(dwidth-1 downto 0);
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  signal ram_data : ram_t := (others => (others => '0')); -- ram storage, initialized to zero
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  attribute ram_style : string;
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  attribute ram_style of ram_data : signal is "BLOCK"; -- direct ISE/Vivado to target block memory
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  signal we : std_logic;
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begin
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  we <= not rw;
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  process ( clk )
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  begin
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    if (rising_edge(clk)) then
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           if (cs = '1') then
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                  data_out <= ram_data(to_integer(unsigned(addr))); -- read port
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                  if (we = '1') then
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                    ram_data(to_integer(unsigned(addr))) <= data_in; -- write port
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        end if;
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      end if;
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    end if;
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  end process;
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end architecture rtl;
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