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[/] [System09/] [trunk/] [src/] [sys09bug/] [mon_rom_vhd] - Blame information for rev 97

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Line No. Rev Author Line
1 59 davidgb
--
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-- SYS09BUG Monitor Program
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-- v1.0 - 21 November 2006 - John Knet
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--
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-- v1.1 - 22 december 2006 - John Kent
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--        made into 4K ROM/RAM.
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
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    use unisim.vcomponents.all;
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entity mon_rom is
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (11 downto 0);
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       data_out : out std_logic_vector (7 downto 0);
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       data_in : in  std_logic_vector (7 downto 0)
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    );
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end mon_rom;
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architecture rtl of mon_rom is
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  signal we     : std_logic;
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  signal cs0    : std_logic;
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  signal cs1    : std_logic;
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  signal dp0    : std_logic;
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  signal dp1    : std_logic;
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  signal rdata0 : std_logic_vector(7 downto 0);
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  signal rdata1 : std_logic_vector(7 downto 0);
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component SYS09BUG_F000
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (10 downto 0);
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       data_out : out std_logic_vector (7 downto 0);
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       data_in : in  std_logic_vector (7 downto 0)
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    );
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end component;
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component SYS09BUG_F800
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (10 downto 0);
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       data_out : out std_logic_vector (7 downto 0);
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       data_in : in  std_logic_vector (7 downto 0)
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    );
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end component;
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begin
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   addr_f000 : SYS09BUG_F000 port map (
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       clk   => clk,
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       rst   => rst,
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       cs    => cs0,
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       rw    => rw,
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       addr  => addr(10 downto 0),
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       data_in => data_in,
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       data_out => rdata0
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    );
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   addr_f800 : SYS09BUG_F800 port map (
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       clk   => clk,
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       rst   => rst,
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       cs    => cs1,
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       rw    => rw,
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       addr  => addr(10 downto 0),
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       data_in => data_in,
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       data_out => rdata1
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    );
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    my_mon : process ( rw, addr, cs, rdata0, rdata1 )
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    begin
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       we    <= not rw;
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       case addr(11) is
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           when '0' =>
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               cs0   <= cs;
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               cs1   <= '0';
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               data_out <= rdata0;
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           when '1' =>
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               cs0   <= '0';
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               cs1   <= cs;
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               data_out <= rdata1;
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           when others =>
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               null;
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       end case;
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    end process;
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end architecture rtl;
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