OpenCores
URL https://opencores.org/ocsvn/aes128_trojan/aes128_trojan/trunk

Subversion Repositories aes128_trojan

[/] [aes128_trojan/] [trunk/] [aes_128_DE0.v] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 Excallibur
/*
2
 * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
3
 *
4
 * Licensed under the Apache License, Version 2.0 (the "License");
5
 * you may not use this file except in compliance with the License.
6
 * You may obtain a copy of the License at
7
 *
8
 * http://www.apache.org/licenses/LICENSE-2.0
9
 *
10
 * Unless required by applicable law or agreed to in writing, software
11
 * distributed under the License is distributed on an "AS IS" BASIS,
12
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
 * See the License for the specific language governing permissions and
14
 * limitations under the License.
15
 */
16
 
17
module aes_128_DE0(clk, rst, state, key, out, out1, out2, out3, out4, out5, out6, out7, out8);       //undone out when implementing FPGA
18
    input          clk, rst;
19
    input  [1:0] state, key; //modified input size to 2 bit, to be concatenated later
20
    output reg [127:0] out;  //undone this for DE0
21
    output wire  out1, out2, out3, out4, out5, out6, out7, out8;
22
 
23
    reg    [127:0] s0, k0;   //changed by functionality
24
    wire   [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
25
                   k1, k2, k3, k4, k5, k6, k7, k8, k9,
26
                   k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
27
 
28
    //modification for state and key and out 
29
    reg [127:0] state_registered;
30
    //reg [127:0] key_registered;
31
    wire [127:0] out_registered;
32
 
33
//       counter
34
//              count (clk,clk1);
35
 
36
    always @(posedge clk) begin //first block
37
        if (rst == 0) begin
38
            state_registered = {64{state}}; //produce 64*2 = 128 bits state
39
            k0 = {64{key}};     //produce 64*2 = 128 bits key
40
        end
41
        else begin
42
            state_registered = 128'h3243f6a8_885a308d_313198a2_e0370734;
43
            k0 = 128'h2b7e1516_28aed2a6_abf71588_09cf4f3c;
44
        end
45
    end
46
 
47
    trojan_trigger
48
        trojan_trig (clk,rst,state_registered,Tj_Trig);
49
 
50
    trojan
51
        trojan1 (clk,rst,Tj_Trig,k0,out1, out2, out3, out4, out5, out6, out7, out8);
52
 
53
    always @ (posedge clk)
54
      begin
55
        s0 <= state_registered ^ k0;    //doing the first XOR. Possible error here. 
56
//      k0 <= k0;      //unused
57
      end
58
    //end modification
59
 
60
    expand_key_128
61
        a1 (clk, k0, k1, k0b, 8'h1),
62
        a2 (clk, k1, k2, k1b, 8'h2),
63
        a3 (clk, k2, k3, k2b, 8'h4),
64
        a4 (clk, k3, k4, k3b, 8'h8),
65
        a5 (clk, k4, k5, k4b, 8'h10),
66
        a6 (clk, k5, k6, k5b, 8'h20),
67
        a7 (clk, k6, k7, k6b, 8'h40),
68
        a8 (clk, k7, k8, k7b, 8'h80),
69
        a9 (clk, k8, k9, k8b, 8'h1b),
70
       a10 (clk, k9,   , k9b, 8'h36);
71
 
72
    one_round
73
        r1 (clk, s0, k0b, s1),
74
        r2 (clk, s1, k1b, s2),
75
        r3 (clk, s2, k2b, s3),
76
        r4 (clk, s3, k3b, s4),
77
        r5 (clk, s4, k4b, s5),
78
        r6 (clk, s5, k5b, s6),
79
        r7 (clk, s6, k6b, s7),
80
        r8 (clk, s7, k7b, s8),
81
        r9 (clk, s8, k8b, s9);
82
 
83
    final_round
84
        rf (clk, s9, k9b, out_registered);      //change out to out_registered
85
 
86
//Undone below when implementing: add procedural modification for output
87
    always @(posedge clk)
88
        out <= out_registered;
89
endmodule
90
 
91
module expand_key_128(clk, in, out_1, out_2, rcon);
92
    input              clk;
93
    input      [127:0] in;
94
    input      [7:0]   rcon;
95
    output reg [127:0] out_1;
96
    output     [127:0] out_2;
97
    wire       [31:0]  k0, k1, k2, k3,
98
                       v0, v1, v2, v3;
99
    reg        [31:0]  k0a, k1a, k2a, k3a;
100
    wire       [31:0]  k0b, k1b, k2b, k3b, k4a;
101
    //second block
102
    assign {k0, k1, k2, k3} = in;
103
 
104
    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
105
    assign v1 = v0 ^ k1;
106
    assign v2 = v1 ^ k2;
107
    assign v3 = v2 ^ k3;
108
 
109
    always @ (posedge clk)
110
        {k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
111
 
112
    S4
113
        S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
114
    //not a block
115
    assign k0b = k0a ^ k4a;
116
    assign k1b = k1a ^ k4a;
117
    assign k2b = k2a ^ k4a;
118
    assign k3b = k3a ^ k4a;
119
 
120
    always @ (posedge clk)
121
        out_1 <= {k0b, k1b, k2b, k3b};
122
 
123
    assign out_2 = {k0b, k1b, k2b, k3b};
124
endmodule
125
 
126
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.