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[/] [aes128_trojan/] [trunk/] [counter.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Excallibur
`timescale 1ns/1ps
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module counter(clk,counter_out);
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input clk;
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output reg [3:0]counter_out;
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reg [23:0]count;
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initial begin
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        counter_out = 4'b0000;
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        count = 24'd0;
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end
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always@(posedge clk) begin
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        if(count == 24'd50000000) begin
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                counter_out <= counter_out + 1'b1;
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                count <= 24'd0;
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        end else count <= count + 1'b1;
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end
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endmodule

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