OpenCores
URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [docs/] [altor_insn.md] - Blame information for rev 41

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 41 ultra_embe
AltOR32 Instruction Set
2
=======================
3
 
4
### l.add rD,rA,rB
5
 
6
##### Description
7
The contents of register rA are added to the contents of register rB to form the result.
8
The result is placed into register rD.
9
The carry flag is set on unsigned arithmetic overflow.
10
 
11
##### Implementation
12
`rD[31:0] = rA[31:0] + rB[31:0]`
13
`SR[CY]   = carry out`
14
 
15
##### Encoding
16
`opcode[31:26] == 0x38`
17
`opcode[9:8]   == 0x0`
18
`opcode[3:0]   == 0x0`
19
`opcode[25:21] == rD`
20
`opcode[20:16] == rA`
21
`opcode[15:11] == rB`
22
 
23
### l.addc rD,rA,rB
24
 
25
##### Description
26
The contents of register rA are added to the contents of register rB and carry SR[CY] to form the result.
27
The result is placed into register rD.
28
The carry flag is set on unsigned arithmetic overflow.
29
 
30
##### Implementation
31
`rD[31:0] = rA[31:0] + rB[31:0] + SR[CY]`
32
`SR[CY]   = carry out`
33
 
34
##### Encoding
35
`opcode[31:26] == 0x38`
36
`opcode[9:8]   == 0x0`
37
`opcode[3:0]   == 0x1`
38
`opcode[25:21] == rD`
39
`opcode[20:16] == rA`
40
`opcode[15:11] == rB`
41
 
42
### l.addi rD,rA,I
43
 
44
##### Description
45
The immediate value is sign-extended and added to the contents of register rA to form the result.
46
The result is placed into register rD.
47
The carry flag is set on unsigned arithmetic overflow.
48
 
49
##### Implementation
50
`rD[31:0] = rA[31:0] + sign_extend(Immediate)`
51
`SR[CY]   = carry out`
52
 
53
##### Encoding
54
`opcode[31:26] == 0x27`
55
`opcode[25:21] == rD`
56
`opcode[20:16] == rA`
57
`opcode[15:0]  == Immediate`
58
 
59
### l.and rD,rA,rB
60
 
61
##### Description
62
The contents of register rA are combined with the contents of register rB in a bit-wise logical AND operation.
63
The result is placed into register rD.
64
 
65
##### Implementation
66
`rD[31:0] = rA[31:0] AND rB[31:0]`
67
 
68
##### Encoding
69
`opcode[31:26] == 0x38`
70
`opcode[9:8]   == 0x0`
71
`opcode[3:0]   == 0x3`
72
`opcode[25:21] == rD`
73
`opcode[20:16] == rA`
74
`opcode[15:11] == rB`
75
 
76
### l.andi rD,rA,K
77
 
78
##### Description
79
The immediate value is zero-extended and combined with the contents of register rA in a bit-wise logical AND operation.
80
The result is placed into register rD.
81
 
82
##### Implementation
83
`rD[31:0] = rA[31:0] AND unsigned_extend(Immediate)`
84
 
85
##### Encoding
86
`opcode[31:26] == 0x29`
87
`opcode[25:21] == rD`
88
`opcode[20:16] == rA`
89
`opcode[15:0]  == Immediate`
90
 
91
### l.bf N
92
 
93
##### Description
94
The immediate value is shifted left two bits, sign-extended to program counter width, and then added to the address of the branch instruction.
95
If the flag is set, the program branches to the calculated address.
96
 
97
##### Implementation
98
`ADDR = sign_extend(Immediate << 2) + CurrentPC`
99
`PC   = ADDR if SR[F] set`
100
 
101
##### Encoding
102
`opcode[31:26] == 0x4`
103
`opcode[25:0]  == N`
104
 
105
### l.bnf N
106
 
107
##### Description
108
The immediate value is shifted left two bits, sign-extended to program counter width, and then added to the address of the branch instruction.
109
If the flag is not set, the program branches to the calculated address.
110
 
111
##### Implementation
112
`ADDR = sign_extend(Immediate << 2) + CurrentPC`
113
`PC   = ADDR if SR[F] cleared`
114
 
115
##### Encoding
116
`opcode[31:26] == 0x3`
117
`opcode[25:0]  == N`
118
 
119
### l.j N
120
 
121
##### Description
122
The immediate value is shifted left two bits, sign-extended to program counter width, and then added to the address of the jump instruction.
123
The program unconditionally jumps to the calculated address.
124
 
125
##### Implementation
126
`PC = sign_extend(Immediate << 2) + CurrentPC`
127
 
128
##### Encoding
129
`opcode[31:26] == 0x0`
130
`opcode[25:0]  == N`
131
 
132
### l.jal N
133
 
134
##### Description
135
The immediate value is shifted left two bits, sign-extended to program counter width, and then added to the address of the jump instruction.
136
The program unconditionally jumps to the calculated address and the instruction address after the jump location is stored in R9 (LR).
137
 
138
##### Implementation
139
`PC = sign_extend(Immediate << 2) + CurrentPC`
140
`LR = CurrentPC + 4`
141
 
142
##### Encoding
143
`opcode[31:26] == 0x1`
144
`opcode[25:0]  == N`
145
 
146
### l.jalr rB
147
 
148
##### Description
149
The contents of register rB is the effective address of the jump.
150
The program unconditionally jumps to the address held in rB and the instruction address after the jump location is stored in R9 (LR).
151
 
152
##### Implementation
153
`PC = rB`
154
`LR = CurrentPC + 4`
155
 
156
##### Encoding
157
`opcode[31:26] == 0x12`
158
`opcode[15:11] == rB`
159
 
160
### l.jr rB
161
 
162
##### Description
163
The contents of register rB is the effective address of the jump.
164
The program unconditionally jumps to the address in rB.
165
 
166
##### Implementation
167
`PC = rB`
168
 
169
##### Encoding
170
`opcode[31:26] == 0x11`
171
`opcode[15:11] == rB`
172
 
173
### l.lbs rD,I(rA)
174
 
175
##### Description
176
The offset is sign-extended and added to the contents of register rA.
177
The byte in memory addressed by ADDR is loaded into the low-order eight bits of register rD. High-order bits of register rD are replaced with bit 7 of the loaded value.
178
 
179
##### Implementation
180
`ADDR     = sign_extend(Immediate) + rA[31:0]`
181
`rD[7:0]  = ADDR[7:0]`
182
`rD[31:8] = ADDR[7]`
183
 
184
##### Encoding
185
`opcode[31:26] == 0x24`
186
`opcode[25:21] == rD`
187
`opcode[20:16] == rA`
188
`opcode[15:0]  == Immediate`
189
 
190
### l.lbz rD,I(rA)
191
 
192
##### Description
193
The offset is sign-extended and added to the contents of register rA.
194
The byte in memory addressed by ADDR is loaded into the low-order eight bits of register rD. High-order bits of register rD are replaced with zero.
195
 
196
##### Implementation
197
`ADDR     = sign_extend(Immediate) + rA[31:0]`
198
`rD[7:0]  = ADDR[7:0]`
199
`rD[31:8] = 0`
200
 
201
##### Encoding
202
`opcode[31:26] == 0x23`
203
`opcode[25:21] == rD`
204
`opcode[20:16] == rA`
205
`opcode[15:0]  == Immediate`
206
 
207
### l.lhs rD,I(rA)
208
 
209
##### Description
210
The offset is sign-extended and added to the contents of register rA.
211
The half word in memory addressed by ADDR is loaded into the low-order 16 bits of register rD. High-order bits of register rD are replaced with bit 15 of the loaded value.
212
 
213
##### Implementation
214
`ADDR        = sign_extend(Immediate) + rA[31:0]`
215
`rD[15:0]    = ADDR[15:0]`
216
`rD[31:16]   = ADDR[15]`
217
 
218
##### Encoding
219
`opcode[31:26] == 0x26`
220
`opcode[25:21] == rD`
221
`opcode[20:16] == rA`
222
`opcode[15:0]  == Immediate`
223
 
224
### l.lhz rD,I(rA)
225
 
226
##### Description
227
The offset is sign-extended and added to the contents of register rA.
228
The half word in memory addressed by ADDR is loaded into the low-order 16 bits of register rD. High-order bits of register rD are replaced with zero.
229
 
230
##### Implementation
231
`ADDR        = sign_extend(Immediate) + rA[31:0]`
232
`rD[15:0]    = ADDR[15:0]`
233
`rD[31:16]   = 0`
234
 
235
##### Encoding
236
`opcode[31:26] == 0x25`
237
`opcode[25:21] == rD`
238
`opcode[20:16] == rA`
239
`opcode[15:0]  == Immediate`
240
 
241
### l.lws rD,I(rA)
242
 
243
##### Description
244
The offset is sign-extended and added to the contents of register rA.
245
The single word in memory addressed by ADDR is loaded into the low-order 32 bits of register rD. High-order bits of register rD are replaced with bit 31 of the loaded value.
246
 
247
##### Implementation
248
`ADDR           = sign_extend(Immediate) + rA[31:0]`
249
`rD[31:0]       = ADDR[31:0]`
250
 
251
##### Encoding
252
`opcode[31:26] == 0x22`
253
`opcode[25:21] == rD`
254
`opcode[20:16] == rA`
255
`opcode[15:0]  == Immediate`
256
 
257
### l.lwz rD,I(rA)
258
 
259
##### Description
260
The offset is sign-extended and added to the contents of register rA.
261
The single word in memory addressed by ADDR is loaded into the low-order 32 bits of register rD. High-order bits of register rD are replaced with zero.
262
 
263
##### Implementation
264
`ADDR           = sign_extend(Immediate) + rA[31:0]`
265
`rD[31:0]       = ADDR[31:0]`
266
 
267
##### Encoding
268
`opcode[31:26] == 0x21`
269
`opcode[25:21] == rD`
270
`opcode[20:16] == rA`
271
`opcode[15:0]  == Immediate`
272
 
273
### l.mfspr rD,rA,K
274
 
275
##### Description
276
The contents of the special register, defined by contents of rA logically ORed with immediate value, are moved into register rD.
277
 
278
##### Implementation
279
`rD[31:0] = spr(rA OR Immediate)`
280
 
281
##### Encoding
282
`opcode[31:26] == 0x2d`
283
`opcode[25:21] == rD`
284
`opcode[20:16] == rA`
285
`opcode[15:0]  == Immediate`
286
 
287
### l.movhi rD,K
288
 
289
##### Description
290
The 16-bit immediate value is zero-extended, shifted left by 16 bits, and placed into register rD.
291
 
292
##### Implementation
293
`rD[31:0] = unsigned_extend(Immediate) << 16`
294
 
295
##### Encoding
296
`opcode[31:26] == 0x6`
297
`opcode[25:21] == rD`
298
`opcode[15:0]  == Immediate`
299
 
300
### l.mtspr rA,rB,K
301
 
302
##### Description
303
The contents of register rB are moved into the special register defined by contents of register rA logically ORed with the immediate value.
304
 
305
##### Implementation
306
`spr(rA OR Immediate) = rB[31:0]`
307
 
308
##### Encoding
309
`opcode[31:26] == 0x30`
310
`opcode[25:21] == Immediate[15:11]`
311
`opcode[20:16] == rA`
312
`opcode[15:11] == rB`
313
`opcode[10:0]  == Immediate[10:0]`
314
 
315
### l.nop K
316
 
317
##### Description
318
This instruction does not normally do anything other than consume a cycle. In simulation, the immediate value may be used to control various settings / print to the console.
319
 
320
##### Implementation
321
`null operation`
322
 
323
##### Encoding
324
`opcode[31:26] == 0x15`
325
`opcode[15:0] == Immediate`
326
 
327
### l.or rD,rA,rB
328
 
329
##### Description
330
The contents of register rA are combined with the contents of register rB in a bit-wise logical OR operation.
331
The result is placed into register rD.
332
 
333
##### Implementation
334
`rD[31:0] = rA[31:0] OR rB[31:0]`
335
 
336
##### Encoding
337
`opcode[31:26] == 0x38`
338
`opcode[9:8]   == 0x0`
339
`opcode[3:0]   == 0x4`
340
`opcode[25:21] == rD`
341
`opcode[20:16] == rA`
342
`opcode[15:11] == rB`
343
 
344
### l.ori rD,rA,K
345
 
346
##### Description
347
The immediate value is zero-extended and combined with the contents of register rA in a bit-wise logical OR operation. The result is placed into register rD.
348
 
349
##### Implementation
350
`rD[31:0] = rA[31:0] OR unsigned_extend(Immediate)`
351
 
352
##### Encoding
353
`opcode[31:26] == 0x2a`
354
`opcode[25:21] == rD`
355
`opcode[20:16] == rA`
356
`opcode[15:0]  == Immediate`
357
 
358
### l.rfe 
359
 
360
##### Description
361
Execution of this instruction restores PC and SR (status register) registers. Intended as a return from interrupt instruction.
362
 
363
##### Implementation
364
`PC = EPC`
365
`SR = ESR`
366
 
367
##### Encoding
368
`opcode[31:26] == 0x9`
369
 
370
### l.sb I(rA),rB
371
 
372
##### Description
373
The offset is sign-extended and added to the contents of register rA. The sum represents an effective address. The low-order 8 bits of register rB are stored to memory location addressed by ADDR.
374
 
375
##### Implementation
376
`ADDR           = sign_extend(Immediate) + rA[31:0]`
377
`ADDR[7:0]  = rB[7:0]`
378
 
379
##### Encoding
380
`opcode[31:26] == 0x36`
381
`opcode[25:21] == Immediate[15:11]`
382
`opcode[20:16] == rA`
383
`opcode[15:11] == rB`
384
`opcode[10:0]  == Immediate[10:0]`
385
 
386
### l.sfeq rA,rB
387
 
388
##### Description
389
The contents of registers rA and rB are compared. If the contents are equal, the compare flag is set; otherwise the compare flag is cleared.
390
 
391
##### Implementation
392
`SR[F] = rA[31:0] == rB[31:0]`
393
 
394
##### Encoding
395
`opcode[31:21] == 0x720`
396
`opcode[20:16] == rA`
397
`opcode[15:11] == rB`
398
 
399
### l.sfeqi rA,I
400
 
401
##### Description
402
The contents of register rA and the sign-extended immediate value are compared. If the two values are equal, the compare flag is set; otherwise the compare flag is cleared.
403
 
404
##### Implementation
405
`SR[F] = rA[31:0] == sign_extend(Immediate)`
406
 
407
##### Encoding
408
`opcode[31:21] == 0x5e0`
409
`opcode[20:16] == rA`
410
`opcode[15:0]  == Immediate`
411
 
412
### l.sfges rA,rB
413
 
414
##### Description
415
The contents of registers rA and rB are compared as signed integers. If the contents of the first register are greater than or equal to the contents of the second register, the compare flag is set; otherwise the compare flag is cleared.
416
 
417
##### Implementation
418
`SR[F] = rA[31:0] >= rB[31:0]`
419
 
420
##### Encoding
421
`opcode[31:21] == 0x72b`
422
`opcode[20:16] == rA`
423
`opcode[15:11] == rB`
424
 
425
### l.sfgesi rA,I
426
 
427
##### Description
428
The contents of register rA and the sign-extended immediate value are compared as signed integers. If the contents of the first register are greater than or equal to the immediate value the compare flag is set; otherwise the compare flag is cleared.
429
 
430
##### Implementation
431
`SR[F] = rA[31:0] >= sign_extend(Immediate)`
432
 
433
##### Encoding
434
`opcode[31:21] == 0x5eb`
435
`opcode[20:16] == rA`
436
`opcode[15:0]  == Immediate`
437
 
438
### l.sfgeu rA,rB
439
 
440
##### Description
441
The contents of registers rA and rB are compared as unsigned integers. If the contents of the first register are greater than or equal to the contents of the second register, the compare flag is set; otherwise the compare flag is cleared.
442
 
443
##### Implementation
444
`SR[F] = rA[31:0] >= rB[31:0]`
445
 
446
##### Encoding
447
`opcode[31:21] == 0x723`
448
`opcode[20:16] == rA`
449
`opcode[15:11] == rB`
450
 
451
### l.sfgeui rA,I
452
 
453
##### Description
454
The contents of register rA and the sign-extended immediate value are compared as unsigned integers. If the contents of the first register are greater than or equal to the immediate value the compare flag is set; otherwise the compare flag is cleared.
455
 
456
##### Implementation
457
`SR[F] = rA[31:0] >= sign_extend(Immediate)`
458
 
459
##### Encoding
460
`opcode[31:21] == 0x5e3`
461
`opcode[20:16] == rA`
462
`opcode[15:0]  == Immediate`
463
 
464
### l.sfgts rA,rB
465
 
466
##### Description
467
The contents of registers rA and rB are compared as signed integers. If the contents of the first register are greater than the contents of the second register, the compare flag is set; otherwise the compare flag is cleared.
468
 
469
##### Implementation
470
`SR[F] = rA[31:0] > rB[31:0]`
471
 
472
##### Encoding
473
`opcode[31:21] == 0x72a`
474
`opcode[20:16] == rA`
475
`opcode[15:11] == rB`
476
 
477
### l.sfgtsi rA,I
478
 
479
##### Description
480
The contents of register rA and the sign-extended immediate value are compared as signed integers. If the contents of the first register are greater than the immediate value the compare flag is set; otherwise the compare flag is cleared.
481
 
482
##### Implementation
483
`SR[F] = rA[31:0] > sign_extend(Immediate)`
484
 
485
##### Encoding
486
`opcode[31:21] == 0x5ea`
487
`opcode[20:16] == rA`
488
`opcode[15:0]  == Immediate`
489
 
490
### l.sfgtu rA,rB
491
 
492
##### Description
493
The contents of registers rA and rB are compared as unsigned integers. If the contents of the first register are greater than the contents of the second register, the compare flag is set; otherwise the compare flag is cleared.
494
 
495
##### Implementation
496
`SR[F] = rA[31:0] > rB[31:0]`
497
 
498
##### Encoding
499
`opcode[31:21] == 0x722`
500
`opcode[20:16] == rA`
501
`opcode[15:11] == rB`
502
 
503
### l.sfgtui rA,I
504
 
505
##### Description
506
The contents of register rA and the sign-extended immediate value are compared as unsigned integers. If the contents of the first register are greater than the immediate value the compare flag is set; otherwise the compare flag is cleared.
507
 
508
##### Implementation
509
`SR[F] = rA[31:0] > sign_extend(Immediate)`
510
 
511
##### Encoding
512
`opcode[31:21] == 0x5e2`
513
`opcode[20:16] == rA`
514
`opcode[15:0]  == Immediate`
515
 
516
### l.sfles rA,rB
517
 
518
##### Description
519
The contents of registers rA and rB are compared as signed integers. If the contents of the first register are less than or equal to the contents of the second register, the compare flag is set; otherwise the compare flag is cleared.
520
 
521
##### Implementation
522
`SR[F] = rA[31:0] <= rB[31:0]`
523
 
524
##### Encoding
525
`opcode[31:21] == 0x72d`
526
`opcode[20:16] == rA`
527
`opcode[15:11] == rB`
528
 
529
### l.sflesi rA,I
530
 
531
##### Description
532
The contents of register rA and the sign-extended immediate value are compared as signed integers. If the contents of the first register are less than or equal to the immediate value the compare flag is set; otherwise the compare flag is cleared.
533
 
534
##### Implementation
535
`SR[F] = rA[31:0] <= sign_extend(Immediate)`
536
 
537
##### Encoding
538
`opcode[31:21] == 0x5ed`
539
`opcode[20:16] == rA`
540
`opcode[15:0]  == Immediate`
541
 
542
### l.sfleu rA,rB
543
 
544
##### Description
545
The contents of registers rA and rB are compared as unsigned integers. If the contents of the first register are less than or equal to the contents of the second register, the compare flag is set; otherwise the compare flag is cleared.
546
 
547
##### Implementation
548
`SR[F] = rA[31:0] <= rB[31:0]`
549
 
550
##### Encoding
551
`opcode[31:21] == 0x725`
552
`opcode[20:16] == rA`
553
`opcode[15:11] == rB`
554
 
555
### l.sfleui rA,I
556
 
557
##### Description
558
The contents of register rA and the sign-extended immediate value are compared as unsigned integers. If the contents of the first register are less than or equal to the immediate value the compare flag is set; otherwise the compare flag is cleared.
559
 
560
##### Implementation
561
`SR[F] = rA[31:0] <= sign_extend(Immediate)`
562
 
563
##### Encoding
564
`opcode[31:21] == 0x5e5`
565
`opcode[20:16] == rA`
566
`opcode[15:0]  == Immediate`
567
 
568
### l.sflts rA,rB
569
 
570
##### Description
571
The contents of registers rA and rB are compared as signed integers. If the contents of the first register are less than the contents of the second register, the compare flag is set; otherwise the compare flag is cleared.
572
 
573
##### Implementation
574
`SR[F] = rA[31:0] < rB[31:0]`
575
 
576
##### Encoding
577
`opcode[31:21] == 0x72c`
578
`opcode[20:16] == rA`
579
`opcode[15:11] == rB`
580
 
581
### l.sfltsi rA,I
582
 
583
##### Description
584
The contents of register rA and the sign-extended immediate value are compared as signed integers. If the contents of the first register are less than the immediate value the compare flag is set; otherwise the compare flag is cleared.
585
 
586
##### Implementation
587
`SR[F] = rA[31:0] < sign_extend(Immediate)`
588
 
589
##### Encoding
590
`opcode[31:21] == 0x5ec`
591
`opcode[20:16] == rA`
592
`opcode[15:0]  == Immediate`
593
 
594
### l.sfltu rA,rB
595
 
596
##### Description
597
The contents of registers rA and rB are compared as unsigned integers. If the contents of the first register are less than the contents of the second register, the compare flag is set; otherwise the compare flag is cleared.
598
 
599
##### Implementation
600
`SR[F] = rA[31:0] < rB[31:0]`
601
 
602
##### Encoding
603
`opcode[31:21] == 0x724`
604
`opcode[20:16] == rA`
605
`opcode[15:11] == rB`
606
 
607
### l.sfltui rA,I
608
 
609
##### Description
610
The contents of register rA and the sign-extended immediate value are compared as unsigned integers. If the contents of the first register are less than the immediate value the compare flag is set; otherwise the compare flag is cleared.
611
 
612
##### Implementation
613
`SR[F] = rA[31:0] < sign_extend(Immediate)`
614
 
615
##### Encoding
616
`opcode[31:21] == 0x5e4`
617
`opcode[20:16] == rA`
618
`opcode[15:0]  == Immediate`
619
 
620
### l.sfne rA,rB
621
 
622
##### Description
623
The contents of registers rA and rB are compared. If the contents are not equal, the compare flag is set; otherwise the compare flag is cleared.
624
 
625
##### Implementation
626
`SR[F] = rA[31:0] != rB[31:0]`
627
 
628
##### Encoding
629
`opcode[31:21] == 0x721`
630
`opcode[20:16] == rA`
631
`opcode[15:11] == rB`
632
 
633
### l.sfnei rA,I
634
 
635
##### Description
636
The contents of register rA and the sign-extended immediate value are compared. If the two values are not equal, the compare flag is set; otherwise the compare flag is cleared.
637
 
638
##### Implementation
639
`SR[F] = rA[31:0] != sign_extend(Immediate)`
640
 
641
##### Encoding
642
`opcode[31:21] == 0x5e1`
643
`opcode[20:16] == rA`
644
`opcode[15:0]  == Immediate`
645
 
646
### l.sh I(rA),rB
647
 
648
##### Description
649
The offset is sign-extended and added to the contents of register rA. The sum represents an effective address. The low-order 16 bits of register rB are stored to memory location addressed by ADDR.
650
 
651
##### Implementation
652
`ADDR            = sign_extend(Immediate) + rA[31:0]`
653
`ADDR[15:0]  = rB[15:0]`
654
 
655
##### Encoding
656
`opcode[31:26] == 0x37`
657
`opcode[25:21] == Immediate[15:11]`
658
`opcode[20:16] == rA`
659
`opcode[15:11] == rB`
660
`opcode[10:0]  == Immediate[10:0]`
661
 
662
### l.sll rD,rA,rB
663
 
664
##### Description
665
Register rB specifies the number of bit positions; the contents of register rA are shifted left, inserting zeros into the low-order bits.
666
The result is written into rD.
667
 
668
##### Implementation
669
`rD[31:rB[4:0]]  = rA[31-rB[4:0]:0]`
670
`rD[rB[4:0]-1:0] = 0`
671
 
672
##### Encoding
673
`opcode[31:26] == 0x38`
674
`opcode[9:8]   == 0x0`
675
`opcode[3:0]   == 0x8`
676
`opcode[25:21] == rD`
677
`opcode[20:16] == rA`
678
`opcode[15:11] == rB`
679
 
680
### l.slli rD,rA,L
681
 
682
##### Description
683
The immediate value specifies the number of bit positions; the contents of register rA are shifted left, inserting zeros into the low-order bits.
684
The result is written into register rD.
685
 
686
##### Implementation
687
`rD[31:L]  = rA[31-L:0]`
688
`rD[L-1:0] = 0`
689
`opcode[25:21] == rD`
690
`opcode[20:16] == rA`
691
`opcode[15:0]  == Immediate`
692
 
693
##### Encoding
694
`opcode[31:26] == 0x2e`
695
`opcode[25:21] == rD`
696
`opcode[20:16] == rA`
697
`opcode[5:0]   == Immediate`
698
 
699
### l.sra rD,rA,rB
700
 
701
##### Description
702
Register rB specifies the number of bit positions; the contents of register rA are shifted right, sign-extending the high-order bits.
703
The result is written into register rD.
704
 
705
##### Implementation
706
`rD[31-rB[4:0]:0]  = rA[31:rB[4:0]]`
707
`rD[31:32-rB[4:0]] = rA[31]`
708
 
709
##### Encoding
710
`opcode[31:26] == 0x38`
711
`opcode[9:8]   == 0x2`
712
`opcode[3:0]   == 0x8`
713
`opcode[25:21] == rD`
714
`opcode[20:16] == rA`
715
`opcode[15:11] == rB`
716
 
717
### l.srai rD,rA,L
718
 
719
##### Description
720
The 6-bit immediate value specifies the number of bit positions; the contents of register rA are shifted right, sign-extending the high-order bits.
721
The result is written into register rD.
722
 
723
##### Implementation
724
`rD[31-L:0]  = rA[31:L]`
725
`rD[31:32-L] = rA[31]`
726
 
727
##### Encoding
728
`opcode[31:26] == 0x2e`
729
`opcode[25:21] == rD`
730
`opcode[20:16] == rA`
731
`opcode[5:0]   == Immediate`
732
 
733
### l.srl rD,rA,rB
734
 
735
##### Description
736
Register rB specifies the number of bit positions; the contents of register rA are shifted right, inserting zeros into the high-order bits.
737
The result is written into register rD.
738
 
739
##### Implementation
740
`rD[31-rB[4:0]:0]  = rA[31:rB[4:0]]`
741
`rD[31:32-rB[4:0]] = 0`
742
 
743
##### Encoding
744
`opcode[31:26] == 0x38`
745
`opcode[9:8]   == 0x1`
746
`opcode[3:0]   == 0x8`
747
`opcode[25:21] == rD`
748
`opcode[20:16] == rA`
749
`opcode[15:11] == rB`
750
 
751
### l.srli rD,rA,L
752
 
753
##### Description
754
The 6-bit immediate value specifies the number of bit positions; the contents of register rA are shifted right, inserting zeros into the high-order bits.
755
The result is written into register rD.
756
 
757
##### Implementation
758
`rD[31-L:0]  = rA[31:L]`
759
`rD[31:32-L] = 0`
760
 
761
##### Encoding
762
`opcode[31:26] == 0x2e`
763
`opcode[25:21] == rD`
764
`opcode[20:16] == rA`
765
`opcode[5:0]   == Immediate`
766
 
767
### l.sub rD,rA,rB
768
 
769
##### Description
770
The contents of register rB are subtracted from the contents of register rA to form the result. The result is placed into register rD.
771
 
772
##### Implementation
773
`rD[31:0] = rA[31:0] - rB[31:0]`
774
 
775
##### Encoding
776
`opcode[31:26] == 0x38`
777
`opcode[9:8]   == 0x0`
778
`opcode[3:0]   == 0x2`
779
`opcode[25:21] == rD`
780
`opcode[20:16] == rA`
781
`opcode[15:11] == rB`
782
 
783
### l.sw I(rA),rB
784
 
785
##### Description
786
The offset is sign-extended and added to the contents of register rA. The sum represents an effective address. The low-order 32 bits of register rB are stored to memory location addressed by ADDR.
787
 
788
##### Implementation
789
`ADDR            = sign_extend(Immediate) + rA[31:0]`
790
`ADDR[31:0]  = rB[31:0]`
791
 
792
##### Encoding
793
`opcode[31:26] == 0x35`
794
`opcode[25:21] == Immediate[15:11]`
795
`opcode[20:16] == rA`
796
`opcode[15:11] == rB`
797
`opcode[10:0]  == Immediate[10:0]`
798
 
799
### l.sys K
800
 
801
##### Description
802
Execution of the system call instruction results in the system call exception. The system calls exception is a request to the operating system to provide operating system services. The immediate value can be used to specify which system service is requested, alternatively a GPR defined by the ABI can be used to specify system service.
803
 
804
Because an l.sys causes an intentional exception, rather than an interruption of normal processing, the matching l.rfe returns to the next instruction.
805
 
806
##### Implementation
807
`jump_to_sys_vector(K)`
808
 
809
##### Encoding
810
`opcode[31:16] == 0x2000`
811
`opcode[15:0]  == Immediate`
812
 
813
### l.trap K
814
 
815
##### Description
816
Trap exception is a request to the operating system or to the debug facility to execute certain debug services. The immediate value is not used by the CPU itself, but can be used by trap handling software as an argument for handling the breakpoint.
817
 
818
##### Implementation
819
`jump_to_trap_vector(K)`
820
 
821
##### Encoding
822
`opcode[31:16] == 0x2100`
823
`opcode[15:0]  == Immediate`
824
 
825
### l.xor rD,rA,rB
826
 
827
##### Description
828
The contents of register rA are combined with the contents of register rB in a bit-wise logical XOR operation.
829
The result is placed into register rD.
830
 
831
##### Implementation
832
`rD[31:0] = rA[31:0] XOR rB[31:0]`
833
 
834
##### Encoding
835
`opcode[31:26] == 0x38`
836
`opcode[9:8]   == 0x0`
837
`opcode[3:0]   == 0x5`
838
`opcode[25:21] == rD`
839
`opcode[20:16] == rA`
840
`opcode[15:11] == rB`
841
 
842
### l.xori rD,rA,I
843
 
844
##### Description
845
The immediate value is sign-extended and combined with the contents of register rA in a bit-wise logical XOR operation.
846
The result is placed into register rD.
847
 
848
##### Implementation
849
`rD[31:0] = rA[31:0] XOR sign_extend(Immediate)`
850
 
851
##### Encoding
852
`opcode[31:26] == 0x2b`
853
`opcode[25:21] == rD`
854
`opcode[20:16] == rA`
855
`opcode[15:0]  == Immediate`

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.