URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [docs/] [altor_vectors.md] - Blame information for rev 41

Details | Compare with Previous | View Log


﻿AltOR32 Exception Vectors
=========================
 
AltOR32 exception vectors apart from reset are relative to the 'ISR_VECTOR' constant.
The reset vector is relative to 'BOOT_VECTOR'.
 
| Vector   | Priority | Description                    |
|----------| ---------|--------------------------------|
|  0x100   |    0     | Reset vector.                  |
|  0x200   |    1     | Illegal instruction vector.    |
|  0x300   |    5     | External interrupt vector.     |
|  0x400   |    3     | Syscall instruction vector.    |
|  0x500   |    -     | Unused vector.                 |
|  0x600   |    3     | Trap vector.                   |
|  0x700   |    4     | Non-maskable interrupt vector. |
|  0x800   |    2     | Bus (address) error vector.    |
 
 
### Exception Details
 
##### Reset (0x100)
On core reset (rst_i).
 
`EPC = 0`
`ESR = 0`
`PC  = BOOT_VECTOR + 0x100`
`SR  = 0`
 
##### Illegal Instruction (0x200)
Unsupported instruction executed.
 
`EPC = FAULT_PC + 4`
`ESR = SR`
`PC = ISR_VECTOR + 0x200`
`SR = 0`
 
##### External Interrupt (0x300)
External interrupt (intr_i) active whilst interrupts enabled (SR[IEE] == 1).
 
`EPC = PC (Next instruction to execute after return).`
`ESR = SR`
`PC = ISR_VECTOR + 0x300`
`SR = 0`
 
##### SYSCALL Exception (0x400)
On executing l.sys instruction.
 
`EPC = NEXT_PC (instruction after l.sys).`
`ESR = SR`
`PC  = ISR_VECTOR + 0x400`
`SR  = 0`
 
##### Trap Exception (0x600)
On executing l.trap instruction.
 
`EPC = NEXT_PC (instruction after l.trap).`
`ESR = SR`
`PC  = ISR_VECTOR + 0x600`
`SR  = 0`
 
##### Non-maskable Interrupt (NMI) (0x700)
Non-maskable interrupt (nmi_i) active. The non-maskable interrupt is latched internally so should not be asserted for longer than a single cycle.
 
`EPC = PC (Next instruction to execute after return).`
`ESR = SR`
`PC  = ISR_VECTOR + 0x700`
`SR  = 0`
 
##### Bus Error Exception (0x800)
Invalid PC (PC[1:0] != 0) or other erroneous memory access attempt.
 
`EPC = FAULT_PC + 4`
`ESR = SR`
`PC  = ISR_VECTOR + 0x800`
`SR  = 0`
 

Line No.	Rev	Author	Line
1	41	ultra_embe	`AltOR32 Exception Vectors`
2			`=========================`
3
4			`AltOR32 exception vectors apart from reset are relative to the 'ISR_VECTOR' constant.`
5			`The reset vector is relative to 'BOOT_VECTOR'.`
6
7			`\| Vector \| Priority \| Description \|`
8			`\|----------\| ---------\|--------------------------------\|`
9			`\| 0x100 \| 0 \| Reset vector. \|`
10			`\| 0x200 \| 1 \| Illegal instruction vector. \|`
11			`\| 0x300 \| 5 \| External interrupt vector. \|`
12			`\| 0x400 \| 3 \| Syscall instruction vector. \|`
13			`\| 0x500 \| - \| Unused vector. \|`
14			`\| 0x600 \| 3 \| Trap vector. \|`
15			`\| 0x700 \| 4 \| Non-maskable interrupt vector. \|`
16			`\| 0x800 \| 2 \| Bus (address) error vector. \|`
17
18
19			`### Exception Details`
20
21			`##### Reset (0x100)`
22			`On core reset (rst_i).`
23
24			`EPC = 0`
25			`ESR = 0`
26			`PC = BOOT_VECTOR + 0x100`
27			`SR = 0`
28
29			`##### Illegal Instruction (0x200)`
30			`Unsupported instruction executed.`
31
32			`EPC = FAULT_PC + 4`
33			`ESR = SR`
34			`PC = ISR_VECTOR + 0x200`
35			`SR = 0`
36
37			`##### External Interrupt (0x300)`
38			`External interrupt (intr_i) active whilst interrupts enabled (SR[IEE] == 1).`
39
40			`EPC = PC (Next instruction to execute after return).`
41			`ESR = SR`
42			`PC = ISR_VECTOR + 0x300`
43			`SR = 0`
44
45			`##### SYSCALL Exception (0x400)`
46			`On executing l.sys instruction.`
47
48			`EPC = NEXT_PC (instruction after l.sys).`
49			`ESR = SR`
50			`PC = ISR_VECTOR + 0x400`
51			`SR = 0`
52
53			`##### Trap Exception (0x600)`
54			`On executing l.trap instruction.`
55
56			`EPC = NEXT_PC (instruction after l.trap).`
57			`ESR = SR`
58			`PC = ISR_VECTOR + 0x600`
59			`SR = 0`
60
61			`##### Non-maskable Interrupt (NMI) (0x700)`
62			`Non-maskable interrupt (nmi_i) active. The non-maskable interrupt is latched internally so should not be asserted for longer than a single cycle.`
63
64			`EPC = PC (Next instruction to execute after return).`
65			`ESR = SR`
66			`PC = ISR_VECTOR + 0x700`
67			`SR = 0`
68
69			`##### Bus Error Exception (0x800)`
70			`Invalid PC (PC[1:0] != 0) or other erroneous memory access attempt.`
71
72			`EPC = FAULT_PC + 4`
73			`ESR = SR`
74			`PC = ISR_VECTOR + 0x800`
75			`SR = 0`
76

Browse

Tools

Subversion Repositories altor32

[/] [altor32/] [trunk/] [docs/] [altor_vectors.md] - Blame information for rev 41