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//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.1
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2014
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
 
//-----------------------------------------------------------------
// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)
//-----------------------------------------------------------------
module cpu
(
    // General
    input               clk_i /*verilator public*/,
    input               rst_i /*verilator public*/,
 
    input               intr_i /*verilator public*/,
    input               nmi_i /*verilator public*/,
    output              fault_o /*verilator public*/,
    output              break_o /*verilator public*/,
 
    // Instruction memory
    output [31:0]       imem_addr_o /*verilator public*/,
    input [31:0]        imem_dat_i /*verilator public*/,
    output [2:0]        imem_cti_o /*verilator public*/,
    output              imem_cyc_o /*verilator public*/,
    output              imem_stb_o /*verilator public*/,
    input               imem_stall_i/*verilator public*/,
    input               imem_ack_i/*verilator public*/,
 
    // Data memory
    output [31:0]       dmem_addr_o /*verilator public*/,
    output [31:0]       dmem_dat_o /*verilator public*/,
    input [31:0]        dmem_dat_i /*verilator public*/,
    output [3:0]        dmem_sel_o /*verilator public*/,
    output [2:0]        dmem_cti_o /*verilator public*/,
    output              dmem_cyc_o /*verilator public*/,
    output              dmem_we_o /*verilator public*/,
    output              dmem_stb_o /*verilator public*/,
    input               dmem_stall_i/*verilator public*/,
    input               dmem_ack_i/*verilator public*/
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter           BOOT_VECTOR         = 32'h00000000;
parameter           ISR_VECTOR          = 32'h00000000;
parameter           REGISTER_FILE_TYPE  = "SIMULATION";
parameter           ENABLE_ICACHE       = "ENABLED";
parameter           ENABLE_DCACHE       = "DISABLED";
parameter           SUPPORT_32REGS      = "ENABLED";
parameter           PIPELINED_FETCH     = "ENABLED";
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
 
// Register number (rA)
wire [4:0]  w_ra;
 
// Register number (rB)
wire [4:0]  w_rb;
 
// Destination register number (pre execute stage)
wire [4:0]  w_rd;
 
// Destination register number (post execute stage)
wire [4:0]  w_e_rd;
 
// Register value (rA)
wire [31:0] w_reg_ra;
 
// Register value (rB)
wire [31:0] w_reg_rb;
 
// Current opcode
wire [31:0] w_d_opcode;
wire [31:0] w_d_pc;
wire        w_d_valid;
 
wire [31:0] w_e_opcode;
 
// Register writeback value
wire [4:0]  w_wb_rd;
wire [31:0] w_wb_reg_rd;
 
// Register writeback enable
wire        w_wb_write_rd;
 
// Result from execute
wire [31:0] w_e_result;
wire        w_e_mult;
wire [31:0] w_e_mult_result;
 
// Branch request
wire        w_e_branch;
wire [31:0] w_e_branch_pc;
wire        w_e_stall;
 
wire        icache_rd;
wire [31:0] icache_pc;
wire [31:0] icache_inst;
wire        icache_valid;
wire        icache_invalidate;
 
wire [31:0] dcache_addr;
wire [31:0] dcache_data_o;
wire [31:0] dcache_data_i;
wire [3:0]  dcache_sel;
wire        dcache_we;
wire        dcache_stb;
wire        dcache_cyc;
wire        dcache_ack;
wire        dcache_stall;
wire        dcache_flush;
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
 
// Instruction Cache
generate
if (ENABLE_ICACHE == "ENABLED")
begin : ICACHE
    // Instruction cache
    altor32_icache
    #(
        .BOOT_VECTOR(BOOT_VECTOR)
    )
    u_icache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        // Processor interface
        .rd_i(icache_rd),
        .pc_i(icache_pc),
        .instruction_o(icache_inst),
        .valid_o(icache_valid),
        .invalidate_i(icache_invalidate),
 
        // Instruction memory
        .wbm_addr_o(imem_addr_o),
        .wbm_dat_i(imem_dat_i),
        .wbm_cti_o(imem_cti_o),
        .wbm_cyc_o(imem_cyc_o),
        .wbm_stb_o(imem_stb_o),
        .wbm_stall_i(imem_stall_i),
        .wbm_ack_i(imem_ack_i)
    );
end
else
begin : NO_ICACHE
    // No instruction cache
    altor32_noicache
    u_icache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        // Processor interface
        .rd_i(icache_rd),
        .pc_i(icache_pc),
        .instruction_o(icache_inst),
        .valid_o(icache_valid),
        .invalidate_i(icache_invalidate),
 
        // Instruction memory
        .wbm_addr_o(imem_addr_o),
        .wbm_dat_i(imem_dat_i),
        .wbm_cti_o(imem_cti_o),
        .wbm_cyc_o(imem_cyc_o),
        .wbm_stb_o(imem_stb_o),
        .wbm_stall_i(imem_stall_i),
        .wbm_ack_i(imem_ack_i)
    );
end
endgenerate
 
// Instruction Fetch
altor32_fetch
#(
    .BOOT_VECTOR(BOOT_VECTOR),
    .PIPELINED_FETCH(PIPELINED_FETCH)
)
u_fetch
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    // Instruction memory
    .pc_o(icache_pc),
    .data_i(icache_inst),
    .fetch_o(icache_rd),
    .data_valid_i(icache_valid),
 
    // Fetched opcode
    .opcode_o(w_d_opcode),
    .opcode_pc_o(w_d_pc),
    .opcode_valid_o(w_d_valid),
 
    // Branch target
    .branch_i(w_e_branch),
    .branch_pc_i(w_e_branch_pc),
    .stall_i(w_e_stall),
 
    // Decoded register details
    .ra_o(w_ra),
    .rb_o(w_rb),
    .rd_o(w_rd)
);
 
// Register file
generate
if (REGISTER_FILE_TYPE == "XILINX")
begin : REGFILE_XIL
    altor32_regfile_xil
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    reg_bank
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(w_wb_write_rd),
 
        // Tri-port
        .rs_i(w_ra),
        .rt_i(w_rb),
        .rd_i(w_wb_rd),
        .reg_rs_o(w_reg_ra),
        .reg_rt_o(w_reg_rb),
        .reg_rd_i(w_wb_reg_rd)
    );
end
else if (REGISTER_FILE_TYPE == "ALTERA")
begin : REGFILE_ALT
    altor32_regfile_alt
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    reg_bank
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(w_wb_write_rd),
 
        // Tri-port
        .rs_i(w_ra),
        .rt_i(w_rb),
        .rd_i(w_wb_rd),
        .reg_rs_o(w_reg_ra),
        .reg_rt_o(w_reg_rb),
        .reg_rd_i(w_wb_reg_rd)
    );
end
else
begin : REGFILE_SIM
    altor32_regfile_sim
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    reg_bank
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(w_wb_write_rd),
 
        // Tri-port
        .rs_i(w_ra),
        .rt_i(w_rb),
        .rd_i(w_wb_rd),
        .reg_rs_o(w_reg_ra),
        .reg_rt_o(w_reg_rb),
        .reg_rd_i(w_wb_reg_rd)
    );
end
endgenerate
 
generate
if (ENABLE_DCACHE == "ENABLED")
begin : DCACHE
    // Data cache
    altor32_dcache
    u_dcache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        .flush_i(dcache_flush),
 
        // Processor interface
        .address_i({dcache_addr[31:2], 2'b00}),
        .data_o(dcache_data_i),
        .data_i(dcache_data_o),
        .we_i(dcache_we),
        .stb_i(dcache_stb),
        .sel_i(dcache_sel),
        .stall_o(dcache_stall),
        .ack_o(dcache_ack),
 
        // Memory interface (slave)
        .mem_addr_o(dmem_addr_o),
        .mem_data_i(dmem_dat_i),
        .mem_data_o(dmem_dat_o),
        .mem_sel_o(dmem_sel_o),
        .mem_we_o(dmem_we_o),
        .mem_stb_o(dmem_stb_o),
        .mem_cyc_o(dmem_cyc_o),
        .mem_cti_o(dmem_cti_o),
        .mem_stall_i(dmem_stall_i),
        .mem_ack_i(dmem_ack_i)
    );
end
else
begin: NO_DCACHE
    // No data cache
    assign dmem_addr_o      = {dcache_addr[31:2], 2'b00};
    assign dmem_dat_o       = dcache_data_o;
    assign dcache_data_i    = dmem_dat_i;
    assign dmem_sel_o       = dcache_sel;
    assign dmem_cyc_o       = dcache_cyc;
    assign dmem_we_o        = dcache_we;
    assign dmem_stb_o       = dcache_stb;
    assign dmem_cti_o       = 3'b111;
    assign dcache_ack       = dmem_ack_i;
    assign dcache_stall     = dmem_stall_i;
end
endgenerate
 
// Execution unit
altor32_exec
#(
    .BOOT_VECTOR(BOOT_VECTOR),
    .ISR_VECTOR(ISR_VECTOR)
)
u_exec
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    .intr_i(intr_i),
    .nmi_i(nmi_i),
 
    // Status
    .fault_o(fault_o),
    .break_o(break_o),
 
    // Cache control
    .icache_flush_o(icache_invalidate),
    .dcache_flush_o(dcache_flush),
 
    // Branch target
    .branch_o(w_e_branch),
    .branch_pc_o(w_e_branch_pc),
    .stall_o(w_e_stall),
 
    // Opcode & arguments
    .opcode_i(w_d_opcode),
    .opcode_pc_i(w_d_pc),
    .opcode_valid_i(w_d_valid),
 
    .reg_ra_i(w_ra),
    .reg_ra_value_i(w_reg_ra),
 
    .reg_rb_i(w_rb),
    .reg_rb_value_i(w_reg_rb),
 
    .reg_rd_i(w_rd),
 
    // Output
    .opcode_o(w_e_opcode),
    .reg_rd_o(w_e_rd),
    .reg_rd_value_o(w_e_result),
    .mult_o(w_e_mult),
    .mult_res_o(w_e_mult_result),
 
    // Register write back bypass
    .wb_rd_i(w_wb_rd),
    .wb_rd_value_i(w_wb_reg_rd),
 
    // Memory Interface
    .dmem_addr_o(dcache_addr),
    .dmem_data_out_o(dcache_data_o),
    .dmem_data_in_i(dcache_data_i),
    .dmem_sel_o(dcache_sel),
    .dmem_we_o(dcache_we),
    .dmem_stb_o(dcache_stb),
    .dmem_cyc_o(dcache_cyc),
    .dmem_stall_i(dcache_stall),
    .dmem_ack_i(dcache_ack)
);
 
// Register file writeback
altor32_writeback
u_wb
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    // Opcode
    .opcode_i(w_e_opcode),
 
    // Register target
    .rd_i(w_e_rd),
 
    // ALU result
    .alu_result_i(w_e_result),
 
    // Memory load result
    .mem_result_i(dcache_data_i),
    .mem_offset_i(dcache_addr[1:0]),
    .mem_ready_i(dcache_ack),
 
    // Multiplier result
    .mult_i(w_e_mult),
    .mult_result_i(w_e_mult_result),
 
    // Outputs
    .write_enable_o(w_wb_write_rd),
    .write_addr_o(w_wb_rd),
    .write_data_o(w_wb_reg_rd)
);
 
//-------------------------------------------------------------------
// Hooks for debug
//-------------------------------------------------------------------
`ifdef verilator
   function [31:0] get_pc;
      // verilator public
      get_pc = w_d_pc;
   endfunction
   function get_fault;
      // verilator public
      get_fault = fault_o;
   endfunction
   function get_break;
      // verilator public
      get_break = break_o;
   endfunction
`endif
 
endmodule

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4	36	ultra_embe	`// V2.1`
5	27	ultra_embe	`// Ultra-Embedded.com`
6	36	ultra_embe	`// Copyright 2011 - 2014`
7	27	ultra_embe	`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13			`// Copyright (C) 2011 - 2013 Ultra-Embedded.com`
14			`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// Includes`
40			`//-----------------------------------------------------------------`
41			`include "altor32_defs.v"
42
43			`//-----------------------------------------------------------------`
44	32	ultra_embe	`// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)`
45	27	ultra_embe	`//-----------------------------------------------------------------`
46			`module cpu`
47			`(`
48			`// General`
49			`input clk_i /verilator public/,`
50			`input rst_i /verilator public/,`
51
52			`input intr_i /verilator public/,`
53			`input nmi_i /verilator public/,`
54			`output fault_o /verilator public/,`
55			`output break_o /verilator public/,`
56
57			`// Instruction memory`
58			`output [31:0] imem_addr_o /verilator public/,`
59	32	ultra_embe	`input [31:0] imem_dat_i /verilator public/,`
60			`output [2:0] imem_cti_o /verilator public/,`
61			`output imem_cyc_o /verilator public/,`
62			`output imem_stb_o /verilator public/,`
63			`input imem_stall_i/verilator public/,`
64			`input imem_ack_i/verilator public/,`
65	27	ultra_embe
66			`// Data memory`
67			`output [31:0] dmem_addr_o /verilator public/,`
68	32	ultra_embe	`output [31:0] dmem_dat_o /verilator public/,`
69			`input [31:0] dmem_dat_i /verilator public/,`
70			`output [3:0] dmem_sel_o /verilator public/,`
71			`output [2:0] dmem_cti_o /verilator public/,`
72			`output dmem_cyc_o /verilator public/,`
73			`output dmem_we_o /verilator public/,`
74			`output dmem_stb_o /verilator public/,`
75			`input dmem_stall_i/verilator public/,`
76			`input dmem_ack_i/verilator public/`
77	27	ultra_embe	`);`
78
79			`//-----------------------------------------------------------------`
80			`// Params`
81			`//-----------------------------------------------------------------`
82			`parameter BOOT_VECTOR = 32'h00000000;`
83			`parameter ISR_VECTOR = 32'h00000000;`
84			`parameter REGISTER_FILE_TYPE = "SIMULATION";`
85			`parameter ENABLE_ICACHE = "ENABLED";`
86			`parameter ENABLE_DCACHE = "DISABLED";`
87			`parameter SUPPORT_32REGS = "ENABLED";`
88	36	ultra_embe	`parameter PIPELINED_FETCH = "ENABLED";`
89	27	ultra_embe
90			`//-----------------------------------------------------------------`
91			`// Registers / Wires`
92			`//-----------------------------------------------------------------`
93
94			`// Register number (rA)`
95			`wire [4:0] w_ra;`
96
97			`// Register number (rB)`
98			`wire [4:0] w_rb;`
99
100			`// Destination register number (pre execute stage)`
101			`wire [4:0] w_rd;`
102
103			`// Destination register number (post execute stage)`
104			`wire [4:0] w_e_rd;`
105
106			`// Register value (rA)`
107			`wire [31:0] w_reg_ra;`
108
109			`// Register value (rB)`
110			`wire [31:0] w_reg_rb;`
111
112			`// Current opcode`
113			`wire [31:0] w_d_opcode;`
114			`wire [31:0] w_d_pc;`
115			`wire w_d_valid;`
116
117			`wire [31:0] w_e_opcode;`
118
119			`// Register writeback value`
120			`wire [4:0] w_wb_rd;`
121			`wire [31:0] w_wb_reg_rd;`
122
123			`// Register writeback enable`
124			`wire w_wb_write_rd;`
125
126			`// Result from execute`
127			`wire [31:0] w_e_result;`
128			`wire w_e_mult;`
129			`wire [31:0] w_e_mult_result;`
130
131			`// Branch request`
132			`wire w_e_branch;`
133			`wire [31:0] w_e_branch_pc;`
134			`wire w_e_stall;`
135
136			`wire icache_rd;`
137			`wire [31:0] icache_pc;`
138			`wire [31:0] icache_inst;`
139			`wire icache_valid;`
140			`wire icache_invalidate;`
141
142			`wire [31:0] dcache_addr;`
143			`wire [31:0] dcache_data_o;`
144			`wire [31:0] dcache_data_i;`
145	32	ultra_embe	`wire [3:0] dcache_sel;`
146			`wire dcache_we;`
147			`wire dcache_stb;`
148			`wire dcache_cyc;`
149	27	ultra_embe	`wire dcache_ack;`
150	32	ultra_embe	`wire dcache_stall;`
151	27	ultra_embe	`wire dcache_flush;`
152
153			`//-----------------------------------------------------------------`
154			`// Instantiation`
155			`//-----------------------------------------------------------------`
156
157			`// Instruction Cache`
158			`generate`
159			`if (ENABLE_ICACHE == "ENABLED")`
160			`begin : ICACHE`
161			`// Instruction cache`
162			`altor32_icache`
163			`#(`
164			`.BOOT_VECTOR(BOOT_VECTOR)`
165			`)`
166			`u_icache`
167			`(`
168			`.clk_i(clk_i),`
169			`.rst_i(rst_i),`
170
171			`// Processor interface`
172			`.rd_i(icache_rd),`
173			`.pc_i(icache_pc),`
174			`.instruction_o(icache_inst),`
175			`.valid_o(icache_valid),`
176			`.invalidate_i(icache_invalidate),`
177
178			`// Instruction memory`
179	32	ultra_embe	`.wbm_addr_o(imem_addr_o),`
180			`.wbm_dat_i(imem_dat_i),`
181			`.wbm_cti_o(imem_cti_o),`
182			`.wbm_cyc_o(imem_cyc_o),`
183			`.wbm_stb_o(imem_stb_o),`
184			`.wbm_stall_i(imem_stall_i),`
185			`.wbm_ack_i(imem_ack_i)`
186	27	ultra_embe	`);`
187			`end`
188			`else`
189	32	ultra_embe	`begin : NO_ICACHE`
190	27	ultra_embe	`// No instruction cache`
191			`altor32_noicache`
192			`u_icache`
193			`(`
194			`.clk_i(clk_i),`
195			`.rst_i(rst_i),`
196
197			`// Processor interface`
198			`.rd_i(icache_rd),`
199			`.pc_i(icache_pc),`
200			`.instruction_o(icache_inst),`
201			`.valid_o(icache_valid),`
202	36	ultra_embe	`.invalidate_i(icache_invalidate),`
203	27	ultra_embe
204			`// Instruction memory`
205	32	ultra_embe	`.wbm_addr_o(imem_addr_o),`
206			`.wbm_dat_i(imem_dat_i),`
207			`.wbm_cti_o(imem_cti_o),`
208			`.wbm_cyc_o(imem_cyc_o),`
209			`.wbm_stb_o(imem_stb_o),`
210			`.wbm_stall_i(imem_stall_i),`
211			`.wbm_ack_i(imem_ack_i)`
212	27	ultra_embe	`);`
213			`end`
214			`endgenerate`
215
216			`// Instruction Fetch`
217			`altor32_fetch`
218			`#(`
219	36	ultra_embe	`.BOOT_VECTOR(BOOT_VECTOR),`
220			`.PIPELINED_FETCH(PIPELINED_FETCH)`
221	27	ultra_embe	`)`
222			`u_fetch`
223			`(`
224			`// General`
225			`.clk_i(clk_i),`
226			`.rst_i(rst_i),`
227
228			`// Instruction memory`
229			`.pc_o(icache_pc),`
230			`.data_i(icache_inst),`
231			`.fetch_o(icache_rd),`
232			`.data_valid_i(icache_valid),`
233
234			`// Fetched opcode`
235			`.opcode_o(w_d_opcode),`
236			`.opcode_pc_o(w_d_pc),`
237			`.opcode_valid_o(w_d_valid),`
238
239			`// Branch target`
240			`.branch_i(w_e_branch),`
241			`.branch_pc_i(w_e_branch_pc),`
242			`.stall_i(w_e_stall),`
243
244			`// Decoded register details`
245			`.ra_o(w_ra),`
246			`.rb_o(w_rb),`
247			`.rd_o(w_rd)`
248			`);`
249
250			`// Register file`
251			`generate`
252			`if (REGISTER_FILE_TYPE == "XILINX")`
253	32	ultra_embe	`begin : REGFILE_XIL`
254	27	ultra_embe	`altor32_regfile_xil`
255			`#(`
256			`.SUPPORT_32REGS(SUPPORT_32REGS)`
257			`)`
258			`reg_bank`
259			`(`
260			`// Clocking`
261			`.clk_i(clk_i),`
262			`.rst_i(rst_i),`
263			`.wr_i(w_wb_write_rd),`
264
265			`// Tri-port`
266			`.rs_i(w_ra),`
267			`.rt_i(w_rb),`
268			`.rd_i(w_wb_rd),`
269			`.reg_rs_o(w_reg_ra),`
270			`.reg_rt_o(w_reg_rb),`
271			`.reg_rd_i(w_wb_reg_rd)`
272			`);`
273			`end`
274			`else if (REGISTER_FILE_TYPE == "ALTERA")`
275	32	ultra_embe	`begin : REGFILE_ALT`
276	27	ultra_embe	`altor32_regfile_alt`
277			`#(`
278			`.SUPPORT_32REGS(SUPPORT_32REGS)`
279			`)`
280			`reg_bank`
281			`(`
282			`// Clocking`
283			`.clk_i(clk_i),`
284			`.rst_i(rst_i),`
285			`.wr_i(w_wb_write_rd),`
286
287			`// Tri-port`
288			`.rs_i(w_ra),`
289			`.rt_i(w_rb),`
290			`.rd_i(w_wb_rd),`
291			`.reg_rs_o(w_reg_ra),`
292			`.reg_rt_o(w_reg_rb),`
293			`.reg_rd_i(w_wb_reg_rd)`
294			`);`
295			`end`
296			`else`
297	32	ultra_embe	`begin : REGFILE_SIM`
298	27	ultra_embe	`altor32_regfile_sim`
299			`#(`
300			`.SUPPORT_32REGS(SUPPORT_32REGS)`
301			`)`
302			`reg_bank`
303			`(`
304			`// Clocking`
305			`.clk_i(clk_i),`
306			`.rst_i(rst_i),`
307			`.wr_i(w_wb_write_rd),`
308
309			`// Tri-port`
310			`.rs_i(w_ra),`
311			`.rt_i(w_rb),`
312			`.rd_i(w_wb_rd),`
313			`.reg_rs_o(w_reg_ra),`
314			`.reg_rt_o(w_reg_rb),`
315			`.reg_rd_i(w_wb_reg_rd)`
316			`);`
317			`end`
318			`endgenerate`
319
320			`generate`
321			`if (ENABLE_DCACHE == "ENABLED")`
322	32	ultra_embe	`begin : DCACHE`
323	27	ultra_embe	`// Data cache`
324			`altor32_dcache`
325			`u_dcache`
326			`(`
327			`.clk_i(clk_i),`
328			`.rst_i(rst_i),`
329
330			`.flush_i(dcache_flush),`
331
332			`// Processor interface`
333			`.address_i({dcache_addr[31:2], 2'b00}),`
334			`.data_o(dcache_data_i),`
335			`.data_i(dcache_data_o),`
336	32	ultra_embe	`.we_i(dcache_we),`
337			`.stb_i(dcache_stb),`
338			`.sel_i(dcache_sel),`
339			`.stall_o(dcache_stall),`
340	27	ultra_embe	`.ack_o(dcache_ack),`
341
342			`// Memory interface (slave)`
343			`.mem_addr_o(dmem_addr_o),`
344	32	ultra_embe	`.mem_data_i(dmem_dat_i),`
345			`.mem_data_o(dmem_dat_o),`
346			`.mem_sel_o(dmem_sel_o),`
347			`.mem_we_o(dmem_we_o),`
348			`.mem_stb_o(dmem_stb_o),`
349			`.mem_cyc_o(dmem_cyc_o),`
350			`.mem_cti_o(dmem_cti_o),`
351			`.mem_stall_i(dmem_stall_i),`
352	27	ultra_embe	`.mem_ack_i(dmem_ack_i)`
353			`);`
354			`end`
355			`else`
356	32	ultra_embe	`begin: NO_DCACHE`
357	27	ultra_embe	`// No data cache`
358			`assign dmem_addr_o = {dcache_addr[31:2], 2'b00};`
359	32	ultra_embe	`assign dmem_dat_o = dcache_data_o;`
360			`assign dcache_data_i = dmem_dat_i;`
361			`assign dmem_sel_o = dcache_sel;`
362			`assign dmem_cyc_o = dcache_cyc;`
363			`assign dmem_we_o = dcache_we;`
364			`assign dmem_stb_o = dcache_stb;`
365			`assign dmem_cti_o = 3'b111;`
366	27	ultra_embe	`assign dcache_ack = dmem_ack_i;`
367	32	ultra_embe	`assign dcache_stall = dmem_stall_i;`
368	27	ultra_embe	`end`
369			`endgenerate`
370
371			`// Execution unit`
372			`altor32_exec`
373			`#(`
374			`.BOOT_VECTOR(BOOT_VECTOR),`
375			`.ISR_VECTOR(ISR_VECTOR)`
376			`)`
377			`u_exec`
378			`(`
379			`// General`
380			`.clk_i(clk_i),`
381			`.rst_i(rst_i),`
382
383			`.intr_i(intr_i),`
384			`.nmi_i(nmi_i),`
385
386			`// Status`
387			`.fault_o(fault_o),`
388			`.break_o(break_o),`
389
390			`// Cache control`
391			`.icache_flush_o(icache_invalidate),`
392			`.dcache_flush_o(dcache_flush),`
393
394			`// Branch target`
395			`.branch_o(w_e_branch),`
396			`.branch_pc_o(w_e_branch_pc),`
397			`.stall_o(w_e_stall),`
398
399			`// Opcode & arguments`
400			`.opcode_i(w_d_opcode),`
401			`.opcode_pc_i(w_d_pc),`
402			`.opcode_valid_i(w_d_valid),`
403
404			`.reg_ra_i(w_ra),`
405			`.reg_ra_value_i(w_reg_ra),`
406
407			`.reg_rb_i(w_rb),`
408			`.reg_rb_value_i(w_reg_rb),`
409
410			`.reg_rd_i(w_rd),`
411
412			`// Output`
413			`.opcode_o(w_e_opcode),`
414			`.reg_rd_o(w_e_rd),`
415			`.reg_rd_value_o(w_e_result),`
416			`.mult_o(w_e_mult),`
417			`.mult_res_o(w_e_mult_result),`
418
419			`// Register write back bypass`
420			`.wb_rd_i(w_wb_rd),`
421			`.wb_rd_value_i(w_wb_reg_rd),`
422
423			`// Memory Interface`
424			`.dmem_addr_o(dcache_addr),`
425			`.dmem_data_out_o(dcache_data_o),`
426			`.dmem_data_in_i(dcache_data_i),`
427	32	ultra_embe	`.dmem_sel_o(dcache_sel),`
428			`.dmem_we_o(dcache_we),`
429			`.dmem_stb_o(dcache_stb),`
430			`.dmem_cyc_o(dcache_cyc),`
431			`.dmem_stall_i(dcache_stall),`
432	27	ultra_embe	`.dmem_ack_i(dcache_ack)`
433			`);`
434
435			`// Register file writeback`
436			`altor32_writeback`
437			`u_wb`
438			`(`
439			`// General`
440			`.clk_i(clk_i),`
441			`.rst_i(rst_i),`
442
443			`// Opcode`
444			`.opcode_i(w_e_opcode),`
445
446			`// Register target`
447			`.rd_i(w_e_rd),`
448
449			`// ALU result`
450			`.alu_result_i(w_e_result),`
451
452			`// Memory load result`
453			`.mem_result_i(dcache_data_i),`
454			`.mem_offset_i(dcache_addr[1:0]),`
455			`.mem_ready_i(dcache_ack),`
456
457			`// Multiplier result`
458			`.mult_i(w_e_mult),`
459			`.mult_result_i(w_e_mult_result),`
460
461			`// Outputs`
462			`.write_enable_o(w_wb_write_rd),`
463			`.write_addr_o(w_wb_rd),`
464			`.write_data_o(w_wb_reg_rd)`
465			`);`
466
467			`//-------------------------------------------------------------------`
468			`// Hooks for debug`
469			`//-------------------------------------------------------------------`
470			`ifdef verilator
471			`function [31:0] get_pc;`
472			`// verilator public`
473			`get_pc = w_d_pc;`
474			`endfunction`
475			`function get_fault;`
476			`// verilator public`
477			`get_fault = fault_o;`
478			`endfunction`
479			`function get_break;`
480			`// verilator public`
481			`get_break = break_o;`
482			`endfunction`
483			`endif
484
485			`endmodule`

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