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//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.1
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2014
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
 
//-----------------------------------------------------------------
// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)
//-----------------------------------------------------------------
module cpu
(
    // General
    input               clk_i /*verilator public*/,
    input               rst_i /*verilator public*/,
 
    input               intr_i /*verilator public*/,
    input               nmi_i /*verilator public*/,
    output              fault_o /*verilator public*/,
    output              break_o /*verilator public*/,
 
    // Instruction memory
    output [31:0]       imem_addr_o /*verilator public*/,
    input [31:0]        imem_dat_i /*verilator public*/,
    output [2:0]        imem_cti_o /*verilator public*/,
    output              imem_cyc_o /*verilator public*/,
    output              imem_stb_o /*verilator public*/,
    input               imem_stall_i/*verilator public*/,
    input               imem_ack_i/*verilator public*/,
 
    // Data memory
    output [31:0]       dmem_addr_o /*verilator public*/,
    output [31:0]       dmem_dat_o /*verilator public*/,
    input [31:0]        dmem_dat_i /*verilator public*/,
    output [3:0]        dmem_sel_o /*verilator public*/,
    output [2:0]        dmem_cti_o /*verilator public*/,
    output              dmem_cyc_o /*verilator public*/,
    output              dmem_we_o /*verilator public*/,
    output              dmem_stb_o /*verilator public*/,
    input               dmem_stall_i/*verilator public*/,
    input               dmem_ack_i/*verilator public*/
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter           BOOT_VECTOR         = 32'h00000000;
parameter           ISR_VECTOR          = 32'h00000000;
parameter           REGISTER_FILE_TYPE  = "SIMULATION";
parameter           ENABLE_ICACHE       = "ENABLED";
parameter           ENABLE_DCACHE       = "DISABLED";
parameter           SUPPORT_32REGS      = "ENABLED";
parameter           PIPELINED_FETCH     = "ENABLED";
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
 
// Instruction fetch
wire        fetch_rd_w;
wire [31:0] fetch_pc_w;
wire [31:0] fetch_opcode_w;
wire        fetch_valid_w;
 
// Decode opcode / PC / state
wire [31:0] dec_opcode_w;
wire [31:0] dec_opcode_pc_w;
wire        dec_opcode_valid_w;
 
// Register number (rA)
wire [4:0]  dec_ra_w;
 
// Register number (rB)
wire [4:0]  dec_rb_w;
 
// Destination register number (pre execute stage)
wire [4:0]  dec_rd_w;
 
// Register value (rA)
wire [31:0] dec_ra_val_w;
 
// Register value (rB)
wire [31:0] dec_rb_val_w;
 
// Destination register number (post execute stage)
wire [4:0]  ex_rd_w;
 
// Current executing instruction
wire [31:0] ex_opcode_w;
 
// Result from execute
wire [31:0] ex_result_w;
wire [63:0] ex_mult_res_w;
 
// Branch request
wire        ex_branch_w;
wire [31:0] ex_branch_pc_w;
wire        ex_stall_w;
 
// Register writeback value
wire [4:0]  wb_rd_w;
wire [31:0] wb_rd_val_w;
 
// Register writeback enable
wire        wb_rd_write_w;
 
wire [31:0] dcache_addr_w;
wire [31:0] dcache_data_out_w;
wire [31:0] dcache_data_in_w;
wire [3:0]  dcache_sel_w;
wire        dcache_we_w;
wire        dcache_stb_w;
wire        dcache_cyc_w;
wire        dcache_ack_w;
wire        dcache_stall_w;
 
wire        icache_flush_w;
wire        dcache_flush_w;
 
//-----------------------------------------------------------------
// Instruction Cache
//-----------------------------------------------------------------
generate
if (ENABLE_ICACHE == "ENABLED")
begin : ICACHE
    // Instruction cache
    altor32_icache
    #(
        .BOOT_VECTOR(BOOT_VECTOR)
    )
    u_icache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        // Processor interface
        .rd_i(fetch_rd_w),
        .pc_i(fetch_pc_w),
        .instruction_o(fetch_opcode_w),
        .valid_o(fetch_valid_w),
        .invalidate_i(icache_flush_w),
 
        // Instruction memory
        .wbm_addr_o(imem_addr_o),
        .wbm_dat_i(imem_dat_i),
        .wbm_cti_o(imem_cti_o),
        .wbm_cyc_o(imem_cyc_o),
        .wbm_stb_o(imem_stb_o),
        .wbm_stall_i(imem_stall_i),
        .wbm_ack_i(imem_ack_i)
    );
end
//-----------------------------------------------------------------
// No instruction cache
//-----------------------------------------------------------------
else
begin : NO_ICACHE
    altor32_noicache
    u_icache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        // Processor interface
        .rd_i(fetch_rd_w),
        .pc_i(fetch_pc_w),
        .instruction_o(fetch_opcode_w),
        .valid_o(fetch_valid_w),
        .invalidate_i(icache_flush_w),
 
        // Instruction memory
        .wbm_addr_o(imem_addr_o),
        .wbm_dat_i(imem_dat_i),
        .wbm_cti_o(imem_cti_o),
        .wbm_cyc_o(imem_cyc_o),
        .wbm_stb_o(imem_stb_o),
        .wbm_stall_i(imem_stall_i),
        .wbm_ack_i(imem_ack_i)
    );
end
endgenerate
 
//-----------------------------------------------------------------
// Instruction Fetch
//-----------------------------------------------------------------
altor32_fetch
#(
    .BOOT_VECTOR(BOOT_VECTOR),
    .PIPELINED_FETCH(PIPELINED_FETCH)
)
u_fetch
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    // Instruction memory
    .pc_o(fetch_pc_w),
    .data_i(fetch_opcode_w),
    .fetch_o(fetch_rd_w),
    .data_valid_i(fetch_valid_w),
 
    // Fetched opcode
    .opcode_o(dec_opcode_w),
    .opcode_pc_o(dec_opcode_pc_w),
    .opcode_valid_o(dec_opcode_valid_w),
 
    // Branch target
    .branch_i(ex_branch_w),
    .branch_pc_i(ex_branch_pc_w),
    .stall_i(ex_stall_w),
 
    // Decoded register details
    .ra_o(dec_ra_w),
    .rb_o(dec_rb_w),
    .rd_o(dec_rd_w)
);
 
//-----------------------------------------------------------------
// [Xilinx] Register file
//-----------------------------------------------------------------
generate
if (REGISTER_FILE_TYPE == "XILINX")
begin : REGFILE_XIL
    altor32_regfile_xil
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    u_regfile
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(wb_rd_write_w),
 
        // Tri-port
        .ra_i(dec_ra_w),
        .rb_i(dec_rb_w),
        .rd_i(wb_rd_w),
        .reg_ra_o(dec_ra_val_w),
        .reg_rb_o(dec_rb_val_w),
        .reg_rd_i(wb_rd_val_w)
    );
end
//-----------------------------------------------------------------
// [Altera] Register file
//-----------------------------------------------------------------
else if (REGISTER_FILE_TYPE == "ALTERA")
begin : REGFILE_ALT
    altor32_regfile_alt
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    u_regfile
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(wb_rd_write_w),
 
        // Tri-port
        .ra_i(dec_ra_w),
        .rb_i(dec_rb_w),
        .rd_i(wb_rd_w),
        .reg_ra_o(dec_ra_val_w),
        .reg_rb_o(dec_rb_val_w),
        .reg_rd_i(wb_rd_val_w)
    );
end
//-----------------------------------------------------------------
// [Simulation] Register file
//-----------------------------------------------------------------
else
begin : REGFILE_SIM
    altor32_regfile_sim
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    u_regfile
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(wb_rd_write_w),
 
        // Tri-port
        .ra_i(dec_ra_w),
        .rb_i(dec_rb_w),
        .rd_i(wb_rd_w),
        .reg_ra_o(dec_ra_val_w),
        .reg_rb_o(dec_rb_val_w),
        .reg_rd_i(wb_rd_val_w)
    );
end
endgenerate
 
//-----------------------------------------------------------------
// Data cache
//-----------------------------------------------------------------
generate
if (ENABLE_DCACHE == "ENABLED")
begin : DCACHE
    altor32_dcache
    u_dcache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        .flush_i(dcache_flush_w),
 
        // Processor interface
        .address_i({dcache_addr_w[31:2], 2'b00}),
        .data_o(dcache_data_in_w),
        .data_i(dcache_data_out_w),
        .we_i(dcache_we_w),
        .stb_i(dcache_stb_w),
        .sel_i(dcache_sel_w),
        .stall_o(dcache_stall_w),
        .ack_o(dcache_ack_w),
 
        // Memory interface (slave)
        .mem_addr_o(dmem_addr_o),
        .mem_data_i(dmem_dat_i),
        .mem_data_o(dmem_dat_o),
        .mem_sel_o(dmem_sel_o),
        .mem_we_o(dmem_we_o),
        .mem_stb_o(dmem_stb_o),
        .mem_cyc_o(dmem_cyc_o),
        .mem_cti_o(dmem_cti_o),
        .mem_stall_i(dmem_stall_i),
        .mem_ack_i(dmem_ack_i)
    );
end
//-----------------------------------------------------------------
// No data cache
//-----------------------------------------------------------------
else
begin: NO_DCACHE
    assign dmem_addr_o      = {dcache_addr_w[31:2], 2'b00};
    assign dmem_dat_o       = dcache_data_out_w;
    assign dcache_data_in_w = dmem_dat_i;
    assign dmem_sel_o       = dcache_sel_w;
    assign dmem_cyc_o       = dcache_cyc_w;
    assign dmem_we_o        = dcache_we_w;
    assign dmem_stb_o       = dcache_stb_w;
    assign dmem_cti_o       = 3'b111;
    assign dcache_ack_w     = dmem_ack_i;
    assign dcache_stall_w   = dmem_stall_i;
end
endgenerate
 
//-----------------------------------------------------------------
// Execution unit
//-----------------------------------------------------------------
altor32_exec
#(
    .BOOT_VECTOR(BOOT_VECTOR),
    .ISR_VECTOR(ISR_VECTOR)
)
u_exec
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    .intr_i(intr_i),
    .break_i(nmi_i),
 
    // Status
    .fault_o(fault_o),
    .break_o(break_o),
 
    // Cache control
    .icache_flush_o(icache_flush_w),
    .dcache_flush_o(dcache_flush_w),
 
    // Branch target
    .branch_o(ex_branch_w),
    .branch_pc_o(ex_branch_pc_w),
    .stall_o(ex_stall_w),
 
    // Opcode & arguments
    .opcode_i(dec_opcode_w),
    .opcode_pc_i(dec_opcode_pc_w),
    .opcode_valid_i(dec_opcode_valid_w),
 
    // Operands
    .reg_ra_i(dec_ra_w),
    .reg_ra_value_i(dec_ra_val_w),
    .reg_rb_i(dec_rb_w),
    .reg_rb_value_i(dec_rb_val_w),
    .reg_rd_i(dec_rd_w),
 
    // Output
    .opcode_o(ex_opcode_w),
    .opcode_pc_o(/* not used */),
    .reg_rd_o(ex_rd_w),
    .reg_rd_value_o(ex_result_w),
    .mult_res_o(ex_mult_res_w),
 
    // Register write back bypass
    .wb_rd_i(wb_rd_w),
    .wb_rd_value_i(wb_rd_val_w),
 
    // Memory Interface
    .dmem_addr_o(dcache_addr_w),
    .dmem_data_out_o(dcache_data_out_w),
    .dmem_data_in_i(dcache_data_in_w),
    .dmem_sel_o(dcache_sel_w),
    .dmem_we_o(dcache_we_w),
    .dmem_stb_o(dcache_stb_w),
    .dmem_cyc_o(dcache_cyc_w),
    .dmem_stall_i(dcache_stall_w),
    .dmem_ack_i(dcache_ack_w)
);
 
//-----------------------------------------------------------------
// Register file writeback
//-----------------------------------------------------------------
altor32_writeback
u_wb
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    // Opcode
    .opcode_i(ex_opcode_w),
 
    // Register target
    .rd_i(ex_rd_w),
 
    // ALU result
    .alu_result_i(ex_result_w),
 
    // Memory load result
    .mem_result_i(dcache_data_in_w),
    .mem_offset_i(dcache_addr_w[1:0]),
    .mem_ready_i(dcache_ack_w),
 
    // Multiplier result
    .mult_result_i(ex_mult_res_w),
 
    // Outputs
    .write_enable_o(wb_rd_write_w),
    .write_addr_o(wb_rd_w),
    .write_data_o(wb_rd_val_w)
);
 
//-------------------------------------------------------------------
// Hooks for debug
//-------------------------------------------------------------------
`ifdef verilator
   function [31:0] get_pc;
      // verilator public
      get_pc = dec_opcode_pc_w;
   endfunction
   function get_fault;
      // verilator public
      get_fault = fault_o;
   endfunction
   function get_break;
      // verilator public
      get_break = break_o;
   endfunction
`endif
 
endmodule

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4	36	ultra_embe	`// V2.1`
5	27	ultra_embe	`// Ultra-Embedded.com`
6	36	ultra_embe	`// Copyright 2011 - 2014`
7	27	ultra_embe	`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13	37	ultra_embe	`// Copyright (C) 2011 - 2014 Ultra-Embedded.com`
14	27	ultra_embe	`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// Includes`
40			`//-----------------------------------------------------------------`
41			`include "altor32_defs.v"
42
43			`//-----------------------------------------------------------------`
44	32	ultra_embe	`// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)`
45	27	ultra_embe	`//-----------------------------------------------------------------`
46			`module cpu`
47			`(`
48			`// General`
49			`input clk_i /verilator public/,`
50			`input rst_i /verilator public/,`
51
52			`input intr_i /verilator public/,`
53			`input nmi_i /verilator public/,`
54			`output fault_o /verilator public/,`
55			`output break_o /verilator public/,`
56
57			`// Instruction memory`
58			`output [31:0] imem_addr_o /verilator public/,`
59	32	ultra_embe	`input [31:0] imem_dat_i /verilator public/,`
60			`output [2:0] imem_cti_o /verilator public/,`
61			`output imem_cyc_o /verilator public/,`
62			`output imem_stb_o /verilator public/,`
63			`input imem_stall_i/verilator public/,`
64			`input imem_ack_i/verilator public/,`
65	27	ultra_embe
66			`// Data memory`
67			`output [31:0] dmem_addr_o /verilator public/,`
68	32	ultra_embe	`output [31:0] dmem_dat_o /verilator public/,`
69			`input [31:0] dmem_dat_i /verilator public/,`
70			`output [3:0] dmem_sel_o /verilator public/,`
71			`output [2:0] dmem_cti_o /verilator public/,`
72			`output dmem_cyc_o /verilator public/,`
73			`output dmem_we_o /verilator public/,`
74			`output dmem_stb_o /verilator public/,`
75			`input dmem_stall_i/verilator public/,`
76			`input dmem_ack_i/verilator public/`
77	27	ultra_embe	`);`
78
79			`//-----------------------------------------------------------------`
80			`// Params`
81			`//-----------------------------------------------------------------`
82			`parameter BOOT_VECTOR = 32'h00000000;`
83			`parameter ISR_VECTOR = 32'h00000000;`
84			`parameter REGISTER_FILE_TYPE = "SIMULATION";`
85			`parameter ENABLE_ICACHE = "ENABLED";`
86			`parameter ENABLE_DCACHE = "DISABLED";`
87			`parameter SUPPORT_32REGS = "ENABLED";`
88	36	ultra_embe	`parameter PIPELINED_FETCH = "ENABLED";`
89	27	ultra_embe
90			`//-----------------------------------------------------------------`
91			`// Registers / Wires`
92			`//-----------------------------------------------------------------`
93
94	37	ultra_embe	`// Instruction fetch`
95			`wire fetch_rd_w;`
96			`wire [31:0] fetch_pc_w;`
97			`wire [31:0] fetch_opcode_w;`
98			`wire fetch_valid_w;`
99
100			`// Decode opcode / PC / state`
101			`wire [31:0] dec_opcode_w;`
102			`wire [31:0] dec_opcode_pc_w;`
103			`wire dec_opcode_valid_w;`
104
105	27	ultra_embe	`// Register number (rA)`
106	37	ultra_embe	`wire [4:0] dec_ra_w;`
107	27	ultra_embe
108			`// Register number (rB)`
109	37	ultra_embe	`wire [4:0] dec_rb_w;`
110	27	ultra_embe
111			`// Destination register number (pre execute stage)`
112	37	ultra_embe	`wire [4:0] dec_rd_w;`
113	27	ultra_embe
114			`// Register value (rA)`
115	37	ultra_embe	`wire [31:0] dec_ra_val_w;`
116	27	ultra_embe
117			`// Register value (rB)`
118	37	ultra_embe	`wire [31:0] dec_rb_val_w;`
119	27	ultra_embe
120	37	ultra_embe	`// Destination register number (post execute stage)`
121			`wire [4:0] ex_rd_w;`
122	27	ultra_embe
123	37	ultra_embe	`// Current executing instruction`
124			`wire [31:0] ex_opcode_w;`
125	27	ultra_embe
126	37	ultra_embe	`// Result from execute`
127			`wire [31:0] ex_result_w;`
128	40	ultra_embe	`wire [63:0] ex_mult_res_w;`
129	37	ultra_embe
130			`// Branch request`
131			`wire ex_branch_w;`
132			`wire [31:0] ex_branch_pc_w;`
133			`wire ex_stall_w;`
134
135	27	ultra_embe	`// Register writeback value`
136	37	ultra_embe	`wire [4:0] wb_rd_w;`
137			`wire [31:0] wb_rd_val_w;`
138	27	ultra_embe
139			`// Register writeback enable`
140	37	ultra_embe	`wire wb_rd_write_w;`
141	27	ultra_embe
142	37	ultra_embe	`wire [31:0] dcache_addr_w;`
143			`wire [31:0] dcache_data_out_w;`
144			`wire [31:0] dcache_data_in_w;`
145			`wire [3:0] dcache_sel_w;`
146			`wire dcache_we_w;`
147			`wire dcache_stb_w;`
148			`wire dcache_cyc_w;`
149			`wire dcache_ack_w;`
150			`wire dcache_stall_w;`
151	27	ultra_embe
152	37	ultra_embe	`wire icache_flush_w;`
153			`wire dcache_flush_w;`
154	27	ultra_embe
155			`//-----------------------------------------------------------------`
156	37	ultra_embe	`// Instruction Cache`
157	27	ultra_embe	`//-----------------------------------------------------------------`
158			`generate`
159			`if (ENABLE_ICACHE == "ENABLED")`
160			`begin : ICACHE`
161			`// Instruction cache`
162			`altor32_icache`
163			`#(`
164			`.BOOT_VECTOR(BOOT_VECTOR)`
165			`)`
166			`u_icache`
167			`(`
168			`.clk_i(clk_i),`
169			`.rst_i(rst_i),`
170
171			`// Processor interface`
172	37	ultra_embe	`.rd_i(fetch_rd_w),`
173			`.pc_i(fetch_pc_w),`
174			`.instruction_o(fetch_opcode_w),`
175			`.valid_o(fetch_valid_w),`
176			`.invalidate_i(icache_flush_w),`
177	27	ultra_embe
178			`// Instruction memory`
179	32	ultra_embe	`.wbm_addr_o(imem_addr_o),`
180			`.wbm_dat_i(imem_dat_i),`
181			`.wbm_cti_o(imem_cti_o),`
182			`.wbm_cyc_o(imem_cyc_o),`
183			`.wbm_stb_o(imem_stb_o),`
184			`.wbm_stall_i(imem_stall_i),`
185			`.wbm_ack_i(imem_ack_i)`
186	27	ultra_embe	`);`
187			`end`
188	37	ultra_embe	`//-----------------------------------------------------------------`
189			`// No instruction cache`
190			`//-----------------------------------------------------------------`
191	27	ultra_embe	`else`
192	32	ultra_embe	`begin : NO_ICACHE`
193	27	ultra_embe	`altor32_noicache`
194			`u_icache`
195			`(`
196			`.clk_i(clk_i),`
197			`.rst_i(rst_i),`
198
199			`// Processor interface`
200	37	ultra_embe	`.rd_i(fetch_rd_w),`
201			`.pc_i(fetch_pc_w),`
202			`.instruction_o(fetch_opcode_w),`
203			`.valid_o(fetch_valid_w),`
204			`.invalidate_i(icache_flush_w),`
205	27	ultra_embe
206			`// Instruction memory`
207	32	ultra_embe	`.wbm_addr_o(imem_addr_o),`
208			`.wbm_dat_i(imem_dat_i),`
209			`.wbm_cti_o(imem_cti_o),`
210			`.wbm_cyc_o(imem_cyc_o),`
211			`.wbm_stb_o(imem_stb_o),`
212			`.wbm_stall_i(imem_stall_i),`
213			`.wbm_ack_i(imem_ack_i)`
214	27	ultra_embe	`);`
215			`end`
216			`endgenerate`
217
218	37	ultra_embe	`//-----------------------------------------------------------------`
219	27	ultra_embe	`// Instruction Fetch`
220	37	ultra_embe	`//-----------------------------------------------------------------`
221	27	ultra_embe	`altor32_fetch`
222			`#(`
223	36	ultra_embe	`.BOOT_VECTOR(BOOT_VECTOR),`
224			`.PIPELINED_FETCH(PIPELINED_FETCH)`
225	27	ultra_embe	`)`
226			`u_fetch`
227			`(`
228			`// General`
229			`.clk_i(clk_i),`
230			`.rst_i(rst_i),`
231
232			`// Instruction memory`
233	37	ultra_embe	`.pc_o(fetch_pc_w),`
234			`.data_i(fetch_opcode_w),`
235			`.fetch_o(fetch_rd_w),`
236			`.data_valid_i(fetch_valid_w),`
237	27	ultra_embe
238			`// Fetched opcode`
239	37	ultra_embe	`.opcode_o(dec_opcode_w),`
240			`.opcode_pc_o(dec_opcode_pc_w),`
241			`.opcode_valid_o(dec_opcode_valid_w),`
242	27	ultra_embe
243			`// Branch target`
244	37	ultra_embe	`.branch_i(ex_branch_w),`
245			`.branch_pc_i(ex_branch_pc_w),`
246			`.stall_i(ex_stall_w),`
247	27	ultra_embe
248			`// Decoded register details`
249	37	ultra_embe	`.ra_o(dec_ra_w),`
250			`.rb_o(dec_rb_w),`
251			`.rd_o(dec_rd_w)`
252	27	ultra_embe	`);`
253
254	37	ultra_embe	`//-----------------------------------------------------------------`
255			`// [Xilinx] Register file`
256			`//-----------------------------------------------------------------`
257	27	ultra_embe	`generate`
258			`if (REGISTER_FILE_TYPE == "XILINX")`
259	32	ultra_embe	`begin : REGFILE_XIL`
260	27	ultra_embe	`altor32_regfile_xil`
261			`#(`
262			`.SUPPORT_32REGS(SUPPORT_32REGS)`
263			`)`
264	37	ultra_embe	`u_regfile`
265	27	ultra_embe	`(`
266			`// Clocking`
267			`.clk_i(clk_i),`
268			`.rst_i(rst_i),`
269	37	ultra_embe	`.wr_i(wb_rd_write_w),`
270	27	ultra_embe
271			`// Tri-port`
272	37	ultra_embe	`.ra_i(dec_ra_w),`
273			`.rb_i(dec_rb_w),`
274			`.rd_i(wb_rd_w),`
275			`.reg_ra_o(dec_ra_val_w),`
276			`.reg_rb_o(dec_rb_val_w),`
277			`.reg_rd_i(wb_rd_val_w)`
278	27	ultra_embe	`);`
279			`end`
280	37	ultra_embe	`//-----------------------------------------------------------------`
281			`// [Altera] Register file`
282			`//-----------------------------------------------------------------`
283	27	ultra_embe	`else if (REGISTER_FILE_TYPE == "ALTERA")`
284	32	ultra_embe	`begin : REGFILE_ALT`
285	27	ultra_embe	`altor32_regfile_alt`
286			`#(`
287			`.SUPPORT_32REGS(SUPPORT_32REGS)`
288			`)`
289	37	ultra_embe	`u_regfile`
290	27	ultra_embe	`(`
291			`// Clocking`
292			`.clk_i(clk_i),`
293			`.rst_i(rst_i),`
294	37	ultra_embe	`.wr_i(wb_rd_write_w),`
295	27	ultra_embe
296			`// Tri-port`
297	37	ultra_embe	`.ra_i(dec_ra_w),`
298			`.rb_i(dec_rb_w),`
299			`.rd_i(wb_rd_w),`
300			`.reg_ra_o(dec_ra_val_w),`
301			`.reg_rb_o(dec_rb_val_w),`
302			`.reg_rd_i(wb_rd_val_w)`
303	27	ultra_embe	`);`
304			`end`
305	37	ultra_embe	`//-----------------------------------------------------------------`
306			`// [Simulation] Register file`
307			`//-----------------------------------------------------------------`
308	27	ultra_embe	`else`
309	32	ultra_embe	`begin : REGFILE_SIM`
310	27	ultra_embe	`altor32_regfile_sim`
311			`#(`
312			`.SUPPORT_32REGS(SUPPORT_32REGS)`
313			`)`
314	37	ultra_embe	`u_regfile`
315	27	ultra_embe	`(`
316			`// Clocking`
317			`.clk_i(clk_i),`
318			`.rst_i(rst_i),`
319	37	ultra_embe	`.wr_i(wb_rd_write_w),`
320	27	ultra_embe
321			`// Tri-port`
322	37	ultra_embe	`.ra_i(dec_ra_w),`
323			`.rb_i(dec_rb_w),`
324			`.rd_i(wb_rd_w),`
325			`.reg_ra_o(dec_ra_val_w),`
326			`.reg_rb_o(dec_rb_val_w),`
327			`.reg_rd_i(wb_rd_val_w)`
328	27	ultra_embe	`);`
329			`end`
330			`endgenerate`
331
332	37	ultra_embe	`//-----------------------------------------------------------------`
333			`// Data cache`
334			`//-----------------------------------------------------------------`
335	27	ultra_embe	`generate`
336			`if (ENABLE_DCACHE == "ENABLED")`
337	32	ultra_embe	`begin : DCACHE`
338	27	ultra_embe	`altor32_dcache`
339			`u_dcache`
340			`(`
341			`.clk_i(clk_i),`
342			`.rst_i(rst_i),`
343
344	37	ultra_embe	`.flush_i(dcache_flush_w),`
345	27	ultra_embe
346			`// Processor interface`
347	37	ultra_embe	`.address_i({dcache_addr_w[31:2], 2'b00}),`
348			`.data_o(dcache_data_in_w),`
349			`.data_i(dcache_data_out_w),`
350			`.we_i(dcache_we_w),`
351			`.stb_i(dcache_stb_w),`
352			`.sel_i(dcache_sel_w),`
353			`.stall_o(dcache_stall_w),`
354			`.ack_o(dcache_ack_w),`
355	27	ultra_embe
356			`// Memory interface (slave)`
357			`.mem_addr_o(dmem_addr_o),`
358	32	ultra_embe	`.mem_data_i(dmem_dat_i),`
359			`.mem_data_o(dmem_dat_o),`
360			`.mem_sel_o(dmem_sel_o),`
361			`.mem_we_o(dmem_we_o),`
362			`.mem_stb_o(dmem_stb_o),`
363			`.mem_cyc_o(dmem_cyc_o),`
364			`.mem_cti_o(dmem_cti_o),`
365			`.mem_stall_i(dmem_stall_i),`
366	27	ultra_embe	`.mem_ack_i(dmem_ack_i)`
367			`);`
368			`end`
369	37	ultra_embe	`//-----------------------------------------------------------------`
370			`// No data cache`
371			`//-----------------------------------------------------------------`
372	27	ultra_embe	`else`
373	32	ultra_embe	`begin: NO_DCACHE`
374	37	ultra_embe	`assign dmem_addr_o = {dcache_addr_w[31:2], 2'b00};`
375			`assign dmem_dat_o = dcache_data_out_w;`
376			`assign dcache_data_in_w = dmem_dat_i;`
377			`assign dmem_sel_o = dcache_sel_w;`
378			`assign dmem_cyc_o = dcache_cyc_w;`
379			`assign dmem_we_o = dcache_we_w;`
380			`assign dmem_stb_o = dcache_stb_w;`
381	32	ultra_embe	`assign dmem_cti_o = 3'b111;`
382	37	ultra_embe	`assign dcache_ack_w = dmem_ack_i;`
383			`assign dcache_stall_w = dmem_stall_i;`
384	27	ultra_embe	`end`
385			`endgenerate`
386
387	37	ultra_embe	`//-----------------------------------------------------------------`
388	27	ultra_embe	`// Execution unit`
389	37	ultra_embe	`//-----------------------------------------------------------------`
390	27	ultra_embe	`altor32_exec`
391			`#(`
392			`.BOOT_VECTOR(BOOT_VECTOR),`
393			`.ISR_VECTOR(ISR_VECTOR)`
394			`)`
395			`u_exec`
396			`(`
397			`// General`
398			`.clk_i(clk_i),`
399			`.rst_i(rst_i),`
400
401			`.intr_i(intr_i),`
402	44	ultra_embe	`.break_i(nmi_i),`
403	27	ultra_embe
404			`// Status`
405			`.fault_o(fault_o),`
406			`.break_o(break_o),`
407
408			`// Cache control`
409	37	ultra_embe	`.icache_flush_o(icache_flush_w),`
410			`.dcache_flush_o(dcache_flush_w),`
411	27	ultra_embe
412			`// Branch target`
413	37	ultra_embe	`.branch_o(ex_branch_w),`
414			`.branch_pc_o(ex_branch_pc_w),`
415			`.stall_o(ex_stall_w),`
416	27	ultra_embe
417			`// Opcode & arguments`
418	37	ultra_embe	`.opcode_i(dec_opcode_w),`
419			`.opcode_pc_i(dec_opcode_pc_w),`
420			`.opcode_valid_i(dec_opcode_valid_w),`
421	27	ultra_embe
422	37	ultra_embe	`// Operands`
423			`.reg_ra_i(dec_ra_w),`
424			`.reg_ra_value_i(dec_ra_val_w),`
425			`.reg_rb_i(dec_rb_w),`
426			`.reg_rb_value_i(dec_rb_val_w),`
427			`.reg_rd_i(dec_rd_w),`
428	27	ultra_embe
429			`// Output`
430	37	ultra_embe	`.opcode_o(ex_opcode_w),`
431			`.opcode_pc_o(/* not used */),`
432			`.reg_rd_o(ex_rd_w),`
433			`.reg_rd_value_o(ex_result_w),`
434			`.mult_res_o(ex_mult_res_w),`
435	27	ultra_embe
436			`// Register write back bypass`
437	37	ultra_embe	`.wb_rd_i(wb_rd_w),`
438			`.wb_rd_value_i(wb_rd_val_w),`
439	27	ultra_embe
440			`// Memory Interface`
441	37	ultra_embe	`.dmem_addr_o(dcache_addr_w),`
442			`.dmem_data_out_o(dcache_data_out_w),`
443			`.dmem_data_in_i(dcache_data_in_w),`
444			`.dmem_sel_o(dcache_sel_w),`
445			`.dmem_we_o(dcache_we_w),`
446			`.dmem_stb_o(dcache_stb_w),`
447			`.dmem_cyc_o(dcache_cyc_w),`
448			`.dmem_stall_i(dcache_stall_w),`
449			`.dmem_ack_i(dcache_ack_w)`
450	27	ultra_embe	`);`
451
452	37	ultra_embe	`//-----------------------------------------------------------------`
453	27	ultra_embe	`// Register file writeback`
454	37	ultra_embe	`//-----------------------------------------------------------------`
455	27	ultra_embe	`altor32_writeback`
456			`u_wb`
457			`(`
458			`// General`
459			`.clk_i(clk_i),`
460			`.rst_i(rst_i),`
461
462			`// Opcode`
463	37	ultra_embe	`.opcode_i(ex_opcode_w),`
464	27	ultra_embe
465			`// Register target`
466	37	ultra_embe	`.rd_i(ex_rd_w),`
467	27	ultra_embe
468			`// ALU result`
469	37	ultra_embe	`.alu_result_i(ex_result_w),`
470	27	ultra_embe
471			`// Memory load result`
472	37	ultra_embe	`.mem_result_i(dcache_data_in_w),`
473			`.mem_offset_i(dcache_addr_w[1:0]),`
474			`.mem_ready_i(dcache_ack_w),`
475	27	ultra_embe
476			`// Multiplier result`
477	37	ultra_embe	`.mult_result_i(ex_mult_res_w),`
478	27	ultra_embe
479			`// Outputs`
480	37	ultra_embe	`.write_enable_o(wb_rd_write_w),`
481			`.write_addr_o(wb_rd_w),`
482			`.write_data_o(wb_rd_val_w)`
483	27	ultra_embe	`);`
484
485			`//-------------------------------------------------------------------`
486			`// Hooks for debug`
487			`//-------------------------------------------------------------------`
488			`ifdef verilator
489			`function [31:0] get_pc;`
490			`// verilator public`
491	37	ultra_embe	`get_pc = dec_opcode_pc_w;`
492	27	ultra_embe	`endfunction`
493			`function get_fault;`
494			`// verilator public`
495			`get_fault = fault_o;`
496			`endfunction`
497			`function get_break;`
498			`// verilator public`
499			`get_break = break_o;`
500			`endfunction`

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