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//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.1
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2014
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module - ALU
//-----------------------------------------------------------------
module altor32_alu
(
    // ALU operation select
    input [3:0]     op_i        /*verilator public*/,
 
    // Operands
    input [31:0]    a_i         /*verilator public*/,
    input [31:0]    b_i         /*verilator public*/,
    input           c_i         /*verilator public*/,
 
    // Result
    output [31:0]   p_o         /*verilator public*/,
 
    // Carry
    output reg      c_o         /*verilator public*/,
    output reg      c_update_o  /*verilator public*/,
 
    // Comparison    
    output reg      equal_o                /*verilator public*/,
    output reg      greater_than_signed_o  /*verilator public*/,
    output reg      greater_than_o         /*verilator public*/,
    output reg      less_than_signed_o     /*verilator public*/,
    output reg      less_than_o            /*verilator public*/,
    output          flag_update_o          /*verilator public*/
);
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
`include "altor32_funcs.v"
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [31:0]      result_r;
 
reg [31:16]     shift_right_fill_r;
reg [31:0]      shift_right_1_r;
reg [31:0]      shift_right_2_r;
reg [31:0]      shift_right_4_r;
reg [31:0]      shift_right_8_r;
 
reg [31:0]      shift_left_1_r;
reg [31:0]      shift_left_2_r;
reg [31:0]      shift_left_4_r;
reg [31:0]      shift_left_8_r;
 
//-----------------------------------------------------------------
// ALU
//-----------------------------------------------------------------
always @ (op_i or a_i or b_i or c_i)
begin
   case (op_i)
       //----------------------------------------------
       // Shift Left
       //----------------------------------------------   
       `ALU_SHIFTL :
       begin
            if (b_i[0] == 1'b1)
                shift_left_1_r = {a_i[30:0],1'b0};
            else
                shift_left_1_r = a_i;
 
            if (b_i[1] == 1'b1)
                shift_left_2_r = {shift_left_1_r[29:0],2'b00};
            else
                shift_left_2_r = shift_left_1_r;
 
            if (b_i[2] == 1'b1)
                shift_left_4_r = {shift_left_2_r[27:0],4'b0000};
            else
                shift_left_4_r = shift_left_2_r;
 
            if (b_i[3] == 1'b1)
                shift_left_8_r = {shift_left_4_r[23:0],8'b00000000};
            else
                shift_left_8_r = shift_left_4_r;
 
            if (b_i[4] == 1'b1)
                result_r = {shift_left_8_r[15:0],16'b0000000000000000};
            else
                result_r = shift_left_8_r;
 
            c_o        = 1'b0;
            c_update_o = 1'b0;
       end
       //----------------------------------------------
       // Shift Right
       //----------------------------------------------
       `ALU_SHIFTR, `ALU_SHIRTR_ARITH:
       begin
            // Arithmetic shift? Fill with 1's if MSB set
            if (a_i[31] == 1'b1 && op_i == `ALU_SHIRTR_ARITH)
                shift_right_fill_r = 16'b1111111111111111;
            else
                shift_right_fill_r = 16'b0000000000000000;
 
            if (b_i[0] == 1'b1)
                shift_right_1_r = {shift_right_fill_r[31], a_i[31:1]};
            else
                shift_right_1_r = a_i;
 
            if (b_i[1] == 1'b1)
                shift_right_2_r = {shift_right_fill_r[31:30], shift_right_1_r[31:2]};
            else
                shift_right_2_r = shift_right_1_r;
 
            if (b_i[2] == 1'b1)
                shift_right_4_r = {shift_right_fill_r[31:28], shift_right_2_r[31:4]};
            else
                shift_right_4_r = shift_right_2_r;
 
            if (b_i[3] == 1'b1)
                shift_right_8_r = {shift_right_fill_r[31:24], shift_right_4_r[31:8]};
            else
                shift_right_8_r = shift_right_4_r;
 
            if (b_i[4] == 1'b1)
                result_r = {shift_right_fill_r[31:16], shift_right_8_r[31:16]};
            else
                result_r = shift_right_8_r;
 
            c_o        = 1'b0;
            c_update_o = 1'b0;
       end
       //----------------------------------------------
       // Arithmetic
       //----------------------------------------------
       `ALU_ADD :
       begin
            {c_o, result_r} = (a_i + b_i);
            c_update_o      = 1'b1;
       end
       `ALU_ADDC :
       begin
            {c_o, result_r} = (a_i + b_i) + {31'h00000000, c_i};
            c_update_o      = 1'b1;
       end
       `ALU_SUB :
       begin
            result_r      = (a_i - b_i);
            c_o           = 1'b0;
            c_update_o    = 1'b0;
       end
       //----------------------------------------------
       // Logical
       //----------------------------------------------       
       `ALU_AND :
       begin
            result_r      = (a_i & b_i);
            c_o           = 1'b0;
            c_update_o    = 1'b0;
       end
       `ALU_OR  :
       begin
            result_r      = (a_i | b_i);
            c_o           = 1'b0;
            c_update_o    = 1'b0;
       end
       `ALU_XOR :
       begin
            result_r      = (a_i ^ b_i);
            c_o           = 1'b0;
            c_update_o    = 1'b0;
       end
       default  :
       begin
            result_r      = a_i;
            c_o           = 1'b0;
            c_update_o    = 1'b0;
       end
   endcase
end
 
assign p_o    = result_r;
 
//-----------------------------------------------------------------
// Comparisons
//-----------------------------------------------------------------
always @ *
begin
    if (a_i == b_i)
        equal_o = 1'b1;
    else
        equal_o = 1'b0;
 
    if (a_i < b_i)
        less_than_o = 1'b1;
    else
        less_than_o = 1'b0;
 
    if (a_i > b_i)
        greater_than_o = 1'b1;
    else
        greater_than_o = 1'b0;
 
    less_than_signed_o    = less_than_signed(a_i, b_i);
    greater_than_signed_o = ~(less_than_signed_o | equal_o);
end
 
assign flag_update_o = (op_i == `ALU_COMPARE);
 
endmodule

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4	36	ultra_embe	`// V2.1`
5	27	ultra_embe	`// Ultra-Embedded.com`
6	36	ultra_embe	`// Copyright 2011 - 2014`
7	27	ultra_embe	`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13	37	ultra_embe	`// Copyright (C) 2011 - 2014 Ultra-Embedded.com`
14	27	ultra_embe	`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// Module - ALU`
40			`//-----------------------------------------------------------------`
41			`module altor32_alu`
42			`(`
43			`// ALU operation select`
44			`input [3:0] op_i /verilator public/,`
45
46			`// Operands`
47			`input [31:0] a_i /verilator public/,`
48			`input [31:0] b_i /verilator public/,`
49			`input c_i /verilator public/,`
50
51			`// Result`
52			`output [31:0] p_o /verilator public/,`
53
54			`// Carry`
55			`output reg c_o /verilator public/,`
56	36	ultra_embe	`output reg c_update_o /verilator public/,`
57
58			`// Comparison`
59			`output reg equal_o /verilator public/,`
60			`output reg greater_than_signed_o /verilator public/,`
61			`output reg greater_than_o /verilator public/,`
62			`output reg less_than_signed_o /verilator public/,`
63			`output reg less_than_o /verilator public/,`
64			`output flag_update_o /verilator public/`
65	27	ultra_embe	`);`
66
67			`//-----------------------------------------------------------------`
68	36	ultra_embe	`// Includes`
69			`//-----------------------------------------------------------------`
70			`include "altor32_defs.v"
71			`include "altor32_funcs.v"
72
73			`//-----------------------------------------------------------------`
74	27	ultra_embe	`// Registers`
75			`//-----------------------------------------------------------------`
76	37	ultra_embe	`reg [31:0] result_r;`
77	27	ultra_embe
78	37	ultra_embe	`reg [31:16] shift_right_fill_r;`
79			`reg [31:0] shift_right_1_r;`
80			`reg [31:0] shift_right_2_r;`
81			`reg [31:0] shift_right_4_r;`
82			`reg [31:0] shift_right_8_r;`
83	27	ultra_embe
84	37	ultra_embe	`reg [31:0] shift_left_1_r;`
85			`reg [31:0] shift_left_2_r;`
86			`reg [31:0] shift_left_4_r;`
87			`reg [31:0] shift_left_8_r;`
88	27	ultra_embe
89			`//-----------------------------------------------------------------`
90			`// ALU`
91			`//-----------------------------------------------------------------`
92			`always @ (op_i or a_i or b_i or c_i)`
93			`begin`
94			`case (op_i)`
95			`//----------------------------------------------`
96			`// Shift Left`
97			`//----------------------------------------------`
98			`ALU_SHIFTL :
99			`begin`
100			`if (b_i[0] == 1'b1)`
101	37	ultra_embe	`shift_left_1_r = {a_i[30:0],1'b0};`
102	27	ultra_embe	`else`
103	37	ultra_embe	`shift_left_1_r = a_i;`
104	27	ultra_embe
105			`if (b_i[1] == 1'b1)`
106	37	ultra_embe	`shift_left_2_r = {shift_left_1_r[29:0],2'b00};`
107	27	ultra_embe	`else`
108	37	ultra_embe	`shift_left_2_r = shift_left_1_r;`
109	27	ultra_embe
110			`if (b_i[2] == 1'b1)`
111	37	ultra_embe	`shift_left_4_r = {shift_left_2_r[27:0],4'b0000};`
112	27	ultra_embe	`else`
113	37	ultra_embe	`shift_left_4_r = shift_left_2_r;`
114	27	ultra_embe
115			`if (b_i[3] == 1'b1)`
116	37	ultra_embe	`shift_left_8_r = {shift_left_4_r[23:0],8'b00000000};`
117	27	ultra_embe	`else`
118	37	ultra_embe	`shift_left_8_r = shift_left_4_r;`
119	27	ultra_embe
120			`if (b_i[4] == 1'b1)`
121	37	ultra_embe	`result_r = {shift_left_8_r[15:0],16'b0000000000000000};`
122	27	ultra_embe	`else`
123	37	ultra_embe	`result_r = shift_left_8_r;`
124	27	ultra_embe
125			`c_o = 1'b0;`
126			`c_update_o = 1'b0;`
127			`end`
128			`//----------------------------------------------`
129			`// Shift Right`
130			`//----------------------------------------------`
131			`ALU_SHIFTR, `ALU_SHIRTR_ARITH:
132			`begin`
133			`// Arithmetic shift? Fill with 1's if MSB set`
134			if (a_i[31] == 1'b1 && op_i == `ALU_SHIRTR_ARITH)
135	37	ultra_embe	`shift_right_fill_r = 16'b1111111111111111;`
136	27	ultra_embe	`else`
137	37	ultra_embe	`shift_right_fill_r = 16'b0000000000000000;`
138	27	ultra_embe
139			`if (b_i[0] == 1'b1)`
140	37	ultra_embe	`shift_right_1_r = {shift_right_fill_r[31], a_i[31:1]};`
141	27	ultra_embe	`else`
142	37	ultra_embe	`shift_right_1_r = a_i;`
143	27	ultra_embe
144			`if (b_i[1] == 1'b1)`
145	37	ultra_embe	`shift_right_2_r = {shift_right_fill_r[31:30], shift_right_1_r[31:2]};`
146	27	ultra_embe	`else`
147	37	ultra_embe	`shift_right_2_r = shift_right_1_r;`
148	27	ultra_embe
149			`if (b_i[2] == 1'b1)`
150	37	ultra_embe	`shift_right_4_r = {shift_right_fill_r[31:28], shift_right_2_r[31:4]};`
151	27	ultra_embe	`else`
152	37	ultra_embe	`shift_right_4_r = shift_right_2_r;`
153	27	ultra_embe
154			`if (b_i[3] == 1'b1)`
155	37	ultra_embe	`shift_right_8_r = {shift_right_fill_r[31:24], shift_right_4_r[31:8]};`
156	27	ultra_embe	`else`
157	37	ultra_embe	`shift_right_8_r = shift_right_4_r;`
158	27	ultra_embe
159			`if (b_i[4] == 1'b1)`
160	37	ultra_embe	`result_r = {shift_right_fill_r[31:16], shift_right_8_r[31:16]};`
161	27	ultra_embe	`else`
162	37	ultra_embe	`result_r = shift_right_8_r;`
163	27	ultra_embe
164			`c_o = 1'b0;`
165			`c_update_o = 1'b0;`
166			`end`
167			`//----------------------------------------------`
168			`// Arithmetic`
169			`//----------------------------------------------`
170			`ALU_ADD :
171			`begin`
172	37	ultra_embe	`{c_o, result_r} = (a_i + b_i);`
173			`c_update_o = 1'b1;`
174	27	ultra_embe	`end`
175			`ALU_ADDC :
176			`begin`
177	37	ultra_embe	`{c_o, result_r} = (a_i + b_i) + {31'h00000000, c_i};`
178			`c_update_o = 1'b1;`
179	27	ultra_embe	`end`
180			`ALU_SUB :
181			`begin`
182	37	ultra_embe	`result_r = (a_i - b_i);`
183	27	ultra_embe	`c_o = 1'b0;`
184			`c_update_o = 1'b0;`
185			`end`
186			`//----------------------------------------------`
187			`// Logical`
188			`//----------------------------------------------`
189			`ALU_AND :
190			`begin`
191	37	ultra_embe	`result_r = (a_i & b_i);`
192	27	ultra_embe	`c_o = 1'b0;`
193			`c_update_o = 1'b0;`
194			`end`
195			`ALU_OR :
196			`begin`
197	37	ultra_embe	`result_r = (a_i \| b_i);`
198	27	ultra_embe	`c_o = 1'b0;`
199			`c_update_o = 1'b0;`
200			`end`
201			`ALU_XOR :
202			`begin`
203	37	ultra_embe	`result_r = (a_i ^ b_i);`
204	27	ultra_embe	`c_o = 1'b0;`
205			`c_update_o = 1'b0;`
206			`end`
207			`default :`
208			`begin`
209	37	ultra_embe	`result_r = a_i;`
210	27	ultra_embe	`c_o = 1'b0;`
211			`c_update_o = 1'b0;`
212			`end`
213			`endcase`
214			`end`
215
216	37	ultra_embe	`assign p_o = result_r;`
217	27	ultra_embe
218	36	ultra_embe	`//-----------------------------------------------------------------`
219			`// Comparisons`
220			`//-----------------------------------------------------------------`
221			`always @ *`
222			`begin`
223			`if (a_i == b_i)`
224			`equal_o = 1'b1;`
225			`else`
226			`equal_o = 1'b0;`
227
228			`if (a_i < b_i)`
229			`less_than_o = 1'b1;`
230			`else`
231			`less_than_o = 1'b0;`
232
233			`if (a_i > b_i)`
234			`greater_than_o = 1'b1;`
235			`else`
236			`greater_than_o = 1'b0;`
237
238			`less_than_signed_o = less_than_signed(a_i, b_i);`
239			`greater_than_signed_o = ~(less_than_signed_o \| equal_o);`
240			`end`
241
242			assign flag_update_o = (op_i == `ALU_COMPARE);
243
244	27	ultra_embe	`endmodule`

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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_alu.v] - Blame information for rev 37