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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dcache.v] - Blame information for rev 27

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//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.0
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2013
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module - Data Cache (write back)
//-----------------------------------------------------------------
module altor32_dcache
(
    input           clk_i /*verilator public*/,
    input           rst_i /*verilator public*/,
 
    input           flush_i /*verilator public*/,
 
    // Input (CPU)
    input [31:0]    address_i /*verilator public*/,
    output [31:0]   data_o /*verilator public*/,
    input [31:0]    data_i /*verilator public*/,
    input           rd_i /*verilator public*/,
    input [3:0]     wr_i /*verilator public*/,
    output          accept_o /*verilator public*/,
    output          ack_o /*verilator public*/,
 
    // Output (Memory)
    output [31:0]   mem_addr_o /*verilator public*/,
    input [31:0]    mem_data_i /*verilator public*/,
    output [31:0]   mem_data_o /*verilator public*/,
    output          mem_burst_o /*verilator public*/,
    output          mem_rd_o /*verilator public*/,
    output [3:0]    mem_wr_o /*verilator public*/,
    input           mem_accept_i/*verilator public*/,
    input           mem_ack_i/*verilator public*/
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CACHE_LINE_SIZE_WIDTH     = 5; /* 5-bits -> 32 entries */
parameter CACHE_LINE_SIZE_BYTES     = 2 ** CACHE_LINE_SIZE_WIDTH; /* 32 bytes / 8 words per line */
parameter CACHE_LINE_ADDR_WIDTH     = 8; /* 256 lines */
parameter CACHE_LINE_WORDS_IDX_MAX  = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit = 8 words */
parameter CACHE_TAG_ENTRIES         = 2 ** CACHE_LINE_ADDR_WIDTH ; /* 256 tag entries */
parameter CACHE_DSIZE               = CACHE_LINE_ADDR_WIDTH * CACHE_LINE_SIZE_BYTES; /* 8KB data */
parameter CACHE_DWIDTH              = CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 2; /* 11-bits */
 
parameter CACHE_TAG_WIDTH           = 16; /* 16-bit tag entry size */
parameter CACHE_TAG_LINE_ADDR_WIDTH = CACHE_TAG_WIDTH - 2; /* 14 bits of data (tag entry size minus valid/dirty bit) */
 
parameter CACHE_TAG_ADDR_LOW        = CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH;
parameter CACHE_TAG_ADDR_HIGH       = CACHE_TAG_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH - 1;
 
// Tag fields
parameter CACHE_TAG_DIRTY_BIT       = 14;
parameter CACHE_TAG_VALID_BIT       = 15;
parameter ADDR_NO_CACHE_BIT         = 25;
parameter ADDR_CACHE_BYPASS_BIT     = 31;
 
//  31          16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
// |--------------|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
//  +--------------------+   +-------------------+   +-----------+      
//    Tag entry                     Line address         Address 
//       (15-bits)                    (8-bits)           within line 
//                                                       (5-bits)
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [CACHE_LINE_ADDR_WIDTH-1:0] tag_entry;
wire [CACHE_TAG_WIDTH-1:0]       tag_data_out;
reg  [CACHE_TAG_WIDTH-1:0]       tag_data_in;
reg                              tag_wr;
 
wire [CACHE_DWIDTH-1:0]          cache_address;
wire [31:0]                      cache_data_r;
reg [31:0]                       cache_data_w;
reg [3:0]                        cache_wr;
 
wire [31:2]                      cache_update_addr;
wire [31:0]                      cache_update_data_w;
wire [31:0]                      cache_update_data_r;
wire                             cache_update_wr;
 
reg                              ack;
 
reg                              fill;
reg                              evict;
wire                             done;
 
reg [31:0]                       data_w;
wire [31:0]                      data_r;
reg                              data_rd;
reg [3:0]                        data_wr;
 
reg                              req_rd;
reg [3:0]                        req_wr;
reg                              req_ack;
reg [31:0]                       req_address;
 
reg                              req_flush;
reg                              flush_single;
 
wire [31:0]                      line_address;
 
wire [31:0]                      muxed_address = (state == STATE_IDLE) ? address_i : req_address;
 
// Current state
parameter STATE_IDLE        = 0;
parameter STATE_SINGLE      = 1;
parameter STATE_CHECK       = 2;
parameter STATE_FETCH       = 3;
parameter STATE_WAIT        = 4;
parameter STATE_WAIT2       = 5;
parameter STATE_WRITE       = 6;
parameter STATE_SINGLE_READY= 7;
parameter STATE_EVICTING    = 8;
parameter STATE_UPDATE      = 9;
parameter STATE_FLUSH1      = 10;
parameter STATE_FLUSH2      = 11;
parameter STATE_FLUSH3      = 12;
parameter STATE_FLUSH4      = 13;
reg [3:0] state;
 
assign tag_entry               = muxed_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
assign cache_address           = {tag_entry, muxed_address[CACHE_LINE_SIZE_WIDTH-1:2]};
 
assign data_o                  = (state == STATE_SINGLE_READY) ? data_r : cache_data_r;
assign accept_o                = (state == STATE_IDLE);
 
 
wire valid                     = tag_data_out[CACHE_TAG_VALID_BIT];
wire dirty                     = tag_data_out[CACHE_TAG_DIRTY_BIT];
 
// Access is cacheable?
wire cacheable                 = ~muxed_address[ADDR_NO_CACHE_BIT] & ~muxed_address[ADDR_CACHE_BYPASS_BIT];
 
// Cache hit?
wire hit                       = cacheable & valid & (muxed_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] == tag_data_out[13:0]) & (state == STATE_CHECK);
 
assign ack_o                   = ack | hit;
 
assign line_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] = tag_entry;
assign line_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] = tag_data_out[13:0];
assign line_address[CACHE_LINE_SIZE_WIDTH-1:0] = {CACHE_LINE_SIZE_WIDTH{1'b0}};
 
//-----------------------------------------------------------------
// Control logic
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        data_w          <= 32'h00000000;
        data_wr         <= 4'h0;
        data_rd         <= 1'b0;
        req_address     <= 32'h00000000;
        req_ack         <= 1'b0;
        req_wr          <= 4'h0;
        req_rd          <= 1'b0;
        tag_wr          <= 1'b0;
        req_flush       <= 1'b0;
        flush_single    <= 1'b0;
        fill            <= 1'b0;
        evict           <= 1'b0;
        cache_data_w    <= 32'h00000000;
        cache_wr        <= 4'b0;
        ack             <= 1'b0;
        state           <= STATE_IDLE;
   end
   else
   begin
        ack             <= 1'b0;
        tag_wr          <= 1'b0;
        fill            <= 1'b0;
        evict           <= 1'b0;
        cache_wr        <= 4'b0;
        data_wr         <= 4'b0;
        data_rd         <= 1'b0;
 
        if (flush_i)
            req_flush       <= 1'b1;
 
        case (state)
 
            //-----------------------------------------
            // IDLE
            //-----------------------------------------
            STATE_IDLE :
            begin
                // Read (uncacheable)
                if (rd_i & ~cacheable)
                begin
                    // Start read single from memory
                    req_address <= address_i;
                    req_address[ADDR_CACHE_BYPASS_BIT] <= 1'b0;
                    data_rd     <= 1'b1;
                    req_rd      <= 1'b1;
                    req_wr      <= 4'b0;
                    req_ack     <= 1'b1;
                    state       <= STATE_SINGLE;
                end
                // Read (cacheable)
                else if (rd_i)
                begin
                    req_address <= address_i;
                    req_rd      <= 1'b1;
                    req_wr      <= 4'b0;
                    req_ack     <= 1'b1;
                    state       <= STATE_CHECK;
                end
                // Write (uncacheable)
                else if (wr_i != 4'b0000 & ~cacheable)
                begin
                    // Perform write single
                    req_address <= address_i;
                    req_address[ADDR_CACHE_BYPASS_BIT] <= 1'b0;
                    data_w      <= data_i;
                    data_wr     <= wr_i;
                    req_wr      <= wr_i;
                    req_rd      <= 1'b0;
                    req_ack     <= 1'b1;
                    state       <= STATE_SINGLE;
                end
                // Write (cacheable)
                else if (wr_i != 4'b0000)
                begin
                    req_address <= address_i;
                    data_w      <= data_i;
                    req_wr      <= wr_i;
                    req_rd      <= 1'b0;
                    req_ack     <= 1'b0;
 
                    // Early ACK
                    ack         <= 1'b1;
 
                    state       <= STATE_WRITE;
                end
                // Cache flush request
                else if (flush_i | req_flush)
                begin
                    // Set to first line address
                    req_address <= 32'h00000000;
                    req_flush   <= 1'b0;
                    req_ack     <= 1'b0;
                    flush_single<= 1'b0;
                    state       <= STATE_FLUSH2;
                end
            end
            //-----------------------------------------
            // WRITE - Wait for write-thru to complete
            //-----------------------------------------
            STATE_WRITE :
            begin
                // Cache hit
                if (valid &&
                    (req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] == tag_data_out[13:0]))
                begin
                    // Update line already in cache
                    cache_data_w <= data_w;
                    cache_wr     <= req_wr;
 
                    // Mark line as dirty
                    tag_data_in  <= tag_data_out;
                    tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b1;
                    tag_wr       <= 1'b1;
 
                    state        <= STATE_WAIT2;
                end
                // Cache dirty
                else if (valid & dirty)
                begin
                    // Evict cache line
                    evict       <= 1'b1;
                    state       <= STATE_EVICTING;
                end
                // Cache miss
                else
                begin
                    // Update tag memory with this line's details   
                    tag_data_in <= {1'b1, 1'b1, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
                    tag_wr      <= 1'b1;
 
                    // Fill cache line
                    fill        <= 1'b1;
                    state       <= STATE_UPDATE;
                end
            end
            //-----------------------------------------
            // EVICTING - Evicting cache line
            //-----------------------------------------
            STATE_EVICTING:
            begin
                // Data ready from memory?
                if (done)
                begin
                    // Update tag memory with this new line's details   
                    tag_data_in <= {1'b1, 1'b0, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
                    tag_wr      <= 1'b1;
 
                    // Fill cache line
                    fill        <= 1'b1;
 
                    // Evict for read?
                    if (req_rd)
                        state   <= STATE_FETCH;
                    // Evict for write
                    else
                        state   <= STATE_UPDATE;
                end
            end
            //-----------------------------------------
            // UPDATE - Update fetched cache line
            //-----------------------------------------
            STATE_UPDATE:
            begin
                // Data ready from memory?
                if (done)
                begin
                    // Update line already in cache
                    cache_data_w <= data_w;
                    cache_wr     <= req_wr;
 
                    // Mark line as dirty
                    tag_data_in  <= tag_data_out;
                    tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b1;
                    tag_wr       <= 1'b1;
 
                    state        <= STATE_WAIT2;
                end
            end
            //-----------------------------------------
            // CHECK - check cache for hit or miss
            //-----------------------------------------
            STATE_CHECK :
            begin
                // Cache hit
                if (valid &&
                    (req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] == tag_data_out[13:0]))
                begin
                    state       <= STATE_IDLE;
                end
                // Cache dirty
                else if (valid & dirty)
                begin
                    // Evict cache line
                    evict       <= 1'b1;
                    state       <= STATE_EVICTING;
                end
                // Cache miss
                else
                begin
                    // Update tag memory with this line's details   
                    tag_data_in <= {1'b1, 1'b0, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
                    tag_wr      <= 1'b1;
 
                    // Fill cache line
                    fill        <= 1'b1;
                    state       <= STATE_FETCH;
                end
            end
            //-----------------------------------------
            // FETCH_SINGLE - Single access to memory
            //-----------------------------------------
            STATE_SINGLE:
            begin
                // Data ready from memory?
                if (done)
                begin
                    // Single WRITE?
                    if (~req_rd)
                    begin
                        state       <= STATE_SINGLE_READY;
                        ack         <= req_ack;
                    end
                    // Dirty? Write back
                    else if (valid & dirty)
                    begin
                        // Evict cache line
                        evict       <= 1'b1;
                        flush_single<= 1'b1;
                        state       <= STATE_FLUSH4;
                    end
                    // Valid line, invalidate
                    else if (valid)
                    begin
                        tag_data_in  <= tag_data_out;
                        tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
                        tag_wr       <= 1'b1;
 
                        state       <= STATE_SINGLE_READY;
                        ack         <= req_ack;
                    end
                    else
                    begin
                        state       <= STATE_SINGLE_READY;
                        ack         <= req_ack;
                    end
                end
            end
            //-----------------------------------------
            // FETCH - Fetch row from memory
            //-----------------------------------------
            STATE_FETCH :
            begin
                // Cache line filled?
                if (done)
                   state    <= STATE_WAIT;
            end
            //-----------------------------------------
            // WAIT - Wait cycle
            //-----------------------------------------
            STATE_WAIT :
            begin
                // Allow extra wait state to handle write & read collision               
                state   <= STATE_WAIT2;
            end
            //-----------------------------------------
            // WAIT2 - Wait cycle
            //-----------------------------------------
            STATE_WAIT2 :
            begin
                state   <= STATE_IDLE;
                ack     <= req_ack;
            end
            //-----------------------------------------
            // SINGLE_READY - Uncached access ready
            //-----------------------------------------
            STATE_SINGLE_READY :
            begin
                // Allow extra wait state to handle write & read collision               
                state   <= STATE_IDLE;
            end
            //-----------------------------------------
            // FLUSHx - Flush dirty lines & invalidate
            //-----------------------------------------
            STATE_FLUSH1 :
            begin
                if (req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] == {CACHE_LINE_ADDR_WIDTH{1'b1}})
                begin
                    req_ack <= 1'b0;
                    state   <= STATE_WAIT;
                end
                else
                begin
                    // Increment flush line address
                    req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] <=
                    req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] + 1;
 
                    state   <= STATE_FLUSH2;
                end
            end
            //-----------------------------------------
            // FLUSH2 - Wait state
            //-----------------------------------------
            STATE_FLUSH2 :
            begin
                // Allow a cycle to read line state
                state   <= STATE_FLUSH3;
            end
            //-----------------------------------------
            // FLUSH3 - Check if line dirty & flush
            //-----------------------------------------            
            STATE_FLUSH3 :
            begin
                // Dirty line? Evict line first
                if (dirty)
                begin
                    // Evict cache line
                    evict       <= 1'b1;
                    state       <= STATE_FLUSH4;
                end
                // Not dirty? Just invalidate
                else
                begin
                    tag_data_in  <= tag_data_out;
                    tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
                    tag_wr       <= 1'b1;
 
                    if (flush_single)
                        state    <= STATE_WAIT;
                    else
                        state    <= STATE_FLUSH1;
                end
            end
            //-----------------------------------------
            // FLUSH4 - Wait for line flush to complete
            //-----------------------------------------            
            STATE_FLUSH4 :
            begin
                // Cache line filled?
                if (done)
                begin
                    // Invalidate line
                    tag_data_in  <= tag_data_out;
                    tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
                    tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b0;
                    tag_wr       <= 1'b1;
 
                    if (flush_single)
                    begin
                        state   <= STATE_SINGLE_READY;
                        ack     <= req_ack;
                    end
                    else
                        state   <= STATE_FLUSH1;
                end
            end
            default:
                ;
           endcase
   end
end
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
 
altor32_dcache_mem_if
#(
    .CACHE_LINE_SIZE_WIDTH(CACHE_LINE_SIZE_WIDTH),
    .CACHE_LINE_WORDS_IDX_MAX(CACHE_LINE_WORDS_IDX_MAX)
)
u_mem_if
(
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    // Cache interface
    .address_i(muxed_address),
    .data_i(data_w),
    .data_o(data_r),
    .fill_i(fill),
    .evict_i(evict),
    .evict_addr_i(line_address),
    .rd_single_i(data_rd),
    .wr_single_i(data_wr),
    .done_o(done),
 
    // Cache memory (fill/evict)
    .cache_addr_o(cache_update_addr),
    .cache_data_o(cache_update_data_w),
    .cache_data_i(cache_update_data_r),
    .cache_wr_o(cache_update_wr),
 
    // Memory interface (slave)
    .mem_addr_o(mem_addr_o),
    .mem_data_i(mem_data_i),
    .mem_data_o(mem_data_o),
    .mem_burst_o(mem_burst_o),
    .mem_rd_o(mem_rd_o),
    .mem_wr_o(mem_wr_o),
    .mem_accept_i(mem_accept_i),
    .mem_ack_i(mem_ack_i)
);
 
// Tag memory    
altor32_ram_sp
#(
    .WIDTH(CACHE_TAG_WIDTH),
    .SIZE(CACHE_LINE_ADDR_WIDTH)
)
u1_tag_mem
(
    .clk_i(clk_i),
    .dat_o(tag_data_out),
    .dat_i(tag_data_in),
    .adr_i(tag_entry),
    .wr_i(tag_wr)
);
 
// Data memory   
altor32_ram_dp
#(
    .WIDTH(8),
    .SIZE(CACHE_DWIDTH)
)
u2_data_mem0
(
    .aclk_i(clk_i),
    .aadr_i(cache_address),
    .adat_o(cache_data_r[7:0]),
    .adat_i(cache_data_w[7:0]),
    .awr_i(cache_wr[0]),
 
    .bclk_i(clk_i),
    .badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
    .bdat_o(cache_update_data_r[7:0]),
    .bdat_i(cache_update_data_w[7:0]),
    .bwr_i(cache_update_wr)
);
 
altor32_ram_dp
#(
    .WIDTH(8),
    .SIZE(CACHE_DWIDTH)
)
u2_data_mem1
(
    .aclk_i(clk_i),
    .aadr_i(cache_address),
    .adat_o(cache_data_r[15:8]),
    .adat_i(cache_data_w[15:8]),
    .awr_i(cache_wr[1]),
 
    .bclk_i(clk_i),
    .badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
    .bdat_o(cache_update_data_r[15:8]),
    .bdat_i(cache_update_data_w[15:8]),
    .bwr_i(cache_update_wr)
);
 
altor32_ram_dp
#(
    .WIDTH(8),
    .SIZE(CACHE_DWIDTH)
)
u2_data_mem2
(
    .aclk_i(clk_i),
    .aadr_i(cache_address),
    .adat_o(cache_data_r[23:16]),
    .adat_i(cache_data_w[23:16]),
    .awr_i(cache_wr[2]),
 
    .bclk_i(clk_i),
    .badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
    .bdat_o(cache_update_data_r[23:16]),
    .bdat_i(cache_update_data_w[23:16]),
    .bwr_i(cache_update_wr)
);
 
altor32_ram_dp
#(
    .WIDTH(8),
    .SIZE(CACHE_DWIDTH)
)
u2_data_mem3
(
    .aclk_i(clk_i),
    .aadr_i(cache_address),
    .adat_o(cache_data_r[31:24]),
    .adat_i(cache_data_w[31:24]),
    .awr_i(cache_wr[3]),
 
    .bclk_i(clk_i),
    .badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
    .bdat_o(cache_update_data_r[31:24]),
    .bdat_i(cache_update_data_w[31:24]),
    .bwr_i(cache_update_wr)
);
 
endmodule

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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dcache.v] - Blame information for rev 27

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4			`// V2.0`
5			`// Ultra-Embedded.com`
6			`// Copyright 2011 - 2013`
7			`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13			`// Copyright (C) 2011 - 2013 Ultra-Embedded.com`
14			`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// Module - Data Cache (write back)`
40			`//-----------------------------------------------------------------`
41			`module altor32_dcache`
42			`(`
43			`input clk_i /verilator public/,`
44			`input rst_i /verilator public/,`
45
46			`input flush_i /verilator public/,`
47
48			`// Input (CPU)`
49			`input [31:0] address_i /verilator public/,`
50			`output [31:0] data_o /verilator public/,`
51			`input [31:0] data_i /verilator public/,`
52			`input rd_i /verilator public/,`
53			`input [3:0] wr_i /verilator public/,`
54			`output accept_o /verilator public/,`
55			`output ack_o /verilator public/,`
56
57			`// Output (Memory)`
58			`output [31:0] mem_addr_o /verilator public/,`
59			`input [31:0] mem_data_i /verilator public/,`
60			`output [31:0] mem_data_o /verilator public/,`
61			`output mem_burst_o /verilator public/,`
62			`output mem_rd_o /verilator public/,`
63			`output [3:0] mem_wr_o /verilator public/,`
64			`input mem_accept_i/verilator public/,`
65			`input mem_ack_i/verilator public/`
66			`);`
67
68			`//-----------------------------------------------------------------`
69			`// Params`
70			`//-----------------------------------------------------------------`
71			`parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */`
72			`parameter CACHE_LINE_SIZE_BYTES = 2 ** CACHE_LINE_SIZE_WIDTH; /* 32 bytes / 8 words per line */`
73			`parameter CACHE_LINE_ADDR_WIDTH = 8; /* 256 lines */`
74			`parameter CACHE_LINE_WORDS_IDX_MAX = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit = 8 words */`
75			`parameter CACHE_TAG_ENTRIES = 2 ** CACHE_LINE_ADDR_WIDTH ; /* 256 tag entries */`
76			`parameter CACHE_DSIZE = CACHE_LINE_ADDR_WIDTH * CACHE_LINE_SIZE_BYTES; /* 8KB data */`
77			`parameter CACHE_DWIDTH = CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 2; /* 11-bits */`
78
79			`parameter CACHE_TAG_WIDTH = 16; /* 16-bit tag entry size */`
80			`parameter CACHE_TAG_LINE_ADDR_WIDTH = CACHE_TAG_WIDTH - 2; /* 14 bits of data (tag entry size minus valid/dirty bit) */`
81
82			`parameter CACHE_TAG_ADDR_LOW = CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH;`
83			`parameter CACHE_TAG_ADDR_HIGH = CACHE_TAG_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH - 1;`
84
85			`// Tag fields`
86			`parameter CACHE_TAG_DIRTY_BIT = 14;`
87			`parameter CACHE_TAG_VALID_BIT = 15;`
88			`parameter ADDR_NO_CACHE_BIT = 25;`
89			`parameter ADDR_CACHE_BYPASS_BIT = 31;`
90
91			`// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00`
92			`// \|--------------\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|`
93			`// +--------------------+ +-------------------+ +-----------+`
94			`// Tag entry Line address Address`
95			`// (15-bits) (8-bits) within line`
96			`// (5-bits)`
97
98			`//-----------------------------------------------------------------`
99			`// Registers / Wires`
100			`//-----------------------------------------------------------------`
101			`wire [CACHE_LINE_ADDR_WIDTH-1:0] tag_entry;`
102			`wire [CACHE_TAG_WIDTH-1:0] tag_data_out;`
103			`reg [CACHE_TAG_WIDTH-1:0] tag_data_in;`
104			`reg tag_wr;`
105
106			`wire [CACHE_DWIDTH-1:0] cache_address;`
107			`wire [31:0] cache_data_r;`
108			`reg [31:0] cache_data_w;`
109			`reg [3:0] cache_wr;`
110
111			`wire [31:2] cache_update_addr;`
112			`wire [31:0] cache_update_data_w;`
113			`wire [31:0] cache_update_data_r;`
114			`wire cache_update_wr;`
115
116			`reg ack;`
117
118			`reg fill;`
119			`reg evict;`
120			`wire done;`
121
122			`reg [31:0] data_w;`
123			`wire [31:0] data_r;`
124			`reg data_rd;`
125			`reg [3:0] data_wr;`
126
127			`reg req_rd;`
128			`reg [3:0] req_wr;`
129			`reg req_ack;`
130			`reg [31:0] req_address;`
131
132			`reg req_flush;`
133			`reg flush_single;`
134
135			`wire [31:0] line_address;`
136
137			`wire [31:0] muxed_address = (state == STATE_IDLE) ? address_i : req_address;`
138
139			`// Current state`
140			`parameter STATE_IDLE = 0;`
141			`parameter STATE_SINGLE = 1;`
142			`parameter STATE_CHECK = 2;`
143			`parameter STATE_FETCH = 3;`
144			`parameter STATE_WAIT = 4;`
145			`parameter STATE_WAIT2 = 5;`
146			`parameter STATE_WRITE = 6;`
147			`parameter STATE_SINGLE_READY= 7;`
148			`parameter STATE_EVICTING = 8;`
149			`parameter STATE_UPDATE = 9;`
150			`parameter STATE_FLUSH1 = 10;`
151			`parameter STATE_FLUSH2 = 11;`
152			`parameter STATE_FLUSH3 = 12;`
153			`parameter STATE_FLUSH4 = 13;`
154			`reg [3:0] state;`
155
156			`assign tag_entry = muxed_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];`
157			`assign cache_address = {tag_entry, muxed_address[CACHE_LINE_SIZE_WIDTH-1:2]};`
158
159			`assign data_o = (state == STATE_SINGLE_READY) ? data_r : cache_data_r;`
160			`assign accept_o = (state == STATE_IDLE);`
161
162
163			`wire valid = tag_data_out[CACHE_TAG_VALID_BIT];`
164			`wire dirty = tag_data_out[CACHE_TAG_DIRTY_BIT];`
165
166			`// Access is cacheable?`
167			`wire cacheable = ~muxed_address[ADDR_NO_CACHE_BIT] & ~muxed_address[ADDR_CACHE_BYPASS_BIT];`
168
169			`// Cache hit?`
170			`wire hit = cacheable & valid & (muxed_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] == tag_data_out[13:0]) & (state == STATE_CHECK);`
171
172			`assign ack_o = ack \| hit;`
173
174			`assign line_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] = tag_entry;`
175			`assign line_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] = tag_data_out[13:0];`
176			`assign line_address[CACHE_LINE_SIZE_WIDTH-1:0] = {CACHE_LINE_SIZE_WIDTH{1'b0}};`
177
178			`//-----------------------------------------------------------------`
179			`// Control logic`
180			`//-----------------------------------------------------------------`
181			`always @ (posedge rst_i or posedge clk_i )`
182			`begin`
183			`if (rst_i == 1'b1)`
184			`begin`
185			`data_w <= 32'h00000000;`
186			`data_wr <= 4'h0;`
187			`data_rd <= 1'b0;`
188			`req_address <= 32'h00000000;`
189			`req_ack <= 1'b0;`
190			`req_wr <= 4'h0;`
191			`req_rd <= 1'b0;`
192			`tag_wr <= 1'b0;`
193			`req_flush <= 1'b0;`
194			`flush_single <= 1'b0;`
195			`fill <= 1'b0;`
196			`evict <= 1'b0;`
197			`cache_data_w <= 32'h00000000;`
198			`cache_wr <= 4'b0;`
199			`ack <= 1'b0;`
200			`state <= STATE_IDLE;`
201			`end`
202			`else`
203			`begin`
204			`ack <= 1'b0;`
205			`tag_wr <= 1'b0;`
206			`fill <= 1'b0;`
207			`evict <= 1'b0;`
208			`cache_wr <= 4'b0;`
209			`data_wr <= 4'b0;`
210			`data_rd <= 1'b0;`
211
212			`if (flush_i)`
213			`req_flush <= 1'b1;`
214
215			`case (state)`
216
217			`//-----------------------------------------`
218			`// IDLE`
219			`//-----------------------------------------`
220			`STATE_IDLE :`
221			`begin`
222			`// Read (uncacheable)`
223			`if (rd_i & ~cacheable)`
224			`begin`
225			`// Start read single from memory`
226			`req_address <= address_i;`
227			`req_address[ADDR_CACHE_BYPASS_BIT] <= 1'b0;`
228			`data_rd <= 1'b1;`
229			`req_rd <= 1'b1;`
230			`req_wr <= 4'b0;`
231			`req_ack <= 1'b1;`
232			`state <= STATE_SINGLE;`
233			`end`
234			`// Read (cacheable)`
235			`else if (rd_i)`
236			`begin`
237			`req_address <= address_i;`
238			`req_rd <= 1'b1;`
239			`req_wr <= 4'b0;`
240			`req_ack <= 1'b1;`
241			`state <= STATE_CHECK;`
242			`end`
243			`// Write (uncacheable)`
244			`else if (wr_i != 4'b0000 & ~cacheable)`
245			`begin`
246			`// Perform write single`
247			`req_address <= address_i;`
248			`req_address[ADDR_CACHE_BYPASS_BIT] <= 1'b0;`
249			`data_w <= data_i;`
250			`data_wr <= wr_i;`
251			`req_wr <= wr_i;`
252			`req_rd <= 1'b0;`
253			`req_ack <= 1'b1;`
254			`state <= STATE_SINGLE;`
255			`end`
256			`// Write (cacheable)`
257			`else if (wr_i != 4'b0000)`
258			`begin`
259			`req_address <= address_i;`
260			`data_w <= data_i;`
261			`req_wr <= wr_i;`
262			`req_rd <= 1'b0;`
263			`req_ack <= 1'b0;`
264
265			`// Early ACK`
266			`ack <= 1'b1;`
267
268			`state <= STATE_WRITE;`
269			`end`
270			`// Cache flush request`
271			`else if (flush_i \| req_flush)`
272			`begin`
273			`// Set to first line address`
274			`req_address <= 32'h00000000;`
275			`req_flush <= 1'b0;`
276			`req_ack <= 1'b0;`
277			`flush_single<= 1'b0;`
278			`state <= STATE_FLUSH2;`
279			`end`
280			`end`
281			`//-----------------------------------------`
282			`// WRITE - Wait for write-thru to complete`
283			`//-----------------------------------------`
284			`STATE_WRITE :`
285			`begin`
286			`// Cache hit`
287			`if (valid &&`
288			`(req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] == tag_data_out[13:0]))`
289			`begin`
290			`// Update line already in cache`
291			`cache_data_w <= data_w;`
292			`cache_wr <= req_wr;`
293
294			`// Mark line as dirty`
295			`tag_data_in <= tag_data_out;`
296			`tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b1;`
297			`tag_wr <= 1'b1;`
298
299			`state <= STATE_WAIT2;`
300			`end`
301			`// Cache dirty`
302			`else if (valid & dirty)`
303			`begin`
304			`// Evict cache line`
305			`evict <= 1'b1;`
306			`state <= STATE_EVICTING;`
307			`end`
308			`// Cache miss`
309			`else`
310			`begin`
311			`// Update tag memory with this line's details`
312			`tag_data_in <= {1'b1, 1'b1, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};`
313			`tag_wr <= 1'b1;`
314
315			`// Fill cache line`
316			`fill <= 1'b1;`
317			`state <= STATE_UPDATE;`
318			`end`
319			`end`
320			`//-----------------------------------------`
321			`// EVICTING - Evicting cache line`
322			`//-----------------------------------------`
323			`STATE_EVICTING:`
324			`begin`
325			`// Data ready from memory?`
326			`if (done)`
327			`begin`
328			`// Update tag memory with this new line's details`
329			`tag_data_in <= {1'b1, 1'b0, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};`
330			`tag_wr <= 1'b1;`
331
332			`// Fill cache line`
333			`fill <= 1'b1;`
334
335			`// Evict for read?`
336			`if (req_rd)`
337			`state <= STATE_FETCH;`
338			`// Evict for write`
339			`else`
340			`state <= STATE_UPDATE;`
341			`end`
342			`end`
343			`//-----------------------------------------`
344			`// UPDATE - Update fetched cache line`
345			`//-----------------------------------------`
346			`STATE_UPDATE:`
347			`begin`
348			`// Data ready from memory?`
349			`if (done)`
350			`begin`
351			`// Update line already in cache`
352			`cache_data_w <= data_w;`
353			`cache_wr <= req_wr;`
354
355			`// Mark line as dirty`
356			`tag_data_in <= tag_data_out;`
357			`tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b1;`
358			`tag_wr <= 1'b1;`
359
360			`state <= STATE_WAIT2;`
361			`end`
362			`end`
363			`//-----------------------------------------`
364			`// CHECK - check cache for hit or miss`
365			`//-----------------------------------------`
366			`STATE_CHECK :`
367			`begin`
368			`// Cache hit`
369			`if (valid &&`
370			`(req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] == tag_data_out[13:0]))`
371			`begin`
372			`state <= STATE_IDLE;`
373			`end`
374			`// Cache dirty`
375			`else if (valid & dirty)`
376			`begin`
377			`// Evict cache line`
378			`evict <= 1'b1;`
379			`state <= STATE_EVICTING;`
380			`end`
381			`// Cache miss`
382			`else`
383			`begin`
384			`// Update tag memory with this line's details`
385			`tag_data_in <= {1'b1, 1'b0, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};`
386			`tag_wr <= 1'b1;`
387
388			`// Fill cache line`
389			`fill <= 1'b1;`
390			`state <= STATE_FETCH;`
391			`end`
392			`end`
393			`//-----------------------------------------`
394			`// FETCH_SINGLE - Single access to memory`
395			`//-----------------------------------------`
396			`STATE_SINGLE:`
397			`begin`
398			`// Data ready from memory?`
399			`if (done)`
400			`begin`
401			`// Single WRITE?`
402			`if (~req_rd)`
403			`begin`
404			`state <= STATE_SINGLE_READY;`
405			`ack <= req_ack;`
406			`end`
407			`// Dirty? Write back`
408			`else if (valid & dirty)`
409			`begin`
410			`// Evict cache line`
411			`evict <= 1'b1;`
412			`flush_single<= 1'b1;`
413			`state <= STATE_FLUSH4;`
414			`end`
415			`// Valid line, invalidate`
416			`else if (valid)`
417			`begin`
418			`tag_data_in <= tag_data_out;`
419			`tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;`
420			`tag_wr <= 1'b1;`
421
422			`state <= STATE_SINGLE_READY;`
423			`ack <= req_ack;`
424			`end`
425			`else`
426			`begin`
427			`state <= STATE_SINGLE_READY;`
428			`ack <= req_ack;`
429			`end`
430			`end`
431			`end`
432			`//-----------------------------------------`
433			`// FETCH - Fetch row from memory`
434			`//-----------------------------------------`
435			`STATE_FETCH :`
436			`begin`
437			`// Cache line filled?`
438			`if (done)`
439			`state <= STATE_WAIT;`
440			`end`
441			`//-----------------------------------------`
442			`// WAIT - Wait cycle`
443			`//-----------------------------------------`
444			`STATE_WAIT :`
445			`begin`
446			`// Allow extra wait state to handle write & read collision`
447			`state <= STATE_WAIT2;`
448			`end`
449			`//-----------------------------------------`
450			`// WAIT2 - Wait cycle`
451			`//-----------------------------------------`
452			`STATE_WAIT2 :`
453			`begin`
454			`state <= STATE_IDLE;`
455			`ack <= req_ack;`
456			`end`
457			`//-----------------------------------------`
458			`// SINGLE_READY - Uncached access ready`
459			`//-----------------------------------------`
460			`STATE_SINGLE_READY :`
461			`begin`
462			`// Allow extra wait state to handle write & read collision`
463			`state <= STATE_IDLE;`
464			`end`
465			`//-----------------------------------------`
466			`// FLUSHx - Flush dirty lines & invalidate`
467			`//-----------------------------------------`
468			`STATE_FLUSH1 :`
469			`begin`
470			`if (req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] == {CACHE_LINE_ADDR_WIDTH{1'b1}})`
471			`begin`
472			`req_ack <= 1'b0;`
473			`state <= STATE_WAIT;`
474			`end`
475			`else`
476			`begin`
477			`// Increment flush line address`
478			`req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] <=`
479			`req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] + 1;`
480
481			`state <= STATE_FLUSH2;`
482			`end`
483			`end`
484			`//-----------------------------------------`
485			`// FLUSH2 - Wait state`
486			`//-----------------------------------------`
487			`STATE_FLUSH2 :`
488			`begin`
489			`// Allow a cycle to read line state`
490			`state <= STATE_FLUSH3;`
491			`end`
492			`//-----------------------------------------`
493			`// FLUSH3 - Check if line dirty & flush`
494			`//-----------------------------------------`
495			`STATE_FLUSH3 :`
496			`begin`
497			`// Dirty line? Evict line first`
498			`if (dirty)`
499			`begin`
500			`// Evict cache line`
501			`evict <= 1'b1;`
502			`state <= STATE_FLUSH4;`
503			`end`
504			`// Not dirty? Just invalidate`
505			`else`
506			`begin`
507			`tag_data_in <= tag_data_out;`
508			`tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;`
509			`tag_wr <= 1'b1;`
510
511			`if (flush_single)`
512			`state <= STATE_WAIT;`
513			`else`
514			`state <= STATE_FLUSH1;`
515			`end`
516			`end`
517			`//-----------------------------------------`
518			`// FLUSH4 - Wait for line flush to complete`
519			`//-----------------------------------------`
520			`STATE_FLUSH4 :`
521			`begin`
522			`// Cache line filled?`
523			`if (done)`
524			`begin`
525			`// Invalidate line`
526			`tag_data_in <= tag_data_out;`
527			`tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;`
528			`tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b0;`
529			`tag_wr <= 1'b1;`
530
531			`if (flush_single)`
532			`begin`
533			`state <= STATE_SINGLE_READY;`
534			`ack <= req_ack;`
535			`end`
536			`else`
537			`state <= STATE_FLUSH1;`
538			`end`
539			`end`
540			`default:`
541			`;`
542			`endcase`
543			`end`
544			`end`
545
546			`//-----------------------------------------------------------------`
547			`// Instantiation`
548			`//-----------------------------------------------------------------`
549
550			`altor32_dcache_mem_if`
551			`#(`
552			`.CACHE_LINE_SIZE_WIDTH(CACHE_LINE_SIZE_WIDTH),`
553			`.CACHE_LINE_WORDS_IDX_MAX(CACHE_LINE_WORDS_IDX_MAX)`
554			`)`
555			`u_mem_if`
556			`(`
557			`.clk_i(clk_i),`
558			`.rst_i(rst_i),`
559
560			`// Cache interface`
561			`.address_i(muxed_address),`
562			`.data_i(data_w),`
563			`.data_o(data_r),`
564			`.fill_i(fill),`
565			`.evict_i(evict),`
566			`.evict_addr_i(line_address),`
567			`.rd_single_i(data_rd),`
568			`.wr_single_i(data_wr),`
569			`.done_o(done),`
570
571			`// Cache memory (fill/evict)`
572			`.cache_addr_o(cache_update_addr),`
573			`.cache_data_o(cache_update_data_w),`
574			`.cache_data_i(cache_update_data_r),`
575			`.cache_wr_o(cache_update_wr),`
576
577			`// Memory interface (slave)`
578			`.mem_addr_o(mem_addr_o),`
579			`.mem_data_i(mem_data_i),`
580			`.mem_data_o(mem_data_o),`
581			`.mem_burst_o(mem_burst_o),`
582			`.mem_rd_o(mem_rd_o),`
583			`.mem_wr_o(mem_wr_o),`
584			`.mem_accept_i(mem_accept_i),`
585			`.mem_ack_i(mem_ack_i)`
586			`);`
587
588			`// Tag memory`
589			`altor32_ram_sp`
590			`#(`
591			`.WIDTH(CACHE_TAG_WIDTH),`
592			`.SIZE(CACHE_LINE_ADDR_WIDTH)`
593			`)`
594			`u1_tag_mem`
595			`(`
596			`.clk_i(clk_i),`
597			`.dat_o(tag_data_out),`
598			`.dat_i(tag_data_in),`
599			`.adr_i(tag_entry),`
600			`.wr_i(tag_wr)`
601			`);`
602
603			`// Data memory`
604			`altor32_ram_dp`
605			`#(`
606			`.WIDTH(8),`
607			`.SIZE(CACHE_DWIDTH)`
608			`)`
609			`u2_data_mem0`
610			`(`
611			`.aclk_i(clk_i),`
612			`.aadr_i(cache_address),`
613			`.adat_o(cache_data_r[7:0]),`
614			`.adat_i(cache_data_w[7:0]),`
615			`.awr_i(cache_wr[0]),`
616
617			`.bclk_i(clk_i),`
618			`.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),`
619			`.bdat_o(cache_update_data_r[7:0]),`
620			`.bdat_i(cache_update_data_w[7:0]),`
621			`.bwr_i(cache_update_wr)`
622			`);`
623
624			`altor32_ram_dp`
625			`#(`
626			`.WIDTH(8),`
627			`.SIZE(CACHE_DWIDTH)`
628			`)`
629			`u2_data_mem1`
630			`(`
631			`.aclk_i(clk_i),`
632			`.aadr_i(cache_address),`
633			`.adat_o(cache_data_r[15:8]),`
634			`.adat_i(cache_data_w[15:8]),`
635			`.awr_i(cache_wr[1]),`
636
637			`.bclk_i(clk_i),`
638			`.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),`
639			`.bdat_o(cache_update_data_r[15:8]),`
640			`.bdat_i(cache_update_data_w[15:8]),`
641			`.bwr_i(cache_update_wr)`
642			`);`
643
644			`altor32_ram_dp`
645			`#(`
646			`.WIDTH(8),`
647			`.SIZE(CACHE_DWIDTH)`
648			`)`
649			`u2_data_mem2`
650			`(`
651			`.aclk_i(clk_i),`
652			`.aadr_i(cache_address),`
653			`.adat_o(cache_data_r[23:16]),`
654			`.adat_i(cache_data_w[23:16]),`
655			`.awr_i(cache_wr[2]),`
656
657			`.bclk_i(clk_i),`
658			`.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),`
659			`.bdat_o(cache_update_data_r[23:16]),`
660			`.bdat_i(cache_update_data_w[23:16]),`
661			`.bwr_i(cache_update_wr)`
662			`);`
663
664			`altor32_ram_dp`
665			`#(`
666			`.WIDTH(8),`
667			`.SIZE(CACHE_DWIDTH)`
668			`)`
669			`u2_data_mem3`
670			`(`
671			`.aclk_i(clk_i),`
672			`.aadr_i(cache_address),`
673			`.adat_o(cache_data_r[31:24]),`
674			`.adat_i(cache_data_w[31:24]),`
675			`.awr_i(cache_wr[3]),`
676
677			`.bclk_i(clk_i),`
678			`.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),`
679			`.bdat_o(cache_update_data_r[31:24]),`
680			`.bdat_i(cache_update_data_w[31:24]),`
681			`.bwr_i(cache_update_wr)`
682			`);`
683
684			`endmodule`