URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dcache_mem_if.v] - Blame information for rev 32

Go to most recent revision | Details | Compare with Previous | View Log


//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.0
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2013
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module - Data Cache Memory Interface
//-----------------------------------------------------------------
module altor32_dcache_mem_if
(
    input               clk_i /*verilator public*/,
    input               rst_i /*verilator public*/,
 
    // Cache interface
    input [31:0]        address_i /*verilator public*/,
    input [31:0]        data_i /*verilator public*/,
    output reg [31:0]   data_o /*verilator public*/,
    input               fill_i /*verilator public*/,
    input               evict_i /*verilator public*/,
    input  [31:0]       evict_addr_i /*verilator public*/,
    input               rd_single_i /*verilator public*/,
    input [3:0]         wr_single_i /*verilator public*/,
    output reg          done_o /*verilator public*/,
 
    // Cache memory (fill/evict)
    output reg [31:2]   cache_addr_o /*verilator public*/,
    output reg [31:0]   cache_data_o /*verilator public*/,
    input      [31:0]   cache_data_i /*verilator public*/,
    output reg          cache_wr_o /*verilator public*/,
 
    // Memory interface (slave)
    output reg [31:0]   mem_addr_o /*verilator public*/,
    input [31:0]        mem_data_i /*verilator public*/,
    output reg [31:0]   mem_data_o /*verilator public*/,
    output reg [2:0]    mem_cti_o /*verilator public*/,
    output reg          mem_cyc_o /*verilator public*/,
    output reg          mem_stb_o /*verilator public*/,
    output reg          mem_we_o /*verilator public*/,
    output reg [3:0]    mem_sel_o /*verilator public*/,
    input               mem_stall_i/*verilator public*/,
    input               mem_ack_i/*verilator public*/
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CACHE_LINE_SIZE_WIDTH     = 5;                         /* 5-bits -> 32 entries */
parameter CACHE_LINE_WORDS_IDX_MAX  = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit -> 8 words */
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
 
reg [31:CACHE_LINE_SIZE_WIDTH]  line_address;
 
reg [CACHE_LINE_WORDS_IDX_MAX-1:0] response_idx;
 
reg [CACHE_LINE_WORDS_IDX_MAX-1:0]  request_idx;
wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_request_idx = request_idx + 1'b1;
 
reg [CACHE_LINE_WORDS_IDX_MAX-1:0]  cache_idx;
wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_cache_idx = cache_idx + 1'b1;
 
 
// Current state
parameter STATE_IDLE        = 0;
parameter STATE_FETCH       = 1;
parameter STATE_WRITE_SETUP = 2;
parameter STATE_WRITE       = 3;
parameter STATE_WRITE_WAIT  = 4;
parameter STATE_MEM_SINGLE  = 5;
parameter STATE_FETCH_WAIT  = 6;
 
reg [3:0] state;
 
//-----------------------------------------------------------------
// Next State Logic
//-----------------------------------------------------------------
reg [3:0] next_state_r;
always @ *
begin
    next_state_r = state;
 
    case (state)
    //-----------------------------------------
    // IDLE
    //-----------------------------------------
    STATE_IDLE :
    begin
        // Perform cache evict (write)     
        if (evict_i)
            next_state_r    = STATE_WRITE_SETUP;
        // Perform cache fill (read)
        else if (fill_i)
            next_state_r    = STATE_FETCH;
        // Read/Write single
        else if (rd_single_i | (|wr_single_i))
            next_state_r    = STATE_MEM_SINGLE;
    end
    //-----------------------------------------
    // FETCH - Fetch line from memory
    //-----------------------------------------
    STATE_FETCH :
    begin
        // Line fetch complete?
        if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
            next_state_r    = STATE_FETCH_WAIT;
    end
    //-----------------------------------------
    // FETCH_WAIT - Wait for read responses
    //-----------------------------------------
    STATE_FETCH_WAIT:
    begin
        // Read from memory complete
        if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
            next_state_r = STATE_IDLE;
    end
    //-----------------------------------------
    // WRITE_SETUP - Wait for data from cache
    //-----------------------------------------
    STATE_WRITE_SETUP :
        next_state_r    = STATE_WRITE;
    //-----------------------------------------
    // WRITE - Write word to memory
    //-----------------------------------------
    STATE_WRITE :
    begin
        // Line write complete?
        if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
            next_state_r = STATE_WRITE_WAIT;
        // Fetch next word for line
        else if (~mem_stall_i | ~mem_stb_o)
            next_state_r = STATE_WRITE_SETUP;
    end
    //-----------------------------------------
    // WRITE_WAIT - Wait for write to complete
    //-----------------------------------------
    STATE_WRITE_WAIT:
    begin
        // Write to memory complete
        if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
            next_state_r = STATE_IDLE;
    end
    //-----------------------------------------
    // MEM_SINGLE - Single access to memory
    //-----------------------------------------
    STATE_MEM_SINGLE:
    begin
        // Data ready from memory?
        if (mem_ack_i)
            next_state_r  = STATE_IDLE;
    end
    default:
        ;
   endcase
end
 
// Update state
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
        state   <= STATE_IDLE;
   else
        state   <= next_state_r;
end
 
//-----------------------------------------------------------------
// Control logic
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        line_address    <= {32-CACHE_LINE_SIZE_WIDTH{1'b0}};
        done_o          <= 1'b0;
        data_o          <= 32'h00000000;
   end
   else
   begin
        done_o          <= 1'b0;
 
        case (state)
 
            //-----------------------------------------
            // IDLE
            //-----------------------------------------
            STATE_IDLE :
            begin
                // Perform cache evict (write)     
                if (evict_i)
                    line_address <= evict_addr_i[31:CACHE_LINE_SIZE_WIDTH];
                // Perform cache fill (read)
                else if (fill_i)
                    line_address <= address_i[31:CACHE_LINE_SIZE_WIDTH];
            end
            //-----------------------------------------
            // FETCH/WRITE_WAIT - Wait for oustanding responses
            //-----------------------------------------
            STATE_WRITE_WAIT,
            STATE_FETCH_WAIT:
            begin
                // Write to memory complete
                if (mem_ack_i)
                begin
                    // Line write complete?
                    if (response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
                        done_o      <= 1'b1;
                end
            end
            //-----------------------------------------
            // MEM_SINGLE - Single access to memory
            //-----------------------------------------
            STATE_MEM_SINGLE:
            begin
                // Data ready from memory?
                if (mem_ack_i)
                begin
                    data_o      <= mem_data_i;
                    done_o      <= 1'b1;
                end
            end
            default:
                ;
           endcase
   end
end
 
//-----------------------------------------------------------------
// Cache Read / Write
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        cache_addr_o    <= 30'h00000000;
        cache_data_o    <= 32'h00000000;
        cache_wr_o      <= 1'b0;
 
        cache_idx       <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
   end
   else
   begin
        cache_wr_o      <= 1'b0;
 
        case (state)
 
            //-----------------------------------------
            // IDLE
            //-----------------------------------------
            STATE_IDLE :
            begin
                cache_idx       <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
 
                // Perform cache evict (write)     
                if (evict_i)
                begin
                    // Read data from cache
                    cache_addr_o  <= {evict_addr_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_WORDS_IDX_MAX{1'b0}}};
                end
            end
            //-----------------------------------------
            // FETCH - Fetch line from memory
            //-----------------------------------------
            STATE_FETCH,
            STATE_FETCH_WAIT:
            begin
                // Data ready from memory?
                if (mem_ack_i)
                begin
                    // Write data into cache
                    cache_addr_o    <= {line_address, cache_idx};
                    cache_data_o    <= mem_data_i;
                    cache_wr_o      <= 1'b1;
 
                    cache_idx       <= next_cache_idx;
                end
            end
            //-----------------------------------------
            // WRITE - Write word to memory
            //-----------------------------------------
            STATE_WRITE_SETUP:
            begin
 
            end
            STATE_WRITE,
            STATE_WRITE_WAIT:
            begin
                if (~mem_stall_i | ~mem_stb_o)
                begin
                    // Setup next word read from cache
                    cache_addr_o <= {line_address, next_cache_idx};
                    cache_idx    <= next_cache_idx;
                end
            end
            default:
                ;
           endcase
   end
end
 
//-----------------------------------------------------------------
// Request
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        mem_addr_o      <= 32'h00000000;
        mem_data_o      <= 32'h00000000;
        mem_sel_o       <= 4'h0;
        mem_cti_o       <= 3'b0;
        mem_stb_o       <= 1'b0;
        mem_we_o        <= 1'b0;
        request_idx     <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
   end
   else
   begin
        if (~mem_stall_i)
        begin
            mem_stb_o   <= 1'b0;
 
            // TMP
            if (mem_cti_o == 3'b111)
            begin
                //mem_addr_o      <= 32'h00000000;
                mem_data_o      <= 32'h00000000;
                mem_sel_o       <= 4'h0;
                mem_cti_o       <= 3'b0;
                mem_stb_o       <= 1'b0;
                mem_we_o        <= 1'b0;
            end
        end
 
        case (state)
 
            //-----------------------------------------
            // IDLE
            //-----------------------------------------
            STATE_IDLE :
            begin
                request_idx     <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
 
                // Perform cache evict (write)     
                if (evict_i)
                begin
 
                end
                // Perform cache fill (read)
                else if (fill_i)
                begin
                    // Start fetch from memory
                    mem_addr_o   <= {address_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
                    mem_data_o   <= 32'h00000000;
                    mem_sel_o    <= 4'b1111;
                    mem_cti_o    <= 3'b010;
                    mem_stb_o    <= 1'b1;
                    mem_we_o     <= 1'b0;
 
                    request_idx  <= next_request_idx;
                end
                // Read single
                else if (rd_single_i)
                begin
                    // Start fetch from memory
                    mem_addr_o   <= address_i;
                    mem_data_o   <= 32'h00000000;
                    mem_sel_o    <= 4'b1111;
                    mem_cti_o    <= 3'b111;
                    mem_stb_o    <= 1'b1;
                    mem_we_o     <= 1'b0;
                end
                // Write single
                else if (|wr_single_i)
                begin
                    // Start fetch from memory
                    mem_addr_o   <= address_i;
                    mem_data_o   <= data_i;
                    mem_sel_o    <= wr_single_i;
                    mem_cti_o    <= 3'b111;
                    mem_stb_o    <= 1'b1;
                    mem_we_o     <= 1'b1;
                end
            end
            //-----------------------------------------
            // FETCH - Fetch line from memory
            //-----------------------------------------
            STATE_FETCH :
            begin
                // Previous request accepted?
                if (~mem_stall_i)
                begin
                    // Fetch next word for line
                    mem_addr_o <= {line_address, request_idx, 2'b00};
                    mem_stb_o  <= 1'b1;
 
                    if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
                        mem_cti_o <= 3'b111;
 
                    request_idx <= next_request_idx;
                end
            end
            //-----------------------------------------
            // WRITE - Write word to memory
            //-----------------------------------------
            STATE_WRITE :
            begin
                // Memory interface can request command?
                if (~mem_stall_i | ~mem_stb_o)
                begin
                    // Write data into memory from cache
                    mem_addr_o   <= {line_address, request_idx, 2'b00};
                    mem_data_o   <= cache_data_i;
                    mem_sel_o    <= 4'b1111;
                    mem_stb_o    <= 1'b1;
                    mem_we_o     <= 1'b1;
 
                    if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
                        mem_cti_o <= 3'b111;
                    else
                        mem_cti_o <= 3'b010;
 
                    request_idx <= next_request_idx;
                end
            end
            default:
                ;
           endcase
   end
end
 
//-----------------------------------------------------------------
// Memory Response Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
        response_idx    <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
   else
   begin
        case (state)
 
            //-----------------------------------------
            // IDLE
            //-----------------------------------------
            STATE_IDLE :
            begin
                response_idx    <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
            end
            //-----------------------------------------
            // FETCH - Fetch line from memory
            //-----------------------------------------
            STATE_FETCH,
            STATE_FETCH_WAIT :
            begin
                // Data ready from memory?
                if (mem_ack_i)
                    response_idx <= response_idx + 1'b1;
            end
            //-----------------------------------------
            // WRITE_WAIT - Wait for write to complete
            //-----------------------------------------
            STATE_WRITE,
            STATE_WRITE_SETUP,
            STATE_WRITE_WAIT:
            begin
                // Write to memory complete
                if (mem_ack_i)
                    response_idx <= response_idx + 1'b1;
            end
            default:
                ;
           endcase
   end
end
 
//-----------------------------------------------------------------
// CYC_O
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
        mem_cyc_o       <= 1'b0;
   else
   begin
        case (state)
 
            //-----------------------------------------
            // IDLE
            //-----------------------------------------
            STATE_IDLE :
            begin
                // Perform cache evict (write)     
                if (evict_i)
                begin
 
                end
                // Perform cache fill (read)
                else if (fill_i)
                    mem_cyc_o    <= 1'b1;
                // Read single
                else if (rd_single_i)
                    mem_cyc_o    <= 1'b1;
                // Write single
                else if (|wr_single_i)
                    mem_cyc_o    <= 1'b1;
            end
            //-----------------------------------------
            // FETCH - Fetch line from memory
            //-----------------------------------------
            STATE_FETCH :
            begin
                // Data ready from memory?
                if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
                    mem_cyc_o   <= 1'b0;
            end
            //-----------------------------------------
            // WRITE - Write word to memory
            //-----------------------------------------
            STATE_WRITE :
            begin
                // Write data into memory from cache
                mem_cyc_o    <= 1'b1;
            end
            //-----------------------------------------
            // FETCH/WRITE_WAIT - Wait for responses
            //-----------------------------------------
            STATE_WRITE_WAIT,
            STATE_FETCH_WAIT:
            begin
                // Write to memory complete
                if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
                    mem_cyc_o   <= 1'b0;
            end
            //-----------------------------------------
            // MEM_SINGLE - Single access to memory
            //-----------------------------------------
            STATE_MEM_SINGLE:
            begin
                // Data ready from memory?
                if (mem_ack_i)
                    mem_cyc_o   <= 1'b0;
            end
            default:
                ;
           endcase
   end
end
 
endmodule

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4			`// V2.0`
5			`// Ultra-Embedded.com`
6			`// Copyright 2011 - 2013`
7			`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13			`// Copyright (C) 2011 - 2013 Ultra-Embedded.com`
14			`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// Module - Data Cache Memory Interface`
40			`//-----------------------------------------------------------------`
41			`module altor32_dcache_mem_if`
42			`(`
43	30	ultra_embe	`input clk_i /verilator public/,`
44			`input rst_i /verilator public/,`
45	27	ultra_embe
46			`// Cache interface`
47	30	ultra_embe	`input [31:0] address_i /verilator public/,`
48			`input [31:0] data_i /verilator public/,`
49			`output reg [31:0] data_o /verilator public/,`
50			`input fill_i /verilator public/,`
51			`input evict_i /verilator public/,`
52			`input [31:0] evict_addr_i /verilator public/,`
53			`input rd_single_i /verilator public/,`
54			`input [3:0] wr_single_i /verilator public/,`
55			`output reg done_o /verilator public/,`
56	27	ultra_embe
57			`// Cache memory (fill/evict)`
58	30	ultra_embe	`output reg [31:2] cache_addr_o /verilator public/,`
59			`output reg [31:0] cache_data_o /verilator public/,`
60			`input [31:0] cache_data_i /verilator public/,`
61			`output reg cache_wr_o /verilator public/,`
62	27	ultra_embe
63			`// Memory interface (slave)`
64	30	ultra_embe	`output reg [31:0] mem_addr_o /verilator public/,`
65	32	ultra_embe	`input [31:0] mem_data_i /verilator public/,`
66	30	ultra_embe	`output reg [31:0] mem_data_o /verilator public/,`
67	32	ultra_embe	`output reg [2:0] mem_cti_o /verilator public/,`
68			`output reg mem_cyc_o /verilator public/,`
69			`output reg mem_stb_o /verilator public/,`
70			`output reg mem_we_o /verilator public/,`
71			`output reg [3:0] mem_sel_o /verilator public/,`
72			`input mem_stall_i/verilator public/,`
73			`input mem_ack_i/verilator public/`
74	27	ultra_embe	`);`
75
76			`//-----------------------------------------------------------------`
77			`// Params`
78			`//-----------------------------------------------------------------`
79			`parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */`
80			`parameter CACHE_LINE_WORDS_IDX_MAX = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit -> 8 words */`
81
82			`//-----------------------------------------------------------------`
83			`// Registers / Wires`
84			`//-----------------------------------------------------------------`
85
86			`reg [31:CACHE_LINE_SIZE_WIDTH] line_address;`
87
88	32	ultra_embe	`reg [CACHE_LINE_WORDS_IDX_MAX-1:0] response_idx;`
89
90			`reg [CACHE_LINE_WORDS_IDX_MAX-1:0] request_idx;`
91			`wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_request_idx = request_idx + 1'b1;`
92
93			`reg [CACHE_LINE_WORDS_IDX_MAX-1:0] cache_idx;`
94			`wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_cache_idx = cache_idx + 1'b1;`
95
96
97	27	ultra_embe	`// Current state`
98			`parameter STATE_IDLE = 0;`
99			`parameter STATE_FETCH = 1;`
100	32	ultra_embe	`parameter STATE_WRITE_SETUP = 2;`
101	27	ultra_embe	`parameter STATE_WRITE = 3;`
102			`parameter STATE_WRITE_WAIT = 4;`
103	32	ultra_embe	`parameter STATE_MEM_SINGLE = 5;`
104			`parameter STATE_FETCH_WAIT = 6;`
105	27	ultra_embe
106			`reg [3:0] state;`
107
108			`//-----------------------------------------------------------------`
109	32	ultra_embe	`// Next State Logic`
110	27	ultra_embe	`//-----------------------------------------------------------------`
111	32	ultra_embe	`reg [3:0] next_state_r;`
112			`always @ *`
113			`begin`
114			`next_state_r = state;`
115	27	ultra_embe
116	32	ultra_embe	`case (state)`
117			`//-----------------------------------------`
118			`// IDLE`
119			`//-----------------------------------------`
120			`STATE_IDLE :`
121			`begin`
122			`// Perform cache evict (write)`
123			`if (evict_i)`
124			`next_state_r = STATE_WRITE_SETUP;`
125			`// Perform cache fill (read)`
126			`else if (fill_i)`
127			`next_state_r = STATE_FETCH;`
128			`// Read/Write single`
129			`else if (rd_single_i \| (\|wr_single_i))`
130			`next_state_r = STATE_MEM_SINGLE;`
131			`end`
132			`//-----------------------------------------`
133			`// FETCH - Fetch line from memory`
134			`//-----------------------------------------`
135			`STATE_FETCH :`
136			`begin`
137			`// Line fetch complete?`
138			`if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})`
139			`next_state_r = STATE_FETCH_WAIT;`
140			`end`
141			`//-----------------------------------------`
142			`// FETCH_WAIT - Wait for read responses`
143			`//-----------------------------------------`
144			`STATE_FETCH_WAIT:`
145			`begin`
146			`// Read from memory complete`
147			`if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})`
148			`next_state_r = STATE_IDLE;`
149			`end`
150			`//-----------------------------------------`
151			`// WRITE_SETUP - Wait for data from cache`
152			`//-----------------------------------------`
153			`STATE_WRITE_SETUP :`
154			`next_state_r = STATE_WRITE;`
155			`//-----------------------------------------`
156			`// WRITE - Write word to memory`
157			`//-----------------------------------------`
158			`STATE_WRITE :`
159			`begin`
160			`// Line write complete?`
161			`if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})`
162			`next_state_r = STATE_WRITE_WAIT;`
163			`// Fetch next word for line`
164			`else if (~mem_stall_i \| ~mem_stb_o)`
165			`next_state_r = STATE_WRITE_SETUP;`
166			`end`
167			`//-----------------------------------------`
168			`// WRITE_WAIT - Wait for write to complete`
169			`//-----------------------------------------`
170			`STATE_WRITE_WAIT:`
171			`begin`
172			`// Write to memory complete`
173			`if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})`
174			`next_state_r = STATE_IDLE;`
175			`end`
176			`//-----------------------------------------`
177			`// MEM_SINGLE - Single access to memory`
178			`//-----------------------------------------`
179			`STATE_MEM_SINGLE:`
180			`begin`
181			`// Data ready from memory?`
182			`if (mem_ack_i)`
183			`next_state_r = STATE_IDLE;`
184			`end`
185			`default:`
186			`;`
187			`endcase`
188			`end`
189
190			`// Update state`
191	27	ultra_embe	`always @ (posedge rst_i or posedge clk_i )`
192			`begin`
193			`if (rst_i == 1'b1)`
194	32	ultra_embe	`state <= STATE_IDLE;`
195			`else`
196			`state <= next_state_r;`
197			`end`
198
199			`//-----------------------------------------------------------------`
200			`// Control logic`
201			`//-----------------------------------------------------------------`
202			`always @ (posedge rst_i or posedge clk_i )`
203			`begin`
204			`if (rst_i == 1'b1)`
205	27	ultra_embe	`begin`
206			`line_address <= {32-CACHE_LINE_SIZE_WIDTH{1'b0}};`
207			`done_o <= 1'b0;`
208			`data_o <= 32'h00000000;`
209			`end`
210			`else`
211			`begin`
212	32	ultra_embe	`done_o <= 1'b0;`
213
214			`case (state)`
215	27	ultra_embe
216	32	ultra_embe	`//-----------------------------------------`
217			`// IDLE`
218			`//-----------------------------------------`
219			`STATE_IDLE :`
220			`begin`
221			`// Perform cache evict (write)`
222			`if (evict_i)`
223			`line_address <= evict_addr_i[31:CACHE_LINE_SIZE_WIDTH];`
224			`// Perform cache fill (read)`
225			`else if (fill_i)`
226			`line_address <= address_i[31:CACHE_LINE_SIZE_WIDTH];`
227			`end`
228			`//-----------------------------------------`
229			`// FETCH/WRITE_WAIT - Wait for oustanding responses`
230			`//-----------------------------------------`
231			`STATE_WRITE_WAIT,`
232			`STATE_FETCH_WAIT:`
233			`begin`
234			`// Write to memory complete`
235			`if (mem_ack_i)`
236			`begin`
237			`// Line write complete?`
238			`if (response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})`
239			`done_o <= 1'b1;`
240			`end`
241			`end`
242			`//-----------------------------------------`
243			`// MEM_SINGLE - Single access to memory`
244			`//-----------------------------------------`
245			`STATE_MEM_SINGLE:`
246			`begin`
247			`// Data ready from memory?`
248			`if (mem_ack_i)`
249			`begin`
250			`data_o <= mem_data_i;`
251			`done_o <= 1'b1;`
252			`end`
253			`end`
254			`default:`
255			`;`
256			`endcase`
257			`end`
258			`end`
259
260			`//-----------------------------------------------------------------`
261			`// Cache Read / Write`
262			`//-----------------------------------------------------------------`
263			`always @ (posedge rst_i or posedge clk_i )`
264			`begin`
265			`if (rst_i == 1'b1)`
266			`begin`
267			`cache_addr_o <= 30'h00000000;`
268			`cache_data_o <= 32'h00000000;`
269	27	ultra_embe	`cache_wr_o <= 1'b0;`
270	32	ultra_embe
271			`cache_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};`
272			`end`
273			`else`
274			`begin`
275			`cache_wr_o <= 1'b0;`
276	27	ultra_embe
277			`case (state)`
278
279			`//-----------------------------------------`
280			`// IDLE`
281			`//-----------------------------------------`
282			`STATE_IDLE :`
283			`begin`
284	32	ultra_embe	`cache_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};`
285
286	27	ultra_embe	`// Perform cache evict (write)`
287			`if (evict_i)`
288			`begin`
289			`// Read data from cache`
290	32	ultra_embe	`cache_addr_o <= {evict_addr_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_WORDS_IDX_MAX{1'b0}}};`
291	27	ultra_embe	`end`
292	32	ultra_embe	`end`
293			`//-----------------------------------------`
294			`// FETCH - Fetch line from memory`
295			`//-----------------------------------------`
296			`STATE_FETCH,`
297			`STATE_FETCH_WAIT:`
298			`begin`
299			`// Data ready from memory?`
300			`if (mem_ack_i)`
301			`begin`
302			`// Write data into cache`
303			`cache_addr_o <= {line_address, cache_idx};`
304			`cache_data_o <= mem_data_i;`
305			`cache_wr_o <= 1'b1;`
306
307			`cache_idx <= next_cache_idx;`
308			`end`
309			`end`
310			`//-----------------------------------------`
311			`// WRITE - Write word to memory`
312			`//-----------------------------------------`
313			`STATE_WRITE_SETUP:`
314			`begin`
315
316			`end`
317			`STATE_WRITE,`
318			`STATE_WRITE_WAIT:`
319			`begin`
320			`if (~mem_stall_i \| ~mem_stb_o)`
321			`begin`
322			`// Setup next word read from cache`
323			`cache_addr_o <= {line_address, next_cache_idx};`
324			`cache_idx <= next_cache_idx;`
325			`end`
326			`end`
327			`default:`
328			`;`
329			`endcase`
330			`end`
331			`end`
332
333			`//-----------------------------------------------------------------`
334			`// Request`
335			`//-----------------------------------------------------------------`
336			`always @ (posedge rst_i or posedge clk_i )`
337			`begin`
338			`if (rst_i == 1'b1)`
339			`begin`
340			`mem_addr_o <= 32'h00000000;`
341			`mem_data_o <= 32'h00000000;`
342			`mem_sel_o <= 4'h0;`
343			`mem_cti_o <= 3'b0;`
344			`mem_stb_o <= 1'b0;`
345			`mem_we_o <= 1'b0;`
346			`request_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};`
347			`end`
348			`else`
349			`begin`
350			`if (~mem_stall_i)`
351			`begin`
352			`mem_stb_o <= 1'b0;`
353
354			`// TMP`
355			`if (mem_cti_o == 3'b111)`
356			`begin`
357			`//mem_addr_o <= 32'h00000000;`
358			`mem_data_o <= 32'h00000000;`
359			`mem_sel_o <= 4'h0;`
360			`mem_cti_o <= 3'b0;`
361			`mem_stb_o <= 1'b0;`
362			`mem_we_o <= 1'b0;`
363			`end`
364			`end`
365
366			`case (state)`
367
368			`//-----------------------------------------`
369			`// IDLE`
370			`//-----------------------------------------`
371			`STATE_IDLE :`
372			`begin`
373			`request_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};`
374
375			`// Perform cache evict (write)`
376			`if (evict_i)`
377			`begin`
378
379			`end`
380	27	ultra_embe	`// Perform cache fill (read)`
381			`else if (fill_i)`
382			`begin`
383			`// Start fetch from memory`
384			`mem_addr_o <= {address_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};`
385	32	ultra_embe	`mem_data_o <= 32'h00000000;`
386			`mem_sel_o <= 4'b1111;`
387			`mem_cti_o <= 3'b010;`
388			`mem_stb_o <= 1'b1;`
389			`mem_we_o <= 1'b0;`
390
391			`request_idx <= next_request_idx;`
392	27	ultra_embe	`end`
393			`// Read single`
394			`else if (rd_single_i)`
395			`begin`
396			`// Start fetch from memory`
397			`mem_addr_o <= address_i;`
398	32	ultra_embe	`mem_data_o <= 32'h00000000;`
399			`mem_sel_o <= 4'b1111;`
400			`mem_cti_o <= 3'b111;`
401			`mem_stb_o <= 1'b1;`
402			`mem_we_o <= 1'b0;`
403	27	ultra_embe	`end`
404			`// Write single`
405			`else if (\|wr_single_i)`
406			`begin`
407			`// Start fetch from memory`
408			`mem_addr_o <= address_i;`
409			`mem_data_o <= data_i;`
410	32	ultra_embe	`mem_sel_o <= wr_single_i;`
411			`mem_cti_o <= 3'b111;`
412			`mem_stb_o <= 1'b1;`
413			`mem_we_o <= 1'b1;`
414	27	ultra_embe	`end`
415			`end`
416			`//-----------------------------------------`
417			`// FETCH - Fetch line from memory`
418			`//-----------------------------------------`
419			`STATE_FETCH :`
420			`begin`
421	32	ultra_embe	`// Previous request accepted?`
422			`if (~mem_stall_i)`
423	27	ultra_embe	`begin`
424			`// Fetch next word for line`
425	32	ultra_embe	`mem_addr_o <= {line_address, request_idx, 2'b00};`
426			`mem_stb_o <= 1'b1;`
427
428			`if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})`
429			`mem_cti_o <= 3'b111;`
430
431			`request_idx <= next_request_idx;`
432	27	ultra_embe	`end`
433			`end`
434			`//-----------------------------------------`
435			`// WRITE - Write word to memory`
436			`//-----------------------------------------`
437			`STATE_WRITE :`
438			`begin`
439	32	ultra_embe	`// Memory interface can request command?`
440			`if (~mem_stall_i \| ~mem_stb_o)`
441			`begin`
442			`// Write data into memory from cache`
443			`mem_addr_o <= {line_address, request_idx, 2'b00};`
444			`mem_data_o <= cache_data_i;`
445			`mem_sel_o <= 4'b1111;`
446			`mem_stb_o <= 1'b1;`
447			`mem_we_o <= 1'b1;`
448
449			`if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})`
450			`mem_cti_o <= 3'b111;`
451			`else`
452			`mem_cti_o <= 3'b010;`
453	27	ultra_embe
454	32	ultra_embe	`request_idx <= next_request_idx;`
455			`end`
456			`end`
457			`default:`
458			`;`
459			`endcase`
460			`end`
461			`end`
462	27	ultra_embe
463	32	ultra_embe	`//-----------------------------------------------------------------`
464			`// Memory Response Counter`
465			`//-----------------------------------------------------------------`
466			`always @ (posedge rst_i or posedge clk_i )`
467			`begin`
468			`if (rst_i == 1'b1)`
469			`response_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};`
470			`else`
471			`begin`
472			`case (state)`
473
474	27	ultra_embe	`//-----------------------------------------`
475	32	ultra_embe	`// IDLE`
476			`//-----------------------------------------`
477			`STATE_IDLE :`
478			`begin`
479			`response_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};`
480			`end`
481			`//-----------------------------------------`
482			`// FETCH - Fetch line from memory`
483			`//-----------------------------------------`
484			`STATE_FETCH,`
485			`STATE_FETCH_WAIT :`
486			`begin`
487			`// Data ready from memory?`
488			`if (mem_ack_i)`
489			`response_idx <= response_idx + 1'b1;`
490			`end`
491			`//-----------------------------------------`
492	27	ultra_embe	`// WRITE_WAIT - Wait for write to complete`
493			`//-----------------------------------------`
494	32	ultra_embe	`STATE_WRITE,`
495			`STATE_WRITE_SETUP,`
496	27	ultra_embe	`STATE_WRITE_WAIT:`
497			`begin`
498			`// Write to memory complete`
499	32	ultra_embe	`if (mem_ack_i)`
500			`response_idx <= response_idx + 1'b1;`

Browse

Tools

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dcache_mem_if.v] - Blame information for rev 32