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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_defs.v] - Blame information for rev 39

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//-----------------------------------------------------------------
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//                           AltOR32 
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//                Alternative Lightweight OpenRisc 
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//                            V2.1
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2014
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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// This source file may be used and distributed without         
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// restriction provided that this copyright statement is not    
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// removed from the file and that any derivative work contains  
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// the original copyright notice and the associated disclaimer. 
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//
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// This source file is free software; you can redistribute it   
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// and/or modify it under the terms of the GNU Lesser General   
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// Public License as published by the Free Software Foundation; 
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// either version 2.1 of the License, or (at your option) any   
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// later version.
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//
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// This source is distributed in the hope that it will be       
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// useful, but WITHOUT ANY WARRANTY; without even the implied   
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
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// PURPOSE.  See the GNU Lesser General Public License for more 
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// details.
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//
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// You should have received a copy of the GNU Lesser General    
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// Public License along with this source; if not, write to the 
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// ALU Operations
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//-----------------------------------------------------------------
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`define ALU_NONE                                4'b0000
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`define ALU_SHIFTL                              4'b0001
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`define ALU_SHIFTR                              4'b0010
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`define ALU_SHIRTR_ARITH                        4'b0011
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`define ALU_ADD                                 4'b0100
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`define ALU_ADDC                                4'b0101
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`define ALU_SUB                                 4'b0110
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`define ALU_AND                                 4'b0111
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`define ALU_OR                                  4'b1000
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`define ALU_XOR                                 4'b1001
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`define ALU_COMPARE                             4'b1010
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//-----------------------------------------------------------------
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// ALU Instructions
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//-----------------------------------------------------------------
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`define INST_OR32_ALU                            8'h38
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`define INST_OR32_ADD                            8'h00
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`define INST_OR32_ADDC                           8'h01
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`define INST_OR32_AND                            8'h03
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`define INST_OR32_OR                             8'h04
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`define INST_OR32_SLL                            8'h08
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`define INST_OR32_SRA                            8'h28
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`define INST_OR32_SRL                            8'h18
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`define INST_OR32_SUB                            8'h02
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`define INST_OR32_XOR                            8'h05
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`define INST_OR32_MUL                            8'hc6
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`define INST_OR32_MULU                           8'hcb
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//-----------------------------------------------------------------
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// INST_OR32_SHIFTI Instructions
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//-----------------------------------------------------------------
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`define INST_OR32_SHIFTI                         8'h2E
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`define INST_OR32_SLLI                           2'b00
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`define INST_OR32_SRAI                           2'b10
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`define INST_OR32_SRLI                           2'b01
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//-----------------------------------------------------------------
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// General Instructions
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//-----------------------------------------------------------------
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`define INST_OR32_ADDI                           8'h27
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`define INST_OR32_ANDI                           8'h29
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`define INST_OR32_BF                             8'h04
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`define INST_OR32_BNF                            8'h03
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`define INST_OR32_J                              8'h00
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`define INST_OR32_JAL                            8'h01
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`define INST_OR32_JALR                           8'h12
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`define INST_OR32_JR                             8'h11
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`define INST_OR32_MFSPR                          8'h2D
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`define INST_OR32_MOVHI                          8'h06
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`define INST_OR32_MTSPR                          8'h30
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`define INST_OR32_NOP                            8'h05
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`define INST_OR32_ORI                            8'h2A
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`define INST_OR32_RFE                            8'h09
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`define INST_OR32_SB                             8'h36
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`define INST_OR32_SH                             8'h37
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`define INST_OR32_SW                             8'h35
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`define INST_OR32_XORI                           8'h2B
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`define INST_OR32_LBS                            8'h24
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`define INST_OR32_LBZ                            8'h23
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`define INST_OR32_LHS                            8'h26
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`define INST_OR32_LHZ                            8'h25
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`define INST_OR32_LWZ                            8'h21
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`define INST_OR32_LWS                            8'h22
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//-----------------------------------------------------------------
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// Set Flag Instructions
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//-----------------------------------------------------------------
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`define INST_OR32_SFXX                           8'h39
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`define INST_OR32_SFXXI                          8'h2F
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`define INST_OR32_SFMASK                         16'hFD3F
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`define INST_OR32_SFEQ                           16'h0520
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`define INST_OR32_SFGES                          16'h052B
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`define INST_OR32_SFGEU                          16'h0523
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`define INST_OR32_SFGTS                          16'h052A
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`define INST_OR32_SFGTU                          16'h0522
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`define INST_OR32_SFLES                          16'h052D
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`define INST_OR32_SFLEU                          16'h0525
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`define INST_OR32_SFLTS                          16'h052C
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`define INST_OR32_SFLTU                          16'h0524
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`define INST_OR32_SFNE                           16'h0521
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//-----------------------------------------------------------------
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// Misc Instructions
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//-----------------------------------------------------------------
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`define INST_OR32_MISC                           8'h08
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`define INST_OR32_SYS                            8'h20
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`define INST_OR32_TRAP                           8'h21
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`define INST_OR32_CUST1                          8'h1C
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`define INST_OR32_BUBBLE                         8'h3F
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`define OPCODE_INST_BUBBLE                       32'hFC000000
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//-----------------------------------------------------------------
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// SPR Register Map
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//-----------------------------------------------------------------
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`define SPR_REG_VR                               16'h0000
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`define SPR_VERSION_CURRENT                      8'h00
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`define SPR_REG_SR                               16'h0011
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`define SPR_REG_EPCR                             16'h0020
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`define SPR_REG_ESR                              16'h0040
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`define SPR_REG_MACLO                            16'h0080
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`define SPR_REG_MACHI                            16'h0081
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//-----------------------------------------------------------------
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// SR Register bits
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//-----------------------------------------------------------------
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`define SR_SM                                    0
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`define SR_TEE                                   1
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`define SR_IEE                                   2
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`define SR_DCE                                   3
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`define SR_ICE                                   4
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`define SR_DME                                   5
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`define SR_IME                                   6
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`define SR_LEE                                   7
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`define SR_CE                                    8
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`define SR_F                                     9
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`define SR_CY                                    10
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`define SR_OV                                    11
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`define SR_OVE                                   12
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`define SR_DSX                                   13
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`define SR_EPH                                   14
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`define SR_FO                                    15
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`define SR_SUMRA                                 16
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`define SR_ICACHE_FLUSH                          17
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`define SR_DCACHE_FLUSH                          18
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//-----------------------------------------------------------------
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// OR32 Vectors
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// NOTE: These differ from the real OR32 vectors for space reasons
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//-----------------------------------------------------------------
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`define VECTOR_RESET                             32'h00000100
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`define VECTOR_ILLEGAL_INST                      32'h00000200
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`define VECTOR_EXTINT                            32'h00000300
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`define VECTOR_SYSCALL                           32'h00000400
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`define VECTOR_TRAP                              32'h00000600
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`define VECTOR_NMI                               32'h00000700
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`define VECTOR_BUS_ERROR                         32'h00000800

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