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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dfu.v] - Blame information for rev 27

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1 27 ultra_embe 
//-----------------------------------------------------------------
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//                           AltOR32
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//                Alternative Lightweight OpenRisc
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//                            V2.0
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2013
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE.  See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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//-----------------------------------------------------------------
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// Module: Data Forwarding Unit
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//-----------------------------------------------------------------
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module altor32_dfu
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(
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    // Input registers
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    input [4:0]         ra_i /*verilator public*/,
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    input [4:0]         rb_i /*verilator public*/,
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    // Input register contents
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    input [31:0]        ra_regval_i /*verilator public*/,
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    input [31:0]        rb_regval_i /*verilator public*/,
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    // Dest register (EXEC stage)
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    input [4:0]         rd_ex_i/*verilator public*/,
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    // Dest register (WB stage)
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    input [4:0]         rd_wb_i/*verilator public*/,
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    // Load pending / target
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    input               load_pending_i /*verilator public*/,
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    input [4:0]         rd_load_i /*verilator public*/,
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    // Multiplier status
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    input               mult_lo_ex_i /*verilator public*/,
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    input               mult_hi_ex_i /*verilator public*/,
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    input               mult_lo_wb_i /*verilator public*/,
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    input               mult_hi_wb_i /*verilator public*/,
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    // Multiplier result
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    input [63:0]        result_mult_i /*verilator public*/,
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    // Result (EXEC)
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    input [31:0]        result_ex_i /*verilator public*/,
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    // Result (WB)
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    input [31:0]        result_wb_i /*verilator public*/,
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    // Resolved register values
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    output reg [31:0]   result_ra_o /*verilator public*/,
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    output reg [31:0]   result_rb_o /*verilator public*/,
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    // Stall due to failed resolve
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    output reg          stall_o /*verilator public*/
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);
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//-------------------------------------------------------------------
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// Data forwarding unit
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//-------------------------------------------------------------------
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always @ *
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begin
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   // Default to no forwarding
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   result_ra_o  = ra_regval_i;
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   result_rb_o  = rb_regval_i;
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   stall_o      = 1'b0;
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   //---------------------------------------------------------------
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   // RA - Hazard detection & forwarding
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   //---------------------------------------------------------------
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   // Register[ra] hazard detection & forwarding logic
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   // (higher priority = latest results!)
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   if (ra_i != 5'b00000)
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   begin
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       //---------------------------------------------------------------
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       // RA from load (result not ready)
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       //---------------------------------------------------------------
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       if (ra_i == rd_load_i & load_pending_i)
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       begin
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            stall_o     = 1'b1;
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`ifdef CONF_CORE_DEBUG
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            $display(" rA[%d] not ready as load still pending", ra_i);
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`endif
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       end
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       //---------------------------------------------------------------
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       // RA from PC-4 (exec)
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       //---------------------------------------------------------------
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       else if (ra_i == rd_ex_i)
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       begin
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            // Multiplier has one cycle latency, stall if needed now
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            if (mult_lo_ex_i | mult_hi_wb_i)
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                stall_o     = 1'b1;
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            else
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            begin
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                result_ra_o = result_ex_i;
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`ifdef CONF_CORE_DEBUG
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                $display(" rA[%d] forwarded 0x%08x (PC-4)", ra_i, result_ra_o);
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`endif
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            end
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       end
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       //---------------------------------------------------------------
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       // RA from PC-8 (writeback)
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       //---------------------------------------------------------------
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       else if (ra_i == rd_wb_i)
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       begin
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            if (mult_hi_wb_i)
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                result_ra_o = result_mult_i[63:32];
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            else if (mult_lo_wb_i)
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                result_ra_o = result_mult_i[31:0];
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            else
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                result_ra_o = result_wb_i;
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`ifdef CONF_CORE_DEBUG
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            $display(" rA[%d] forwarded 0x%08x (PC-8)", ra_i, result_ra_o);
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`endif
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       end
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   end
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   //---------------------------------------------------------------
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   // RB - Hazard detection & forwarding
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   //---------------------------------------------------------------
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   // Register[rb] hazard detection & forwarding logic
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   // (higher priority = latest results!)
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   if (rb_i != 5'b00000)
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   begin
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       //---------------------------------------------------------------
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       // RB from load (result not ready)
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       //---------------------------------------------------------------
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       if (rb_i == rd_load_i & load_pending_i)
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       begin
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            stall_o     = 1'b1;
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`ifdef CONF_CORE_DEBUG
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            $display(" rB[%d] not ready as load still pending", rb_i);
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`endif
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       end
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       //---------------------------------------------------------------
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       // RB from PC-4 (exec)
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       //---------------------------------------------------------------
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       else if (rb_i == rd_ex_i)
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       begin
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            // Multiplier has one cycle latency, stall if needed now
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            if (mult_lo_ex_i | mult_hi_wb_i)
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                stall_o     = 1'b1;
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            else
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            begin
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                result_rb_o = result_ex_i;
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`ifdef CONF_CORE_DEBUG
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                $display(" rB[%d] forwarded 0x%08x (PC-4)", rb_i, result_rb_o);
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`endif
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            end
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       end
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       //---------------------------------------------------------------
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       // RB from PC-8 (writeback)
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       //---------------------------------------------------------------
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       else if (rb_i == rd_wb_i)
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       begin
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            if (mult_hi_wb_i)
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                result_rb_o = result_mult_i[63:32];
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            else if (mult_lo_wb_i)
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                result_rb_o = result_mult_i[31:0];
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            else
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                result_rb_o = result_wb_i;
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`ifdef CONF_CORE_DEBUG
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            $display(" rB[%d] forwarded 0x%08x (PC-8)", rb_i, result_rb_o);
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`endif
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       end
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   end
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end
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endmodule

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