OpenCores
URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_lfu.v] - Blame information for rev 37

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 ultra_embe
//-----------------------------------------------------------------
2
//                           AltOR32 
3
//                Alternative Lightweight OpenRisc 
4 36 ultra_embe
//                            V2.1
5 27 ultra_embe
//                     Ultra-Embedded.com
6 36 ultra_embe
//                   Copyright 2011 - 2014
7 27 ultra_embe
//
8
//               Email: admin@ultra-embedded.com
9
//
10
//                       License: LGPL
11
//-----------------------------------------------------------------
12
//
13 37 ultra_embe
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
14 27 ultra_embe
//
15
// This source file may be used and distributed without         
16
// restriction provided that this copyright statement is not    
17
// removed from the file and that any derivative work contains  
18
// the original copyright notice and the associated disclaimer. 
19
//
20
// This source file is free software; you can redistribute it   
21
// and/or modify it under the terms of the GNU Lesser General   
22
// Public License as published by the Free Software Foundation; 
23
// either version 2.1 of the License, or (at your option) any   
24
// later version.
25
//
26
// This source is distributed in the hope that it will be       
27
// useful, but WITHOUT ANY WARRANTY; without even the implied   
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
29
// PURPOSE.  See the GNU Lesser General Public License for more 
30
// details.
31
//
32
// You should have received a copy of the GNU Lesser General    
33
// Public License along with this source; if not, write to the 
34
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
35
// Boston, MA  02111-1307  USA
36
//-----------------------------------------------------------------
37
 
38
//-----------------------------------------------------------------
39
// Includes
40
//-----------------------------------------------------------------
41
`include "altor32_defs.v"
42
 
43
//-----------------------------------------------------------------
44
// Module: Load Forwarding Unit
45
//-----------------------------------------------------------------
46
module altor32_lfu
47
(
48
    // Opcode
49
    input [7:0]         opcode_i /*verilator public*/,
50
 
51
    // Memory load result
52
    input [31:0]        mem_result_i /*verilator public*/,
53
    input [1:0]         mem_offset_i /*verilator public*/,
54
 
55
    // Result
56
    output reg [31:0]   load_result_o /*verilator public*/,
57
    output reg          load_insn_o /*verilator public*/
58
);
59
 
60
//-------------------------------------------------------------------
61
// Load forwarding unit
62
//-------------------------------------------------------------------
63
always @ *
64
begin
65
    load_result_o   = 32'h00000000;
66
    load_insn_o     = 1'b0;
67
 
68
    case (opcode_i)
69
 
70
        `INST_OR32_LBS: // l.lbs
71
        begin
72
            case (mem_offset_i)
73
                2'b00 :   load_result_o[7:0] = mem_result_i[31:24];
74
                2'b01 :   load_result_o[7:0] = mem_result_i[23:16];
75
                2'b10 :   load_result_o[7:0] = mem_result_i[15:8];
76
                2'b11 :   load_result_o[7:0] = mem_result_i[7:0];
77
                default : ;
78
            endcase
79
 
80
            // Sign extend LB
81
            if (load_result_o[7] == 1'b1)
82
                load_result_o[31:8] = 24'hFFFFFF;
83
 
84
            load_insn_o = 1'b1;
85
        end
86
 
87
        `INST_OR32_LBZ: // l.lbz
88
        begin
89
            case (mem_offset_i)
90
                2'b00 :   load_result_o[7:0] = mem_result_i[31:24];
91
                2'b01 :   load_result_o[7:0] = mem_result_i[23:16];
92
                2'b10 :   load_result_o[7:0] = mem_result_i[15:8];
93
                2'b11 :   load_result_o[7:0] = mem_result_i[7:0];
94
                default : ;
95
            endcase
96
 
97
            load_insn_o = 1'b1;
98
        end
99
 
100
        `INST_OR32_LHS: // l.lhs
101
        begin
102
            case (mem_offset_i)
103
                2'b00 :   load_result_o[15:0] = mem_result_i[31:16];
104
                2'b10 :   load_result_o[15:0] = mem_result_i[15:0];
105
                default : ;
106
            endcase
107
 
108
            // Sign extend LH
109
            if (load_result_o[15] == 1'b1)
110
                load_result_o[31:16] = 16'hFFFF;
111
 
112
            load_insn_o = 1'b1;
113
        end
114
 
115
        `INST_OR32_LHZ: // l.lhz
116
        begin
117
            case (mem_offset_i)
118
                2'b00 :   load_result_o[15:0] = mem_result_i[31:16];
119
                2'b10 :   load_result_o[15:0] = mem_result_i[15:0];
120
                default : ;
121
            endcase
122
 
123
            load_insn_o = 1'b1;
124
        end
125
 
126
        `INST_OR32_LWZ, `INST_OR32_LWS: // l.lwz l.lws
127
        begin
128
            load_result_o   = mem_result_i;
129
            load_insn_o  = 1'b1;
130
        end
131
 
132
        default :
133
            ;
134
    endcase
135
end
136
 
137
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.