OpenCores
URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_ram_sp.v] - Blame information for rev 36

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 ultra_embe
//-----------------------------------------------------------------
2
//                           AltOR32 
3
//                Alternative Lightweight OpenRisc 
4 36 ultra_embe
//                            V2.1
5 27 ultra_embe
//                     Ultra-Embedded.com
6 36 ultra_embe
//                   Copyright 2011 - 2014
7 27 ultra_embe
//
8
//               Email: admin@ultra-embedded.com
9
//
10
//                       License: LGPL
11
//-----------------------------------------------------------------
12
//
13
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
14
//
15
// This source file may be used and distributed without         
16
// restriction provided that this copyright statement is not    
17
// removed from the file and that any derivative work contains  
18
// the original copyright notice and the associated disclaimer. 
19
//
20
// This source file is free software; you can redistribute it   
21
// and/or modify it under the terms of the GNU Lesser General   
22
// Public License as published by the Free Software Foundation; 
23
// either version 2.1 of the License, or (at your option) any   
24
// later version.
25
//
26
// This source is distributed in the hope that it will be       
27
// useful, but WITHOUT ANY WARRANTY; without even the implied   
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
29
// PURPOSE.  See the GNU Lesser General Public License for more 
30
// details.
31
//
32
// You should have received a copy of the GNU Lesser General    
33
// Public License along with this source; if not, write to the 
34
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
35
// Boston, MA  02111-1307  USA
36
//-----------------------------------------------------------------
37
 
38
//-----------------------------------------------------------------
39
// Module: altor32_ram_sp - Single port RAM (used in cache)
40
//-----------------------------------------------------------------
41 30 ultra_embe
module altor32_ram_sp
42
#(
43
    parameter  [31:0]       WIDTH = 8,
44
    parameter  [31:0]       SIZE = 14
45
)
46 27 ultra_embe
(
47
    input                   clk_i /*verilator public*/,
48
    output [(WIDTH - 1):0]  dat_o /*verilator public*/,
49
    input [(WIDTH - 1):0]   dat_i /*verilator public*/,
50
    input [(SIZE - 1):0]    adr_i /*verilator public*/,
51
    input                   wr_i /*verilator public*/
52
);
53
 
54
//-----------------------------------------------------------------
55
// Registers
56
//-----------------------------------------------------------------
57
reg [(WIDTH - 1):0]     ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
58
reg [(SIZE - 1):0]      rd_addr;
59
 
60
//-----------------------------------------------------------------
61
// Processes
62
//-----------------------------------------------------------------
63
always @ (posedge clk_i)
64
begin
65
    if (wr_i == 1'b1)
66
        ram[adr_i] <= dat_i;
67
    rd_addr <= adr_i;
68
end
69
 
70
//-------------------------------------------------------------------
71
// Combinatorial
72
//-------------------------------------------------------------------
73
assign dat_o = ram[rd_addr];
74
 
75
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.