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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_regfile_sim.v] - Blame information for rev 27

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//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.0
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2013
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
 
//-----------------------------------------------------------------
// Module - Simulation register file
//-----------------------------------------------------------------
module altor32_regfile_sim
(
    input           clk_i               /*verilator public*/,
    input           rst_i               /*verilator public*/,
    input           wr_i                /*verilator public*/,
    input [4:0]     rs_i                /*verilator public*/,
    input [4:0]     rt_i                /*verilator public*/,
    input [4:0]     rd_i                /*verilator public*/,
    output [31:0]   reg_rs_o            /*verilator public*/,
    output [31:0]   reg_rt_o            /*verilator public*/,
    input [31:0]    reg_rd_i            /*verilator public*/
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter       SUPPORT_32REGS = "ENABLED";
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
 
// Register file
reg [31:0] reg_r1_sp;
reg [31:0] reg_r2_fp;
reg [31:0] reg_r3;
reg [31:0] reg_r4;
reg [31:0] reg_r5;
reg [31:0] reg_r6;
reg [31:0] reg_r7;
reg [31:0] reg_r8;
reg [31:0] reg_r9_lr;
reg [31:0] reg_r10;
reg [31:0] reg_r11;
reg [31:0] reg_r12;
reg [31:0] reg_r13;
reg [31:0] reg_r14;
reg [31:0] reg_r15;
reg [31:0] reg_r16;
reg [31:0] reg_r17;
reg [31:0] reg_r18;
reg [31:0] reg_r19;
reg [31:0] reg_r20;
reg [31:0] reg_r21;
reg [31:0] reg_r22;
reg [31:0] reg_r23;
reg [31:0] reg_r24;
reg [31:0] reg_r25;
reg [31:0] reg_r26;
reg [31:0] reg_r27;
reg [31:0] reg_r28;
reg [31:0] reg_r29;
reg [31:0] reg_r30;
reg [31:0] reg_r31;
 
reg [31:0] reg_rs_o;
reg [31:0] reg_rt_o;
 
//-----------------------------------------------------------------
// Register File (for simulation)
//-----------------------------------------------------------------
 
// Synchronous register write back
always @ (posedge clk_i or posedge rst_i)
begin
   if (rst_i)
   begin
        reg_r1_sp <= 32'h00000000;
        reg_r2_fp <= 32'h00000000;
        reg_r3 <= 32'h00000000;
        reg_r4 <= 32'h00000000;
        reg_r5 <= 32'h00000000;
        reg_r6 <= 32'h00000000;
        reg_r7 <= 32'h00000000;
        reg_r8 <= 32'h00000000;
        reg_r9_lr <= 32'h00000000;
        reg_r10 <= 32'h00000000;
        reg_r11 <= 32'h00000000;
        reg_r12 <= 32'h00000000;
        reg_r13 <= 32'h00000000;
        reg_r14 <= 32'h00000000;
        reg_r15 <= 32'h00000000;
        reg_r16 <= 32'h00000000;
        reg_r17 <= 32'h00000000;
        reg_r18 <= 32'h00000000;
        reg_r19 <= 32'h00000000;
        reg_r20 <= 32'h00000000;
        reg_r21 <= 32'h00000000;
        reg_r22 <= 32'h00000000;
        reg_r23 <= 32'h00000000;
        reg_r24 <= 32'h00000000;
        reg_r25 <= 32'h00000000;
        reg_r26 <= 32'h00000000;
        reg_r27 <= 32'h00000000;
        reg_r28 <= 32'h00000000;
        reg_r29 <= 32'h00000000;
        reg_r30 <= 32'h00000000;
        reg_r31 <= 32'h00000000;
   end
   else
   begin
       if (wr_i == 1'b1)
           case (rd_i[4:0])
               5'b00001 :
                       reg_r1_sp <= reg_rd_i;
               5'b00010 :
                       reg_r2_fp <= reg_rd_i;
               5'b00011 :
                       reg_r3 <= reg_rd_i;
               5'b00100 :
                       reg_r4 <= reg_rd_i;
               5'b00101 :
                       reg_r5 <= reg_rd_i;
               5'b00110 :
                       reg_r6 <= reg_rd_i;
               5'b00111 :
                       reg_r7 <= reg_rd_i;
               5'b01000 :
                       reg_r8 <= reg_rd_i;
               5'b01001 :
                       reg_r9_lr <= reg_rd_i;
               5'b01010 :
                       reg_r10 <= reg_rd_i;
               5'b01011 :
                       reg_r11 <= reg_rd_i;
               5'b01100 :
                       reg_r12 <= reg_rd_i;
               5'b01101 :
                       reg_r13 <= reg_rd_i;
               5'b01110 :
                       reg_r14 <= reg_rd_i;
               5'b01111 :
                       reg_r15 <= reg_rd_i;
               5'b10000 :
                       reg_r16 <= reg_rd_i;
               5'b10001 :
                       reg_r17 <= reg_rd_i;
               5'b10010 :
                       reg_r18 <= reg_rd_i;
               5'b10011 :
                       reg_r19 <= reg_rd_i;
               5'b10100 :
                       reg_r20 <= reg_rd_i;
               5'b10101 :
                       reg_r21 <= reg_rd_i;
               5'b10110 :
                       reg_r22 <= reg_rd_i;
               5'b10111 :
                       reg_r23 <= reg_rd_i;
               5'b11000 :
                       reg_r24 <= reg_rd_i;
               5'b11001 :
                       reg_r25 <= reg_rd_i;
               5'b11010 :
                       reg_r26 <= reg_rd_i;
               5'b11011 :
                       reg_r27 <= reg_rd_i;
               5'b11100 :
                       reg_r28 <= reg_rd_i;
               5'b11101 :
                       reg_r29 <= reg_rd_i;
               5'b11110 :
                       reg_r30 <= reg_rd_i;
               5'b11111 :
                       reg_r31 <= reg_rd_i;
               default :
                   ;
           endcase
   end
end
 
generate
if (SUPPORT_32REGS == "ENABLED")
begin
    // Asynchronous Register read (Rs & Rd)
    always @ *
    begin
       case (rs_i)
           5'b00000 :
                   reg_rs_o = 32'h00000000;
           5'b00001 :
                   reg_rs_o = reg_r1_sp;
           5'b00010 :
                   reg_rs_o = reg_r2_fp;
           5'b00011 :
                   reg_rs_o = reg_r3;
           5'b00100 :
                   reg_rs_o = reg_r4;
           5'b00101 :
                   reg_rs_o = reg_r5;
           5'b00110 :
                   reg_rs_o = reg_r6;
           5'b00111 :
                   reg_rs_o = reg_r7;
           5'b01000 :
                   reg_rs_o = reg_r8;
           5'b01001 :
                   reg_rs_o = reg_r9_lr;
           5'b01010 :
                   reg_rs_o = reg_r10;
           5'b01011 :
                   reg_rs_o = reg_r11;
           5'b01100 :
                   reg_rs_o = reg_r12;
           5'b01101 :
                   reg_rs_o = reg_r13;
           5'b01110 :
                   reg_rs_o = reg_r14;
           5'b01111 :
                   reg_rs_o = reg_r15;
           5'b10000 :
                   reg_rs_o = reg_r16;
           5'b10001 :
                   reg_rs_o = reg_r17;
           5'b10010 :
                   reg_rs_o = reg_r18;
           5'b10011 :
                   reg_rs_o = reg_r19;
           5'b10100 :
                   reg_rs_o = reg_r20;
           5'b10101 :
                   reg_rs_o = reg_r21;
           5'b10110 :
                   reg_rs_o = reg_r22;
           5'b10111 :
                   reg_rs_o = reg_r23;
           5'b11000 :
                   reg_rs_o = reg_r24;
           5'b11001 :
                   reg_rs_o = reg_r25;
           5'b11010 :
                   reg_rs_o = reg_r26;
           5'b11011 :
                   reg_rs_o = reg_r27;
           5'b11100 :
                   reg_rs_o = reg_r28;
           5'b11101 :
                   reg_rs_o = reg_r29;
           5'b11110 :
                   reg_rs_o = reg_r30;
           5'b11111 :
                   reg_rs_o = reg_r31;
           default :
                   reg_rs_o = 32'h00000000;
       endcase
 
       case (rt_i)
           5'b00000 :
                   reg_rt_o = 32'h00000000;
           5'b00001 :
                   reg_rt_o = reg_r1_sp;
           5'b00010 :
                   reg_rt_o = reg_r2_fp;
           5'b00011 :
                   reg_rt_o = reg_r3;
           5'b00100 :
                   reg_rt_o = reg_r4;
           5'b00101 :
                   reg_rt_o = reg_r5;
           5'b00110 :
                   reg_rt_o = reg_r6;
           5'b00111 :
                   reg_rt_o = reg_r7;
           5'b01000 :
                   reg_rt_o = reg_r8;
           5'b01001 :
                   reg_rt_o = reg_r9_lr;
           5'b01010 :
                   reg_rt_o = reg_r10;
           5'b01011 :
                   reg_rt_o = reg_r11;
           5'b01100 :
                   reg_rt_o = reg_r12;
           5'b01101 :
                   reg_rt_o = reg_r13;
           5'b01110 :
                   reg_rt_o = reg_r14;
           5'b01111 :
                   reg_rt_o = reg_r15;
           5'b10000 :
                   reg_rt_o = reg_r16;
           5'b10001 :
                   reg_rt_o = reg_r17;
           5'b10010 :
                   reg_rt_o = reg_r18;
           5'b10011 :
                   reg_rt_o = reg_r19;
           5'b10100 :
                   reg_rt_o = reg_r20;
           5'b10101 :
                   reg_rt_o = reg_r21;
           5'b10110 :
                   reg_rt_o = reg_r22;
           5'b10111 :
                   reg_rt_o = reg_r23;
           5'b11000 :
                   reg_rt_o = reg_r24;
           5'b11001 :
                   reg_rt_o = reg_r25;
           5'b11010 :
                   reg_rt_o = reg_r26;
           5'b11011 :
                   reg_rt_o = reg_r27;
           5'b11100 :
                   reg_rt_o = reg_r28;
           5'b11101 :
                   reg_rt_o = reg_r29;
           5'b11110 :
                   reg_rt_o = reg_r30;
           5'b11111 :
                   reg_rt_o = reg_r31;
           default :
                   reg_rt_o = 32'h00000000;
       endcase
    end
end
else
begin
    // Asynchronous Register read (Rs & Rd)
    always @ *
    begin
       case (rs_i)
           5'b00000 :
                   reg_rs_o = 32'h00000000;
           5'b00001 :
                   reg_rs_o = reg_r1_sp;
           5'b00010 :
                   reg_rs_o = reg_r2_fp;
           5'b00011 :
                   reg_rs_o = reg_r3;
           5'b00100 :
                   reg_rs_o = reg_r4;
           5'b00101 :
                   reg_rs_o = reg_r5;
           5'b00110 :
                   reg_rs_o = reg_r6;
           5'b00111 :
                   reg_rs_o = reg_r7;
           5'b01000 :
                   reg_rs_o = reg_r8;
           5'b01001 :
                   reg_rs_o = reg_r9_lr;
           5'b01010 :
                   reg_rs_o = reg_r10;
           5'b01011 :
                   reg_rs_o = reg_r11;
           5'b01100 :
                   reg_rs_o = reg_r12;
           5'b01101 :
                   reg_rs_o = reg_r13;
           5'b01110 :
                   reg_rs_o = reg_r14;
           5'b01111 :
                   reg_rs_o = reg_r15;
           default :
                   reg_rs_o = 32'h00000000;
       endcase
 
       case (rt_i)
           5'b00000 :
                   reg_rt_o = 32'h00000000;
           5'b00001 :
                   reg_rt_o = reg_r1_sp;
           5'b00010 :
                   reg_rt_o = reg_r2_fp;
           5'b00011 :
                   reg_rt_o = reg_r3;
           5'b00100 :
                   reg_rt_o = reg_r4;
           5'b00101 :
                   reg_rt_o = reg_r5;
           5'b00110 :
                   reg_rt_o = reg_r6;
           5'b00111 :
                   reg_rt_o = reg_r7;
           5'b01000 :
                   reg_rt_o = reg_r8;
           5'b01001 :
                   reg_rt_o = reg_r9_lr;
           5'b01010 :
                   reg_rt_o = reg_r10;
           5'b01011 :
                   reg_rt_o = reg_r11;
           5'b01100 :
                   reg_rt_o = reg_r12;
           5'b01101 :
                   reg_rt_o = reg_r13;
           5'b01110 :
                   reg_rt_o = reg_r14;
           5'b01111 :
                   reg_rt_o = reg_r15;
           default :
                   reg_rt_o = 32'h00000000;
       endcase
    end
end
endgenerate
 
endmodule

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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_regfile_sim.v] - Blame information for rev 27

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4			`// V2.0`
5			`// Ultra-Embedded.com`
6			`// Copyright 2011 - 2013`
7			`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13			`// Copyright (C) 2011 - 2013 Ultra-Embedded.com`
14			`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// Includes`
40			`//-----------------------------------------------------------------`
41			`include "altor32_defs.v"
42
43			`//-----------------------------------------------------------------`
44			`// Module - Simulation register file`
45			`//-----------------------------------------------------------------`
46			`module altor32_regfile_sim`
47			`(`
48			`input clk_i /verilator public/,`
49			`input rst_i /verilator public/,`
50			`input wr_i /verilator public/,`
51			`input [4:0] rs_i /verilator public/,`
52			`input [4:0] rt_i /verilator public/,`
53			`input [4:0] rd_i /verilator public/,`
54			`output [31:0] reg_rs_o /verilator public/,`
55			`output [31:0] reg_rt_o /verilator public/,`
56			`input [31:0] reg_rd_i /verilator public/`
57			`);`
58
59			`//-----------------------------------------------------------------`
60			`// Params`
61			`//-----------------------------------------------------------------`
62			`parameter SUPPORT_32REGS = "ENABLED";`
63
64			`//-----------------------------------------------------------------`
65			`// Registers`
66			`//-----------------------------------------------------------------`
67
68			`// Register file`
69			`reg [31:0] reg_r1_sp;`
70			`reg [31:0] reg_r2_fp;`
71			`reg [31:0] reg_r3;`
72			`reg [31:0] reg_r4;`
73			`reg [31:0] reg_r5;`
74			`reg [31:0] reg_r6;`
75			`reg [31:0] reg_r7;`
76			`reg [31:0] reg_r8;`
77			`reg [31:0] reg_r9_lr;`
78			`reg [31:0] reg_r10;`
79			`reg [31:0] reg_r11;`
80			`reg [31:0] reg_r12;`
81			`reg [31:0] reg_r13;`
82			`reg [31:0] reg_r14;`
83			`reg [31:0] reg_r15;`
84			`reg [31:0] reg_r16;`
85			`reg [31:0] reg_r17;`
86			`reg [31:0] reg_r18;`
87			`reg [31:0] reg_r19;`
88			`reg [31:0] reg_r20;`
89			`reg [31:0] reg_r21;`
90			`reg [31:0] reg_r22;`
91			`reg [31:0] reg_r23;`
92			`reg [31:0] reg_r24;`
93			`reg [31:0] reg_r25;`
94			`reg [31:0] reg_r26;`
95			`reg [31:0] reg_r27;`
96			`reg [31:0] reg_r28;`
97			`reg [31:0] reg_r29;`
98			`reg [31:0] reg_r30;`
99			`reg [31:0] reg_r31;`
100
101			`reg [31:0] reg_rs_o;`
102			`reg [31:0] reg_rt_o;`
103
104			`//-----------------------------------------------------------------`
105			`// Register File (for simulation)`
106			`//-----------------------------------------------------------------`
107
108			`// Synchronous register write back`
109			`always @ (posedge clk_i or posedge rst_i)`
110			`begin`
111			`if (rst_i)`
112			`begin`
113			`reg_r1_sp <= 32'h00000000;`
114			`reg_r2_fp <= 32'h00000000;`
115			`reg_r3 <= 32'h00000000;`
116			`reg_r4 <= 32'h00000000;`
117			`reg_r5 <= 32'h00000000;`
118			`reg_r6 <= 32'h00000000;`
119			`reg_r7 <= 32'h00000000;`
120			`reg_r8 <= 32'h00000000;`
121			`reg_r9_lr <= 32'h00000000;`
122			`reg_r10 <= 32'h00000000;`
123			`reg_r11 <= 32'h00000000;`
124			`reg_r12 <= 32'h00000000;`
125			`reg_r13 <= 32'h00000000;`
126			`reg_r14 <= 32'h00000000;`
127			`reg_r15 <= 32'h00000000;`
128			`reg_r16 <= 32'h00000000;`
129			`reg_r17 <= 32'h00000000;`
130			`reg_r18 <= 32'h00000000;`
131			`reg_r19 <= 32'h00000000;`
132			`reg_r20 <= 32'h00000000;`
133			`reg_r21 <= 32'h00000000;`
134			`reg_r22 <= 32'h00000000;`
135			`reg_r23 <= 32'h00000000;`
136			`reg_r24 <= 32'h00000000;`
137			`reg_r25 <= 32'h00000000;`
138			`reg_r26 <= 32'h00000000;`
139			`reg_r27 <= 32'h00000000;`
140			`reg_r28 <= 32'h00000000;`
141			`reg_r29 <= 32'h00000000;`
142			`reg_r30 <= 32'h00000000;`
143			`reg_r31 <= 32'h00000000;`
144			`end`
145			`else`
146			`begin`
147			`if (wr_i == 1'b1)`
148			`case (rd_i[4:0])`
149			`5'b00001 :`
150			`reg_r1_sp <= reg_rd_i;`
151			`5'b00010 :`
152			`reg_r2_fp <= reg_rd_i;`
153			`5'b00011 :`
154			`reg_r3 <= reg_rd_i;`
155			`5'b00100 :`
156			`reg_r4 <= reg_rd_i;`
157			`5'b00101 :`
158			`reg_r5 <= reg_rd_i;`
159			`5'b00110 :`
160			`reg_r6 <= reg_rd_i;`
161			`5'b00111 :`
162			`reg_r7 <= reg_rd_i;`
163			`5'b01000 :`
164			`reg_r8 <= reg_rd_i;`
165			`5'b01001 :`
166			`reg_r9_lr <= reg_rd_i;`
167			`5'b01010 :`
168			`reg_r10 <= reg_rd_i;`
169			`5'b01011 :`
170			`reg_r11 <= reg_rd_i;`
171			`5'b01100 :`
172			`reg_r12 <= reg_rd_i;`
173			`5'b01101 :`
174			`reg_r13 <= reg_rd_i;`
175			`5'b01110 :`
176			`reg_r14 <= reg_rd_i;`
177			`5'b01111 :`
178			`reg_r15 <= reg_rd_i;`
179			`5'b10000 :`
180			`reg_r16 <= reg_rd_i;`
181			`5'b10001 :`
182			`reg_r17 <= reg_rd_i;`
183			`5'b10010 :`
184			`reg_r18 <= reg_rd_i;`
185			`5'b10011 :`
186			`reg_r19 <= reg_rd_i;`
187			`5'b10100 :`
188			`reg_r20 <= reg_rd_i;`
189			`5'b10101 :`
190			`reg_r21 <= reg_rd_i;`
191			`5'b10110 :`
192			`reg_r22 <= reg_rd_i;`
193			`5'b10111 :`
194			`reg_r23 <= reg_rd_i;`
195			`5'b11000 :`
196			`reg_r24 <= reg_rd_i;`
197			`5'b11001 :`
198			`reg_r25 <= reg_rd_i;`
199			`5'b11010 :`
200			`reg_r26 <= reg_rd_i;`
201			`5'b11011 :`
202			`reg_r27 <= reg_rd_i;`
203			`5'b11100 :`
204			`reg_r28 <= reg_rd_i;`
205			`5'b11101 :`
206			`reg_r29 <= reg_rd_i;`
207			`5'b11110 :`
208			`reg_r30 <= reg_rd_i;`
209			`5'b11111 :`
210			`reg_r31 <= reg_rd_i;`
211			`default :`
212			`;`
213			`endcase`
214			`end`
215			`end`
216
217			`generate`
218			`if (SUPPORT_32REGS == "ENABLED")`
219			`begin`
220			`// Asynchronous Register read (Rs & Rd)`
221			`always @ *`
222			`begin`
223			`case (rs_i)`
224			`5'b00000 :`
225			`reg_rs_o = 32'h00000000;`
226			`5'b00001 :`
227			`reg_rs_o = reg_r1_sp;`
228			`5'b00010 :`
229			`reg_rs_o = reg_r2_fp;`
230			`5'b00011 :`
231			`reg_rs_o = reg_r3;`
232			`5'b00100 :`
233			`reg_rs_o = reg_r4;`
234			`5'b00101 :`
235			`reg_rs_o = reg_r5;`
236			`5'b00110 :`
237			`reg_rs_o = reg_r6;`
238			`5'b00111 :`
239			`reg_rs_o = reg_r7;`
240			`5'b01000 :`
241			`reg_rs_o = reg_r8;`
242			`5'b01001 :`
243			`reg_rs_o = reg_r9_lr;`
244			`5'b01010 :`
245			`reg_rs_o = reg_r10;`
246			`5'b01011 :`
247			`reg_rs_o = reg_r11;`
248			`5'b01100 :`
249			`reg_rs_o = reg_r12;`
250			`5'b01101 :`
251			`reg_rs_o = reg_r13;`
252			`5'b01110 :`
253			`reg_rs_o = reg_r14;`
254			`5'b01111 :`
255			`reg_rs_o = reg_r15;`
256			`5'b10000 :`
257			`reg_rs_o = reg_r16;`
258			`5'b10001 :`
259			`reg_rs_o = reg_r17;`
260			`5'b10010 :`
261			`reg_rs_o = reg_r18;`
262			`5'b10011 :`
263			`reg_rs_o = reg_r19;`
264			`5'b10100 :`
265			`reg_rs_o = reg_r20;`
266			`5'b10101 :`
267			`reg_rs_o = reg_r21;`
268			`5'b10110 :`
269			`reg_rs_o = reg_r22;`
270			`5'b10111 :`
271			`reg_rs_o = reg_r23;`
272			`5'b11000 :`
273			`reg_rs_o = reg_r24;`
274			`5'b11001 :`
275			`reg_rs_o = reg_r25;`
276			`5'b11010 :`
277			`reg_rs_o = reg_r26;`
278			`5'b11011 :`
279			`reg_rs_o = reg_r27;`
280			`5'b11100 :`
281			`reg_rs_o = reg_r28;`
282			`5'b11101 :`
283			`reg_rs_o = reg_r29;`
284			`5'b11110 :`
285			`reg_rs_o = reg_r30;`
286			`5'b11111 :`
287			`reg_rs_o = reg_r31;`
288			`default :`
289			`reg_rs_o = 32'h00000000;`
290			`endcase`
291
292			`case (rt_i)`
293			`5'b00000 :`
294			`reg_rt_o = 32'h00000000;`
295			`5'b00001 :`
296			`reg_rt_o = reg_r1_sp;`
297			`5'b00010 :`
298			`reg_rt_o = reg_r2_fp;`
299			`5'b00011 :`
300			`reg_rt_o = reg_r3;`
301			`5'b00100 :`
302			`reg_rt_o = reg_r4;`
303			`5'b00101 :`
304			`reg_rt_o = reg_r5;`
305			`5'b00110 :`
306			`reg_rt_o = reg_r6;`
307			`5'b00111 :`
308			`reg_rt_o = reg_r7;`
309			`5'b01000 :`
310			`reg_rt_o = reg_r8;`
311			`5'b01001 :`
312			`reg_rt_o = reg_r9_lr;`
313			`5'b01010 :`
314			`reg_rt_o = reg_r10;`
315			`5'b01011 :`
316			`reg_rt_o = reg_r11;`
317			`5'b01100 :`
318			`reg_rt_o = reg_r12;`
319			`5'b01101 :`
320			`reg_rt_o = reg_r13;`
321			`5'b01110 :`
322			`reg_rt_o = reg_r14;`
323			`5'b01111 :`
324			`reg_rt_o = reg_r15;`
325			`5'b10000 :`
326			`reg_rt_o = reg_r16;`
327			`5'b10001 :`
328			`reg_rt_o = reg_r17;`
329			`5'b10010 :`
330			`reg_rt_o = reg_r18;`
331			`5'b10011 :`
332			`reg_rt_o = reg_r19;`
333			`5'b10100 :`
334			`reg_rt_o = reg_r20;`
335			`5'b10101 :`
336			`reg_rt_o = reg_r21;`
337			`5'b10110 :`
338			`reg_rt_o = reg_r22;`
339			`5'b10111 :`
340			`reg_rt_o = reg_r23;`
341			`5'b11000 :`
342			`reg_rt_o = reg_r24;`
343			`5'b11001 :`
344			`reg_rt_o = reg_r25;`
345			`5'b11010 :`
346			`reg_rt_o = reg_r26;`
347			`5'b11011 :`
348			`reg_rt_o = reg_r27;`
349			`5'b11100 :`
350			`reg_rt_o = reg_r28;`
351			`5'b11101 :`
352			`reg_rt_o = reg_r29;`
353			`5'b11110 :`
354			`reg_rt_o = reg_r30;`
355			`5'b11111 :`
356			`reg_rt_o = reg_r31;`
357			`default :`
358			`reg_rt_o = 32'h00000000;`
359			`endcase`
360			`end`
361			`end`
362			`else`
363			`begin`
364			`// Asynchronous Register read (Rs & Rd)`
365			`always @ *`
366			`begin`
367			`case (rs_i)`
368			`5'b00000 :`
369			`reg_rs_o = 32'h00000000;`
370			`5'b00001 :`
371			`reg_rs_o = reg_r1_sp;`
372			`5'b00010 :`
373			`reg_rs_o = reg_r2_fp;`
374			`5'b00011 :`
375			`reg_rs_o = reg_r3;`
376			`5'b00100 :`
377			`reg_rs_o = reg_r4;`
378			`5'b00101 :`
379			`reg_rs_o = reg_r5;`
380			`5'b00110 :`
381			`reg_rs_o = reg_r6;`
382			`5'b00111 :`
383			`reg_rs_o = reg_r7;`
384			`5'b01000 :`
385			`reg_rs_o = reg_r8;`
386			`5'b01001 :`
387			`reg_rs_o = reg_r9_lr;`
388			`5'b01010 :`
389			`reg_rs_o = reg_r10;`
390			`5'b01011 :`
391			`reg_rs_o = reg_r11;`
392			`5'b01100 :`
393			`reg_rs_o = reg_r12;`
394			`5'b01101 :`
395			`reg_rs_o = reg_r13;`
396			`5'b01110 :`
397			`reg_rs_o = reg_r14;`
398			`5'b01111 :`
399			`reg_rs_o = reg_r15;`
400			`default :`
401			`reg_rs_o = 32'h00000000;`
402			`endcase`
403
404			`case (rt_i)`
405			`5'b00000 :`
406			`reg_rt_o = 32'h00000000;`
407			`5'b00001 :`
408			`reg_rt_o = reg_r1_sp;`
409			`5'b00010 :`
410			`reg_rt_o = reg_r2_fp;`
411			`5'b00011 :`
412			`reg_rt_o = reg_r3;`
413			`5'b00100 :`
414			`reg_rt_o = reg_r4;`
415			`5'b00101 :`
416			`reg_rt_o = reg_r5;`
417			`5'b00110 :`
418			`reg_rt_o = reg_r6;`
419			`5'b00111 :`
420			`reg_rt_o = reg_r7;`
421			`5'b01000 :`
422			`reg_rt_o = reg_r8;`
423			`5'b01001 :`
424			`reg_rt_o = reg_r9_lr;`
425			`5'b01010 :`
426			`reg_rt_o = reg_r10;`
427			`5'b01011 :`
428			`reg_rt_o = reg_r11;`
429			`5'b01100 :`
430			`reg_rt_o = reg_r12;`
431			`5'b01101 :`
432			`reg_rt_o = reg_r13;`
433			`5'b01110 :`
434			`reg_rt_o = reg_r14;`
435			`5'b01111 :`
436			`reg_rt_o = reg_r15;`
437			`default :`
438			`reg_rt_o = 32'h00000000;`
439			`endcase`
440			`end`
441			`end`
442			`endgenerate`
443
444			`endmodule`