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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_wb_fetch.v] - Blame information for rev 37

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1 37 ultra_embe
//-----------------------------------------------------------------
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//                           AltOR32 
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//                Alternative Lightweight OpenRisc 
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//                            V2.1
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2014
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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// This source file may be used and distributed without         
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// restriction provided that this copyright statement is not    
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// removed from the file and that any derivative work contains  
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// the original copyright notice and the associated disclaimer. 
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//
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// This source file is free software; you can redistribute it   
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// and/or modify it under the terms of the GNU Lesser General   
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// Public License as published by the Free Software Foundation; 
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// either version 2.1 of the License, or (at your option) any   
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// later version.
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//
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// This source is distributed in the hope that it will be       
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// useful, but WITHOUT ANY WARRANTY; without even the implied   
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
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// PURPOSE.  See the GNU Lesser General Public License for more 
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// details.
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//
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// You should have received a copy of the GNU Lesser General    
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// Public License along with this source; if not, write to the 
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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//-----------------------------------------------------------------
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// Module - Wishbone fetch unit
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//-----------------------------------------------------------------
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module altor32_wb_fetch
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(
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    input                       clk_i /*verilator public*/,
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    input                       rst_i /*verilator public*/,
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    // Fetch
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    input                       fetch_i /*verilator public*/,
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    input                       burst_i /*verilator public*/,
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    input [31:0]                address_i /*verilator public*/,
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    // Response
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    output [31:0]               resp_addr_o /*verilator public*/,
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    output [31:0]               data_o /*verilator public*/,
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    output                      valid_o /*verilator public*/,
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    output                      final_o /*verilator public*/,
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    // Memory interface
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    output reg [31:0]           wbm_addr_o /*verilator public*/,
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    input [31:0]                wbm_dat_i /*verilator public*/,
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    output reg [2:0]            wbm_cti_o /*verilator public*/,
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    output reg                  wbm_cyc_o /*verilator public*/,
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    output reg                  wbm_stb_o /*verilator public*/,
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    input                       wbm_stall_i/*verilator public*/,
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    input                       wbm_ack_i/*verilator public*/
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);
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//-----------------------------------------------------------------
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// Params
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//-----------------------------------------------------------------
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parameter FETCH_WORDS_W             = 3; /* 2 ^ 3 * 4 = 32 */
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parameter FETCH_BYTES_W             = FETCH_WORDS_W + 2;
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parameter WB_CTI_BURST              = 3'b010;
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parameter WB_CTI_FINAL              = 3'b111;
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//-----------------------------------------------------------------
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// Registers / Wires
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//-----------------------------------------------------------------
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// Word currently being fetched within a line
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reg [FETCH_WORDS_W-1:0]  fetch_word_q;
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reg [FETCH_WORDS_W-1:0]  resp_word_q;
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wire [FETCH_WORDS_W-1:0] next_word_w  = fetch_word_q + 1;
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wire penultimate_word_w  = (fetch_word_q == ({FETCH_WORDS_W{1'b1}}-1));
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wire final_resp_w        = ((resp_word_q  == {FETCH_WORDS_W{1'b1}}) | ~burst_i);
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//-----------------------------------------------------------------
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// Pipelined Wishbone Master
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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begin
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   if (rst_i == 1'b1)
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   begin
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        wbm_addr_o      <= 32'h00000000;
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        wbm_cti_o       <= 3'b0;
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        wbm_stb_o       <= 1'b0;
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        wbm_cyc_o       <= 1'b0;
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        fetch_word_q    <= {FETCH_WORDS_W{1'b0}};
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        resp_word_q     <= {FETCH_WORDS_W{1'b0}};
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   end
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   else
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   begin
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        // Idle
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        if (!wbm_cyc_o)
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        begin
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            if (fetch_i)
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            begin
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                if (burst_i)
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                begin
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                    wbm_addr_o      <= {address_i[31:FETCH_BYTES_W], {FETCH_BYTES_W{1'b0}}};
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                    fetch_word_q    <= {FETCH_WORDS_W{1'b0}};
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                    resp_word_q     <= {FETCH_WORDS_W{1'b0}};
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                    // Incrementing linear burst
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                    wbm_cti_o       <= WB_CTI_BURST;
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                end
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                else
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                begin
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                    wbm_addr_o      <= address_i;
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                    resp_word_q     <= address_i[FETCH_BYTES_W-1:2];
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                    // Single fetch
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                    wbm_cti_o       <= WB_CTI_FINAL;
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                end
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                // Start fetch from memory
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                wbm_stb_o           <= 1'b1;
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                wbm_cyc_o           <= 1'b1;
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            end
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        end
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        // Access in-progress
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        else
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        begin
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            // Command accepted
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            if (~wbm_stall_i)
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            begin
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                // Fetch next word for line
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                if (wbm_cti_o != WB_CTI_FINAL)
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                begin
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                    wbm_addr_o      <= {wbm_addr_o[31:FETCH_BYTES_W], next_word_w, 2'b0};
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                    fetch_word_q    <= next_word_w;
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                    // Final word to read?
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                    if (penultimate_word_w)
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                        wbm_cti_o   <= WB_CTI_FINAL;
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                end
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                // Fetch complete
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                else
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                    wbm_stb_o       <= 1'b0;
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            end
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            // Response
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            if (wbm_ack_i)
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                resp_word_q         <= resp_word_q + 1;
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            // Last response?
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            if (final_o)
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                wbm_cyc_o           <= 1'b0;
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        end
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   end
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end
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// Response
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assign data_o       = wbm_dat_i;
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assign valid_o      = wbm_ack_i;
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assign final_o      = final_resp_w & wbm_ack_i;
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assign resp_addr_o  = {address_i[31:FETCH_BYTES_W], resp_word_q, 2'b0};
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endmodule

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