OpenCores
URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_writeback.v] - Blame information for rev 40

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 ultra_embe
//-----------------------------------------------------------------
2
//                           AltOR32 
3
//                Alternative Lightweight OpenRisc 
4 36 ultra_embe
//                            V2.1
5 27 ultra_embe
//                     Ultra-Embedded.com
6 36 ultra_embe
//                   Copyright 2011 - 2014
7 27 ultra_embe
//
8
//               Email: admin@ultra-embedded.com
9
//
10
//                       License: LGPL
11
//-----------------------------------------------------------------
12
//
13 37 ultra_embe
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
14 27 ultra_embe
//
15
// This source file may be used and distributed without         
16
// restriction provided that this copyright statement is not    
17
// removed from the file and that any derivative work contains  
18
// the original copyright notice and the associated disclaimer. 
19
//
20
// This source file is free software; you can redistribute it   
21
// and/or modify it under the terms of the GNU Lesser General   
22
// Public License as published by the Free Software Foundation; 
23
// either version 2.1 of the License, or (at your option) any   
24
// later version.
25
//
26
// This source is distributed in the hope that it will be       
27
// useful, but WITHOUT ANY WARRANTY; without even the implied   
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
29
// PURPOSE.  See the GNU Lesser General Public License for more 
30
// details.
31
//
32
// You should have received a copy of the GNU Lesser General    
33
// Public License along with this source; if not, write to the 
34
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
35
// Boston, MA  02111-1307  USA
36
//-----------------------------------------------------------------
37
 
38
//-----------------------------------------------------------------
39
// Includes
40
//-----------------------------------------------------------------
41
`include "altor32_defs.v"
42
 
43
//-----------------------------------------------------------------
44
// Module - Writeback
45
//-----------------------------------------------------------------
46
module altor32_writeback
47
(
48
    // General
49
    input               clk_i /*verilator public*/,
50
    input               rst_i /*verilator public*/,
51
 
52
    // Opcode
53
    input [31:0]        opcode_i /*verilator public*/,
54
 
55
    // Register target
56
    input [4:0]         rd_i /*verilator public*/,
57
 
58
    // ALU result
59
    input [31:0]        alu_result_i /*verilator public*/,
60
 
61
    // Memory load result
62
    input [31:0]        mem_result_i /*verilator public*/,
63
    input [1:0]         mem_offset_i /*verilator public*/,
64
    input               mem_ready_i /*verilator public*/,
65
 
66
    // Multiplier result
67 40 ultra_embe
    input [63:0]        mult_result_i /*verilator public*/,
68 27 ultra_embe
 
69
    // Outputs
70 40 ultra_embe
    output reg          write_enable_o /*verilator public*/,
71
    output reg [4:0]    write_addr_o /*verilator public*/,
72
    output reg [31:0]   write_data_o /*verilator public*/
73 27 ultra_embe
);
74
 
75
//-----------------------------------------------------------------
76 40 ultra_embe
// Registers / Wires
77 27 ultra_embe
//-----------------------------------------------------------------
78
 
79
// Register address
80 37 ultra_embe
reg [4:0]  rd_q;
81 27 ultra_embe
 
82
// Register writeback value
83 37 ultra_embe
reg [31:0] result_q;
84 27 ultra_embe
 
85 37 ultra_embe
reg [7:0]  opcode_q;
86 27 ultra_embe
 
87
// Register writeback enable
88 37 ultra_embe
reg        write_rd_q;
89 27 ultra_embe
 
90 40 ultra_embe
reg [1:0]  mem_offset_q;
91
 
92 27 ultra_embe
//-------------------------------------------------------------------
93 40 ultra_embe
// Pipeline Registers
94 27 ultra_embe
//-------------------------------------------------------------------
95
always @ (posedge clk_i or posedge rst_i)
96
begin
97
   if (rst_i == 1'b1)
98
   begin
99 37 ultra_embe
       write_rd_q   <= 1'b1;
100
       result_q     <= 32'h00000000;
101
       rd_q         <= 5'b00000;
102
       opcode_q     <= 8'b0;
103 40 ultra_embe
       mem_offset_q <= 2'b0;
104 27 ultra_embe
   end
105
   else
106 37 ultra_embe
   begin
107
        rd_q        <= rd_i;
108
        result_q    <= alu_result_i;
109 27 ultra_embe
 
110 40 ultra_embe
        opcode_q    <= {2'b00,opcode_i[31:26]};
111
        mem_offset_q<= mem_offset_i;
112
 
113 27 ultra_embe
        // Register writeback required?
114
        if (rd_i != 5'b00000)
115 37 ultra_embe
            write_rd_q  <= 1'b1;
116
        else
117
            write_rd_q  <= 1'b0;
118 27 ultra_embe
   end
119
end
120
 
121
//-------------------------------------------------------------------
122
// Load result resolve
123
//-------------------------------------------------------------------
124 37 ultra_embe
wire            load_inst_w;
125
wire [31:0]     load_result_w;
126 27 ultra_embe
 
127
altor32_lfu
128
u_lfu
129
(
130
    // Opcode
131 37 ultra_embe
    .opcode_i(opcode_q),
132 27 ultra_embe
 
133
    // Memory load result
134
    .mem_result_i(mem_result_i),
135 40 ultra_embe
    .mem_offset_i(mem_offset_q),
136 27 ultra_embe
 
137
    // Result
138 37 ultra_embe
    .load_result_o(load_result_w),
139
    .load_insn_o(load_inst_w)
140 27 ultra_embe
);
141
 
142
//-------------------------------------------------------------------
143 40 ultra_embe
// Writeback
144 27 ultra_embe
//-------------------------------------------------------------------
145 40 ultra_embe
always @ *
146
begin
147
    write_addr_o = rd_q;
148 27 ultra_embe
 
149 40 ultra_embe
    // Load result
150
    if (load_inst_w)
151
    begin
152
        write_enable_o = write_rd_q & mem_ready_i;
153
        write_data_o   = load_result_w;
154
    end
155
    // Normal ALU instruction
156
    else
157
    begin
158
        write_enable_o = write_rd_q;
159
        write_data_o   = result_q;
160
    end
161
end
162
 
163 27 ultra_embe
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.