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[/] [altor32/] [trunk/] [rtl/] [peripheral/] [intr_periph.v] - Blame information for rev 27

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1 27 ultra_embe
//-----------------------------------------------------------------
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//                           AltOR32 
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//                Alternative Lightweight OpenRisc 
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//                            V2.0
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2013
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without         
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// restriction provided that this copyright statement is not    
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// removed from the file and that any derivative work contains  
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// the original copyright notice and the associated disclaimer. 
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//
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// This source file is free software; you can redistribute it   
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// and/or modify it under the terms of the GNU Lesser General   
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// Public License as published by the Free Software Foundation; 
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// either version 2.1 of the License, or (at your option) any   
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// later version.
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//
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// This source is distributed in the hope that it will be       
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// useful, but WITHOUT ANY WARRANTY; without even the implied   
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
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// PURPOSE.  See the GNU Lesser General Public License for more 
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// details.
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//
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// You should have received a copy of the GNU Lesser General    
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// Public License along with this source; if not, write to the 
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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//-----------------------------------------------------------------
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`include "intr_defs.v"
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//-----------------------------------------------------------------
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// Module:
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//-----------------------------------------------------------------
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module intr_periph
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(
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    // General - Clocking & Reset
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    clk_i,
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    rst_i,
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    intr_o,
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    // Interrupts
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    intr0_i,
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    intr1_i,
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    intr2_i,
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    intr3_i,
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    intr4_i,
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    intr5_i,
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    intr6_i,
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    intr7_i,
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    intr_ext_i,
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    // Peripheral bus
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    addr_i,
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    data_o,
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    data_i,
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    wr_i,
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    rd_i
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);
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//-----------------------------------------------------------------
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// Params
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//-----------------------------------------------------------------
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parameter           EXTERNAL_INTERRUPTS = 1;
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parameter           INTERRUPT_COUNT     = EXTERNAL_INTERRUPTS + 8;
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//-----------------------------------------------------------------
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// I/O
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//-----------------------------------------------------------------
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input               clk_i /*verilator public*/;
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input               rst_i /*verilator public*/;
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output              intr_o /*verilator public*/;
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input               intr0_i /*verilator public*/;
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input               intr1_i /*verilator public*/;
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input               intr2_i /*verilator public*/;
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input               intr3_i /*verilator public*/;
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input               intr4_i /*verilator public*/;
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input               intr5_i /*verilator public*/;
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input               intr6_i /*verilator public*/;
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input               intr7_i /*verilator public*/;
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input [(EXTERNAL_INTERRUPTS - 1):0] intr_ext_i /*verilator public*/;
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input [7:0]         addr_i /*verilator public*/;
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output [31:0]       data_o /*verilator public*/;
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input [31:0]        data_i /*verilator public*/;
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input [3:0]         wr_i /*verilator public*/;
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input               rd_i /*verilator public*/;
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//-----------------------------------------------------------------
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// Registers / Wires
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//-----------------------------------------------------------------
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reg [31:0]                  data_o;
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reg                         intr_o;
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// IRQ Status
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wire                        intr_in;
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reg [INTERRUPT_COUNT-1:0]   irq_status;
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reg [INTERRUPT_COUNT-1:0]   irq_mask;
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reg [INTERRUPT_COUNT-1:0]   v_irq_status;
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//-----------------------------------------------------------------
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// Peripheral Register Write
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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begin
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   if (rst_i == 1'b1)
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   begin
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       irq_status       <= {(INTERRUPT_COUNT){1'b0}};
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       irq_mask         <= {(INTERRUPT_COUNT){1'b0}};
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       intr_o           <= 1'b0;
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   end
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   else
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   begin
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       // Get current IRQ status
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       v_irq_status = irq_status;
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       // IRQ0
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       if (intr0_i == 1'b1)
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           v_irq_status[0] = 1'b1;
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       // IRQ1
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       if (intr1_i == 1'b1)
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           v_irq_status[1] = 1'b1;
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       // IRQ2
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       if (intr2_i == 1'b1)
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           v_irq_status[2] = 1'b1;
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       // IRQ3
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       if (intr3_i == 1'b1)
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           v_irq_status[3] = 1'b1;
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       // IRQ4
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       if (intr4_i == 1'b1)
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           v_irq_status[4] = 1'b1;
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       // IRQ5
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       if (intr5_i == 1'b1)
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           v_irq_status[5] = 1'b1;
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       // IRQ6
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       if (intr6_i == 1'b1)
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           v_irq_status[6] = 1'b1;
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       // IRQ7
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       if (intr7_i == 1'b1)
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           v_irq_status[7] = 1'b1;
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       // External interrupts
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       begin : ext_ints_loop
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           integer i;
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           for (i=0; i< EXTERNAL_INTERRUPTS; i=i+1)
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           begin
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               if (intr_ext_i[i] == 1'b1)
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                   v_irq_status[(`IRQ_EXT_FIRST + i)] = 1'b1;
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           end
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       end
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       // Update IRQ status
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       irq_status <= v_irq_status;
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       // Generate interrupt based on masked status
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       intr_o <= ((v_irq_status & irq_mask) != {(INTERRUPT_COUNT){1'b0}}) ? 1'b1 : 1'b0;
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       // Write Cycle
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       if (wr_i != 4'b0000)
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       begin
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           case (addr_i)
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           `IRQ_MASK_SET :
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                irq_mask    <= (irq_mask | data_i[INTERRUPT_COUNT-1:0]);
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           `IRQ_MASK_CLR :
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                irq_mask    <= (irq_mask & ~ (data_i[INTERRUPT_COUNT-1:0]));
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           `IRQ_STATUS : // (IRQ Acknowledge)
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                irq_status  <= (v_irq_status & ~ (data_i[INTERRUPT_COUNT-1:0]));
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           default :
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               ;
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           endcase
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        end
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   end
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end
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//-----------------------------------------------------------------
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// Peripheral Register Read
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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begin
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   if (rst_i == 1'b1)
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   begin
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       data_o       <= 32'h00000000;
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   end
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   else
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   begin
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       // Read cycle?
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       if (rd_i == 1'b1)
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       begin
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           case (addr_i[7:0])
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           `IRQ_MASK_SET :
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                data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
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           `IRQ_MASK_CLR :
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                data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
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           `IRQ_STATUS :
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                data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_status};
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           default :
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                data_o <= 32'h00000000;
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           endcase
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        end
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   end
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end
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endmodule

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